Target/ARM/ARMISelLowering.cpp

1919     unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
6214   unsigned dest    = MI->getOperand(0).getReg();
6215   unsigned ptr     = MI->getOperand(1).getReg();
6216   unsigned oldval  = MI->getOperand(2).getReg();
6217   unsigned newval  = MI->getOperand(3).getReg();
6312   unsigned dest = MI->getOperand(0).getReg();
6313   unsigned ptr = MI->getOperand(1).getReg();
6314   unsigned incr = MI->getOperand(2).getReg();
6407   unsigned dest = MI->getOperand(0).getReg();
6408   unsigned ptr = MI->getOperand(1).getReg();
6409   unsigned incr = MI->getOperand(2).getReg();
6527   unsigned destlo = MI->getOperand(0).getReg();
6528   unsigned desthi = MI->getOperand(1).getReg();
6529   unsigned ptr = MI->getOperand(offset+2).getReg();
6530   unsigned vallo = MI->getOperand(offset+3).getReg();
6531   unsigned valhi = MI->getOperand(offset+4).getReg();
6623     StoreLo = MI->getOperand(5).getReg();
6624     StoreHi = MI->getOperand(6).getReg();
6702   unsigned destlo = MI->getOperand(0).getReg();
6703   unsigned desthi = MI->getOperand(1).getReg();
6704   unsigned ptr = MI->getOperand(2).getReg();
7229         DefRegs[OI->getReg()] = true;
7384   unsigned dest = MI->getOperand(0).getReg();
7385   unsigned src = MI->getOperand(1).getReg();
7831       .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
7846             TII->get(ARM::PHI), MI->getOperand(0).getReg())
7847       .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
7848       .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
7863     unsigned LHS1 = MI->getOperand(1).getReg();
7864     unsigned LHS2 = MI->getOperand(2).getReg();
7873       unsigned RHS1 = MI->getOperand(3).getReg();
7874       unsigned RHS2 = MI->getOperand(4).getReg();
7930     unsigned int ABSSrcReg = MI->getOperand(1).getReg();
7931     unsigned int ABSDstReg = MI->getOperand(0).getReg();
8035     if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) {
8049     assert(!MI->getOperand(ccOutIdx).getReg() &&