Searched refs:getReg (Results 126 - 150 of 244) sorted by relevance

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/freebsd-10.2-release/contrib/llvm/include/llvm/MC/
H A DMCInstrDesc.h300 RI.isSubRegisterEq(PC, MI.getOperand(i).getReg()))
561 RI.isSubRegisterEq(Reg, MI.getOperand(i).getReg()))
H A DMCInst.h62 /// getReg - Returns the register number.
63 unsigned getReg() const { function in class:llvm::MCOperand
/freebsd-10.2-release/contrib/llvm/lib/Target/Hexagon/
H A DHexagonAsmPrinter.cpp82 O << HexagonInstPrinter::getRegisterName(MO.getReg());
258 O << HexagonInstPrinter::getRegisterName(MO1.getReg())
H A DHexagonCallingConvLower.cpp102 addLoc(CCValAssign::getReg(0, MVT::i32, Reg, MVT::i32,
108 addLoc(CCValAssign::getReg(0, MVT::i64, Reg, MVT::i64,
H A DHexagonInstrInfo.cpp86 return MI->getOperand(0).getReg();
110 return MI->getOperand(2).getReg();
160 get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
165 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
355 SrcReg = MI->getOperand(1).getReg();
364 SrcReg = MI->getOperand(1).getReg();
373 SrcReg = MI->getOperand(1).getReg();
394 SrcReg2 = MI->getOperand(2).getReg();
874 MI->getOperand(oper+1).ChangeToRegister(MO.getReg(), MO.isDef(),
917 MI->getOperand(oper+1).ChangeToRegister(PredMO.getReg(), PredM
[all...]
H A DHexagonFixupHwLoops.cpp170 .addReg(MII->getOperand(1).getReg());
/freebsd-10.2-release/contrib/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.cpp301 unsigned NegSizeReg = MI.getOperand(1).getReg();
327 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
352 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
384 unsigned SrcReg = MI.getOperand(0).getReg();
428 unsigned DestReg = MI.getOperand(0).getReg();
467 unsigned SrcReg = MI.getOperand(0).getReg();
492 unsigned DestReg = MI.getOperand(0).getReg();
680 unsigned StackReg = MI.getOperand(FIOperandNum).getReg();
H A DPPCBranchSelector.cpp164 unsigned CRReg = I->getOperand(1).getReg();
/freebsd-10.2-release/contrib/llvm/lib/Target/R600/
H A DAMDGPUAsmPrinter.cpp126 unsigned HWReg = RI->getEncodingValue(MO.getReg()) & 0xff;
195 reg = MO.getReg();
/freebsd-10.2-release/contrib/llvm/lib/Target/R600/InstPrinter/
H A DAMDGPUInstPrinter.cpp88 switch (Op.getReg()) {
94 printRegOperand(Op.getReg(), O);
/freebsd-10.2-release/contrib/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.cpp178 unsigned SrcReg = MI.getOperand(2).getReg();
190 unsigned DestReg = MI.getOperand(0).getReg();
/freebsd-10.2-release/contrib/llvm/lib/CodeGen/
H A DPostRASchedulerList.cpp455 if (LiveRegs.test(MO.getReg())) {
464 const unsigned SuperReg = MO.getReg();
504 unsigned Reg = MO.getReg();
523 unsigned Reg = MO.getReg();
558 unsigned Reg = MO.getReg();
H A DTailDuplication.cpp282 unsigned Dst = Copy->getOperand(0).getReg();
283 unsigned Src = Copy->getOperand(1).getReg();
361 unsigned SrcReg = MI.getOperand(i).getReg();
390 unsigned DefReg = MI->getOperand(0).getReg();
393 unsigned SrcReg = MI->getOperand(SrcOpIdx).getReg();
427 unsigned Reg = MO.getReg();
474 unsigned Reg = MO0.getReg();
H A DSpiller.cpp111 if (!op.isReg() || op.getReg() != li->reg)
/freebsd-10.2-release/contrib/llvm/lib/Target/AArch64/InstPrinter/
H A DAArch64InstPrinter.cpp328 unsigned Reg0 = MI->getOperand(0).getReg();
329 unsigned Reg1 = MI->getOperand(1).getReg();
373 unsigned Reg = MI->getOperand(OpNo).getReg();
383 unsigned Reg = Op.getReg();
520 unsigned Reg = MI->getOperand(OpNum).getReg();
/freebsd-10.2-release/contrib/llvm/lib/Target/XCore/
H A DXCoreFrameLowering.cpp195 unsigned Reg = MRI->getDwarfRegNum(CSI.getReg(), true);
286 MBB.addLiveIn(it->getReg());
288 unsigned Reg = it->getReg();
314 unsigned Reg = it->getReg();
316 TII.loadRegFromStackSlot(MBB, MI, it->getReg(), it->getFrameIdx(),
/freebsd-10.2-release/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGRRList.cpp289 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
534 SUnit *RegDef = LiveRegDefs[I->getReg()]; (void)RegDef;
537 LiveRegDefs[I->getReg()] = I->getSUnit();
538 if (!LiveRegGens[I->getReg()]) {
540 LiveRegGens[I->getReg()] = SU;
741 // LiveRegDegs[I->getReg()] != SU when SU is a two-address node.
742 if (I->isAssignedRegDep() && LiveRegDefs[I->getReg()] == SU) {
745 LiveRegDefs[I->getReg()] = NULL;
746 LiveRegGens[I->getReg()] = NULL;
747 releaseInterferences(I->getReg());
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/freebsd-10.2-release/contrib/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp299 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { function
309 uint16_t Register = getReg(Decoder, AArch64::GPR64RegClassID, RegNo);
320 uint16_t Register = getReg(Decoder, AArch64::GPR64xspRegClassID, RegNo);
331 uint16_t Register = getReg(Decoder, AArch64::GPR32RegClassID, RegNo);
342 uint16_t Register = getReg(Decoder, AArch64::GPR32wspRegClassID, RegNo);
353 uint16_t Register = getReg(Decoder, AArch64::FPR8RegClassID, RegNo);
364 uint16_t Register = getReg(Decoder, AArch64::FPR16RegClassID, RegNo);
376 uint16_t Register = getReg(Decoder, AArch64::FPR32RegClassID, RegNo);
387 uint16_t Register = getReg(Decoder, AArch64::FPR64RegClassID, RegNo);
407 uint16_t Register = getReg(Decode
[all...]
/freebsd-10.2-release/contrib/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp2268 return Base.getReg();
2286 unsigned DestReg = MI->getOperand(0).getReg();
2287 unsigned TrueReg = MI->getOperand(1).getReg();
2288 unsigned FalseReg = MI->getOperand(2).getReg();
2334 unsigned SrcReg = MI->getOperand(0).getReg();
2337 unsigned IndexReg = MI->getOperand(3).getReg();
2406 unsigned Dest = MI->getOperand(0).getReg();
2410 unsigned BitShift = (IsSubWord ? MI->getOperand(4).getReg() : 0);
2411 unsigned NegBitShift = (IsSubWord ? MI->getOperand(5).getReg() : 0);
2432 MRI.createVirtualRegister(RC) : Src2.getReg());
[all...]
/freebsd-10.2-release/contrib/llvm/lib/Target/X86/
H A DX86InstrInfo.cpp1474 SrcReg = MI.getOperand(1).getReg();
1475 DstReg = MI.getOperand(0).getReg();
1507 MI->getOperand(Op+2).getReg() == 0 &&
1578 return MI->getOperand(0).getReg();
1600 return MI->getOperand(X86::AddrNumOperands).getReg();
1673 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
1675 unsigned BaseReg = MI->getOperand(1).getReg();
1691 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
1696 unsigned BaseReg = MI->getOperand(1).getReg();
1733 if (MO.getReg()
[all...]
/freebsd-10.2-release/contrib/llvm/lib/Target/AArch64/
H A DAArch64MCInstLower.cpp107 MCOp = MCOperand::CreateReg(MO.getReg());
/freebsd-10.2-release/contrib/llvm/lib/Target/Mips/
H A DMips16InstrInfo.cpp349 if (MO.isReg() && MO.getReg() != 0 && !MO.isDef() &&
350 !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
351 Candidates.reset(MO.getReg());
367 DefReg = MO.getReg();
H A DMipsMCInstLower.cpp137 return MCOperand::CreateReg(MO.getReg());
/freebsd-10.2-release/contrib/llvm/lib/Target/R600/MCTargetDesc/
H A DSIMCCodeEmitter.cpp173 return MRI.getEncodingValue(MO.getReg());
/freebsd-10.2-release/contrib/llvm/lib/Target/Sparc/MCTargetDesc/
H A DSparcMCCodeEmitter.cpp105 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());

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