Target/X86/X86InstrInfo.cpp

1474     SrcReg = MI.getOperand(1).getReg();
1475     DstReg = MI.getOperand(0).getReg();
1507       MI->getOperand(Op+2).getReg() == 0 &&
1578       return MI->getOperand(0).getReg();
1600       return MI->getOperand(X86::AddrNumOperands).getReg();
1673         MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
1675       unsigned BaseReg = MI->getOperand(1).getReg();
1691         MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
1696       unsigned BaseReg = MI->getOperand(1).getReg();
1733       if (MO.getReg() == X86::EFLAGS) {
1779       if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
1813   NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
1822         MO.getReg() == X86::EFLAGS && !MO.isDead()) {
1862   unsigned SrcReg = Src.getReg();
1884     NewSrc = getX86SubSuperRegister(Src.getReg(), MVT::i64);
1931   unsigned Dest = MI->getOperand(0).getReg();
1932   unsigned Src = MI->getOperand(1).getReg();
1986     unsigned Src2 = MI->getOperand(2).getReg();
2073     unsigned B = MI->getOperand(1).getReg();
2074     unsigned C = MI->getOperand(2).getReg();
2085     unsigned B = MI->getOperand(1).getReg();
2086     unsigned C = MI->getOperand(2).getReg();
2103     if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
2104         !MF.getRegInfo().constrainRegClass(Src.getReg(),
2133     if (ImplicitOp.getReg() != 0)
2171       if (ImplicitOp.getReg() != 0)
2202       if (ImplicitOp.getReg() != 0)
2245       if (ImplicitOp.getReg() != 0)
2247       if (ImplicitOp2.getReg() != 0)
2265       unsigned Src2 = MI->getOperand(2).getReg();
2269                         Src.getReg(), Src.isKill(), Src2, isKill2);
2307       if (ImplicitOp.getReg() != 0)
2332       LV->replaceKillInstruction(Src.getReg(), MI, NewMI);
2334       LV->replaceKillInstruction(Dest.getReg(), MI, NewMI);
3297     SrcReg = MI->getOperand(0).getReg();
3307     SrcReg = MI->getOperand(1).getReg();
3316     SrcReg = MI->getOperand(1).getReg();
3317     SrcReg2 = MI->getOperand(2).getReg();
3328     SrcReg = MI->getOperand(1).getReg();
3337     SrcReg = MI->getOperand(0).getReg();
3338     SrcReg2 = MI->getOperand(1).getReg();
3346     SrcReg = MI->getOperand(0).getReg();
3347     if (MI->getOperand(1).getReg() != SrcReg) return false;
3374       ((OI->getOperand(1).getReg() == SrcReg &&
3375         OI->getOperand(2).getReg() == SrcReg2) ||
3376        (OI->getOperand(1).getReg() == SrcReg2 &&
3377         OI->getOperand(2).getReg() == SrcReg)))
3394       OI->getOperand(1).getReg() == SrcReg &&
3514     if (!MRI->use_nodbg_empty(CmpInstr->getOperand(0).getReg()))
3605   bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
3606                     Sub->getOperand(2).getReg() == SrcReg);
3670         unsigned DstReg = Instr.getOperand(0).getReg();
3724     if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
3772       unsigned Reg = MO.getReg();
3824   unsigned Reg = MIB->getOperand(0).getReg();
3831   assert(MIB->getOperand(1).getReg() == Reg &&
3832          MIB->getOperand(2).getReg() == Reg && "Misplaced operand");
3971       MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
4027         unsigned DstReg = NewMI->getOperand(0).getReg();
4096   unsigned Reg = MO.getReg();
4168   if (MO.isUndef() && TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
4178   unsigned Reg = MI->getOperand(OpNum).getReg();
4240       assert(MO.getReg() && "patchpoint can only fold a vreg operand");
4242       const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(MO.getReg());
4433         MF.getRegInfo().getRegClass(LoadMI->getOperand(0).getReg())->getSize()
4440         MF.getRegInfo().getRegClass(LoadMI->getOperand(0).getReg())->getSize()
4585     MIB.addReg(MO.getReg(),
4617       MO1.ChangeToRegister(MO0.getReg(), false);