CodeGen/SelectionDAG/ScheduleDAGRRList.cpp

289       unsigned Reg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
534       SUnit *RegDef = LiveRegDefs[I->getReg()]; (void)RegDef;
537       LiveRegDefs[I->getReg()] = I->getSUnit();
538       if (!LiveRegGens[I->getReg()]) {
540         LiveRegGens[I->getReg()] = SU;
741     // LiveRegDegs[I->getReg()] != SU when SU is a two-address node.
742     if (I->isAssignedRegDep() && LiveRegDefs[I->getReg()] == SU) {
745       LiveRegDefs[I->getReg()] = NULL;
746       LiveRegGens[I->getReg()] = NULL;
747       releaseInterferences(I->getReg());
811     if (I->isAssignedRegDep() && SU == LiveRegGens[I->getReg()]){
813       assert(LiveRegDefs[I->getReg()] == I->getSUnit() &&
816       LiveRegDefs[I->getReg()] = NULL;
817       LiveRegGens[I->getReg()] = NULL;
818       releaseInterferences(I->getReg());
853       if (!LiveRegDefs[I->getReg()])
857       LiveRegDefs[I->getReg()] = SU;
858       if (LiveRegGens[I->getReg()] == NULL ||
859           I->getSUnit()->getHeight() < LiveRegGens[I->getReg()]->getHeight())
860         LiveRegGens[I->getReg()] = I->getSUnit();
1266     if (I->isAssignedRegDep() && LiveRegDefs[I->getReg()] != SU)
1267       CheckForLiveRegDef(I->getSUnit(), I->getReg(), LiveRegDefs,
1289             unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
2232         cast<RegisterSDNode>(PredSU->getNode()->getOperand(1))->getReg();
2254         cast<RegisterSDNode>(SuccSU->getNode()->getOperand(1))->getReg();
2727       if (RegMask && MachineOperand::clobbersPhysReg(RegMask, PI->getReg()) &&
2736           if (TRI->regsOverlap(*ImpDef, PI->getReg()) &&
2831             (cast<RegisterSDNode>(N->getOperand(1))->getReg()))
2856             (cast<RegisterSDNode>(N->getOperand(1))->getReg()))