Searched refs:CVMX_ADD_IO_SEG (Results 26 - 50 of 63) sorted by relevance

123

/freebsd-10.2-release/sys/contrib/octeon-sdk/
H A Dcvmx-dpi-defs.h61 return CVMX_ADD_IO_SEG(0x0001DF0000000000ull);
64 #define CVMX_DPI_BIST_STATUS (CVMX_ADD_IO_SEG(0x0001DF0000000000ull))
72 return CVMX_ADD_IO_SEG(0x0001DF0000000040ull);
75 #define CVMX_DPI_CTL (CVMX_ADD_IO_SEG(0x0001DF0000000040ull))
87 return CVMX_ADD_IO_SEG(0x0001DF0000000300ull) + ((offset) & 7) * 8;
90 #define CVMX_DPI_DMAX_COUNTS(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000300ull) + ((offset) & 7) * 8)
102 return CVMX_ADD_IO_SEG(0x0001DF0000000200ull) + ((offset) & 7) * 8;
105 #define CVMX_DPI_DMAX_DBELL(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000200ull) + ((offset) & 7) * 8)
116 return CVMX_ADD_IO_SEG(0x0001DF0000000A80ull) + ((offset) & 7) * 8;
119 #define CVMX_DPI_DMAX_ERR_RSP_STATUS(offset) (CVMX_ADD_IO_SEG(
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H A Dcvmx-uahcx-defs.h65 return CVMX_ADD_IO_SEG(0x00016F0000000028ull);
68 #define CVMX_UAHCX_EHCI_ASYNCLISTADDR(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000028ull))
80 return CVMX_ADD_IO_SEG(0x00016F0000000050ull);
83 #define CVMX_UAHCX_EHCI_CONFIGFLAG(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000050ull))
95 return CVMX_ADD_IO_SEG(0x00016F0000000020ull);
98 #define CVMX_UAHCX_EHCI_CTRLDSSEGMENT(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000020ull))
110 return CVMX_ADD_IO_SEG(0x00016F000000001Cull);
113 #define CVMX_UAHCX_EHCI_FRINDEX(block_id) (CVMX_ADD_IO_SEG(0x00016F000000001Cull))
125 return CVMX_ADD_IO_SEG(0x00016F0000000000ull);
128 #define CVMX_UAHCX_EHCI_HCCAPBASE(block_id) (CVMX_ADD_IO_SEG(
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H A Dcvmx-rad-defs.h61 return CVMX_ADD_IO_SEG(0x0001180070001000ull);
64 #define CVMX_RAD_MEM_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180070001000ull))
72 return CVMX_ADD_IO_SEG(0x0001180070001008ull);
75 #define CVMX_RAD_MEM_DEBUG1 (CVMX_ADD_IO_SEG(0x0001180070001008ull))
83 return CVMX_ADD_IO_SEG(0x0001180070001010ull);
86 #define CVMX_RAD_MEM_DEBUG2 (CVMX_ADD_IO_SEG(0x0001180070001010ull))
94 return CVMX_ADD_IO_SEG(0x0001180070000080ull);
97 #define CVMX_RAD_REG_BIST_RESULT (CVMX_ADD_IO_SEG(0x0001180070000080ull))
105 return CVMX_ADD_IO_SEG(0x0001180070000008ull);
108 #define CVMX_RAD_REG_CMD_BUF (CVMX_ADD_IO_SEG(
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H A Dcvmx-pemx-defs.h65 return CVMX_ADD_IO_SEG(0x00011800C00000A8ull) + (((offset) & 15) + ((block_id) & 1) * 0x200000ull) * 8;
68 #define CVMX_PEMX_BAR1_INDEXX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C00000A8ull) + (((offset) & 15) + ((block_id) & 1) * 0x200000ull) * 8)
79 return CVMX_ADD_IO_SEG(0x00011800C0000130ull) + ((block_id) & 1) * 0x1000000ull;
82 #define CVMX_PEMX_BAR2_MASK(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000130ull) + ((block_id) & 1) * 0x1000000ull)
94 return CVMX_ADD_IO_SEG(0x00011800C0000128ull) + ((block_id) & 1) * 0x1000000ull;
97 #define CVMX_PEMX_BAR_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000128ull) + ((block_id) & 1) * 0x1000000ull)
109 return CVMX_ADD_IO_SEG(0x00011800C0000018ull) + ((block_id) & 1) * 0x1000000ull;
112 #define CVMX_PEMX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000018ull) + ((block_id) & 1) * 0x1000000ull)
124 return CVMX_ADD_IO_SEG(0x00011800C0000420ull) + ((block_id) & 1) * 0x1000000ull;
127 #define CVMX_PEMX_BIST_STATUS2(block_id) (CVMX_ADD_IO_SEG(
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H A Dcvmx-iob-defs.h55 #define CVMX_IOB_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011800F00007F8ull))
56 #define CVMX_IOB_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011800F0000050ull))
63 return CVMX_ADD_IO_SEG(0x00011800F0000028ull);
66 #define CVMX_IOB_DWB_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000028ull))
68 #define CVMX_IOB_FAU_TIMEOUT (CVMX_ADD_IO_SEG(0x00011800F0000000ull))
75 return CVMX_ADD_IO_SEG(0x00011800F0000010ull);
78 #define CVMX_IOB_I2C_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000010ull))
80 #define CVMX_IOB_INB_CONTROL_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000078ull))
81 #define CVMX_IOB_INB_CONTROL_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F0000088ull))
82 #define CVMX_IOB_INB_DATA_MATCH (CVMX_ADD_IO_SEG(
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H A Dcvmx-uctlx-defs.h65 return CVMX_ADD_IO_SEG(0x000118006F0000A0ull);
68 #define CVMX_UCTLX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x000118006F0000A0ull))
80 return CVMX_ADD_IO_SEG(0x000118006F000000ull);
83 #define CVMX_UCTLX_CLK_RST_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000000ull))
95 return CVMX_ADD_IO_SEG(0x000118006F000080ull);
98 #define CVMX_UCTLX_EHCI_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000080ull))
110 return CVMX_ADD_IO_SEG(0x000118006F0000A8ull);
113 #define CVMX_UCTLX_EHCI_FLA(block_id) (CVMX_ADD_IO_SEG(0x000118006F0000A8ull))
125 return CVMX_ADD_IO_SEG(0x000118006F000090ull);
128 #define CVMX_UCTLX_ERTO_CTL(block_id) (CVMX_ADD_IO_SEG(
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H A Dcvmx-usbcx-defs.h65 return CVMX_ADD_IO_SEG(0x00016F0010000818ull) + ((block_id) & 1) * 0x100000000000ull;
68 #define CVMX_USBCX_DAINT(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000818ull) + ((block_id) & 1) * 0x100000000000ull)
80 return CVMX_ADD_IO_SEG(0x00016F001000081Cull) + ((block_id) & 1) * 0x100000000000ull;
83 #define CVMX_USBCX_DAINTMSK(block_id) (CVMX_ADD_IO_SEG(0x00016F001000081Cull) + ((block_id) & 1) * 0x100000000000ull)
95 return CVMX_ADD_IO_SEG(0x00016F0010000800ull) + ((block_id) & 1) * 0x100000000000ull;
98 #define CVMX_USBCX_DCFG(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000800ull) + ((block_id) & 1) * 0x100000000000ull)
110 return CVMX_ADD_IO_SEG(0x00016F0010000804ull) + ((block_id) & 1) * 0x100000000000ull;
113 #define CVMX_USBCX_DCTL(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000804ull) + ((block_id) & 1) * 0x100000000000ull)
125 return CVMX_ADD_IO_SEG(0x00016F0010000900ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32;
128 #define CVMX_USBCX_DIEPCTLX(offset, block_id) (CVMX_ADD_IO_SEG(
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H A Dcvmx-dfa-defs.h61 return CVMX_ADD_IO_SEG(0x00011800370007F0ull);
64 #define CVMX_DFA_BIST0 (CVMX_ADD_IO_SEG(0x00011800370007F0ull))
72 return CVMX_ADD_IO_SEG(0x00011800370007F8ull);
75 #define CVMX_DFA_BIST1 (CVMX_ADD_IO_SEG(0x00011800370007F8ull))
83 return CVMX_ADD_IO_SEG(0x00011800300007F0ull);
86 #define CVMX_DFA_BST0 (CVMX_ADD_IO_SEG(0x00011800300007F0ull))
94 return CVMX_ADD_IO_SEG(0x00011800300007F8ull);
97 #define CVMX_DFA_BST1 (CVMX_ADD_IO_SEG(0x00011800300007F8ull))
105 return CVMX_ADD_IO_SEG(0x0001180030000000ull);
108 #define CVMX_DFA_CFG (CVMX_ADD_IO_SEG(
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H A Dcvmx-npi-defs.h69 return CVMX_ADD_IO_SEG(0x00011F0000000070ull) + ((offset) & 3) * 16;
72 #define CVMX_NPI_BASE_ADDR_INPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000070ull) + ((offset) & 3) * 16)
88 return CVMX_ADD_IO_SEG(0x00011F00000000B8ull) + ((offset) & 3) * 8;
91 #define CVMX_NPI_BASE_ADDR_OUTPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F00000000B8ull) + ((offset) & 3) * 8)
99 return CVMX_ADD_IO_SEG(0x00011F00000003F8ull);
102 #define CVMX_NPI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F00000003F8ull))
118 return CVMX_ADD_IO_SEG(0x00011F00000000E0ull) + ((offset) & 3) * 8;
121 #define CVMX_NPI_BUFF_SIZE_OUTPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F00000000E0ull) + ((offset) & 3) * 8)
129 return CVMX_ADD_IO_SEG(0x00011F0000000218ull);
132 #define CVMX_NPI_COMP_CTL (CVMX_ADD_IO_SEG(
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H A Dcvmx-lmcx-defs.h63 return CVMX_ADD_IO_SEG(0x00011800880000F0ull) + ((block_id) & 1) * 0x60000000ull;
66 #define CVMX_LMCX_BIST_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880000F0ull) + ((block_id) & 1) * 0x60000000ull)
76 return CVMX_ADD_IO_SEG(0x00011800880000F8ull) + ((block_id) & 1) * 0x60000000ull;
79 #define CVMX_LMCX_BIST_RESULT(block_id) (CVMX_ADD_IO_SEG(0x00011800880000F8ull) + ((block_id) & 1) * 0x60000000ull)
91 return CVMX_ADD_IO_SEG(0x0001180088000220ull) + ((block_id) & 3) * 0x1000000ull;
94 #define CVMX_LMCX_CHAR_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000220ull) + ((block_id) & 3) * 0x1000000ull)
106 return CVMX_ADD_IO_SEG(0x0001180088000228ull) + ((block_id) & 3) * 0x1000000ull;
109 #define CVMX_LMCX_CHAR_MASK0(block_id) (CVMX_ADD_IO_SEG(0x0001180088000228ull) + ((block_id) & 3) * 0x1000000ull)
121 return CVMX_ADD_IO_SEG(0x0001180088000230ull) + ((block_id) & 3) * 0x1000000ull;
124 #define CVMX_LMCX_CHAR_MASK1(block_id) (CVMX_ADD_IO_SEG(
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H A Dcvmx-ciu2-defs.h61 return CVMX_ADD_IO_SEG(0x00010701080C0800ull) + ((block_id) & 1) * 0x200000ull;
64 #define CVMX_CIU2_ACK_IOX_INT(block_id) (CVMX_ADD_IO_SEG(0x00010701080C0800ull) + ((block_id) & 1) * 0x200000ull)
72 return CVMX_ADD_IO_SEG(0x00010701000C0000ull) + ((block_id) & 31) * 0x200000ull;
75 #define CVMX_CIU2_ACK_PPX_IP2(block_id) (CVMX_ADD_IO_SEG(0x00010701000C0000ull) + ((block_id) & 31) * 0x200000ull)
83 return CVMX_ADD_IO_SEG(0x00010701000C0200ull) + ((block_id) & 31) * 0x200000ull;
86 #define CVMX_CIU2_ACK_PPX_IP3(block_id) (CVMX_ADD_IO_SEG(0x00010701000C0200ull) + ((block_id) & 31) * 0x200000ull)
94 return CVMX_ADD_IO_SEG(0x00010701000C0400ull) + ((block_id) & 31) * 0x200000ull;
97 #define CVMX_CIU2_ACK_PPX_IP4(block_id) (CVMX_ADD_IO_SEG(0x00010701000C0400ull) + ((block_id) & 31) * 0x200000ull)
105 return CVMX_ADD_IO_SEG(0x0001070108097800ull) + ((block_id) & 1) * 0x200000ull;
108 #define CVMX_CIU2_EN_IOX_INT_GPIO(block_id) (CVMX_ADD_IO_SEG(
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H A Dcvmx-l2d-defs.h61 return CVMX_ADD_IO_SEG(0x0001180080000780ull);
64 #define CVMX_L2D_BST0 (CVMX_ADD_IO_SEG(0x0001180080000780ull))
72 return CVMX_ADD_IO_SEG(0x0001180080000788ull);
75 #define CVMX_L2D_BST1 (CVMX_ADD_IO_SEG(0x0001180080000788ull))
83 return CVMX_ADD_IO_SEG(0x0001180080000790ull);
86 #define CVMX_L2D_BST2 (CVMX_ADD_IO_SEG(0x0001180080000790ull))
94 return CVMX_ADD_IO_SEG(0x0001180080000798ull);
97 #define CVMX_L2D_BST3 (CVMX_ADD_IO_SEG(0x0001180080000798ull))
105 return CVMX_ADD_IO_SEG(0x0001180080000010ull);
108 #define CVMX_L2D_ERR (CVMX_ADD_IO_SEG(
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H A Dcvmx-agl-defs.h61 return CVMX_ADD_IO_SEG(0x00011800E0000518ull);
64 #define CVMX_AGL_GMX_BAD_REG (CVMX_ADD_IO_SEG(0x00011800E0000518ull))
72 return CVMX_ADD_IO_SEG(0x00011800E0000400ull);
75 #define CVMX_AGL_GMX_BIST (CVMX_ADD_IO_SEG(0x00011800E0000400ull))
83 return CVMX_ADD_IO_SEG(0x00011800E00007F0ull);
86 #define CVMX_AGL_GMX_DRV_CTL (CVMX_ADD_IO_SEG(0x00011800E00007F0ull))
94 return CVMX_ADD_IO_SEG(0x00011800E00007F8ull);
97 #define CVMX_AGL_GMX_INF_MODE (CVMX_ADD_IO_SEG(0x00011800E00007F8ull))
110 return CVMX_ADD_IO_SEG(0x00011800E0000010ull) + ((offset) & 1) * 2048;
113 #define CVMX_AGL_GMX_PRTX_CFG(offset) (CVMX_ADD_IO_SEG(
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H A Dcvmx-sriox-defs.h62 return CVMX_ADD_IO_SEG(0x00011800C8000148ull) + ((block_id) & 3) * 0x1000000ull;
65 #define CVMX_SRIOX_ACC_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000148ull) + ((block_id) & 3) * 0x1000000ull)
74 return CVMX_ADD_IO_SEG(0x00011800C8000200ull) + ((block_id) & 3) * 0x1000000ull;
77 #define CVMX_SRIOX_ASMBLY_ID(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000200ull) + ((block_id) & 3) * 0x1000000ull)
86 return CVMX_ADD_IO_SEG(0x00011800C8000208ull) + ((block_id) & 3) * 0x1000000ull;
89 #define CVMX_SRIOX_ASMBLY_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000208ull) + ((block_id) & 3) * 0x1000000ull)
98 return CVMX_ADD_IO_SEG(0x00011800C8000310ull) + ((block_id) & 3) * 0x1000000ull;
101 #define CVMX_SRIOX_BELL_RESP_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000310ull) + ((block_id) & 3) * 0x1000000ull)
110 return CVMX_ADD_IO_SEG(0x00011800C8000108ull) + ((block_id) & 3) * 0x1000000ull;
113 #define CVMX_SRIOX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(
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H A Dcvmx-l2c-defs.h61 return CVMX_ADD_IO_SEG(0x0001180080800030ull);
64 #define CVMX_L2C_BIG_CTL (CVMX_ADD_IO_SEG(0x0001180080800030ull))
72 return CVMX_ADD_IO_SEG(0x00011800808007F8ull);
75 #define CVMX_L2C_BST (CVMX_ADD_IO_SEG(0x00011800808007F8ull))
83 return CVMX_ADD_IO_SEG(0x00011800800007F8ull);
86 #define CVMX_L2C_BST0 (CVMX_ADD_IO_SEG(0x00011800800007F8ull))
94 return CVMX_ADD_IO_SEG(0x00011800800007F0ull);
97 #define CVMX_L2C_BST1 (CVMX_ADD_IO_SEG(0x00011800800007F0ull))
105 return CVMX_ADD_IO_SEG(0x00011800800007E8ull);
108 #define CVMX_L2C_BST2 (CVMX_ADD_IO_SEG(
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H A Dcvmx-mio-defs.h55 #define CVMX_MIO_BOOT_BIST_STAT (CVMX_ADD_IO_SEG(0x00011800000000F8ull))
62 return CVMX_ADD_IO_SEG(0x00011800000000B8ull);
65 #define CVMX_MIO_BOOT_COMP (CVMX_ADD_IO_SEG(0x00011800000000B8ull))
79 return CVMX_ADD_IO_SEG(0x0001180000000100ull) + ((offset) & 3) * 8;
82 #define CVMX_MIO_BOOT_DMA_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001180000000100ull) + ((offset) & 3) * 8)
96 return CVMX_ADD_IO_SEG(0x0001180000000138ull) + ((offset) & 3) * 8;
99 #define CVMX_MIO_BOOT_DMA_INTX(offset) (CVMX_ADD_IO_SEG(0x0001180000000138ull) + ((offset) & 3) * 8)
113 return CVMX_ADD_IO_SEG(0x0001180000000150ull) + ((offset) & 3) * 8;
116 #define CVMX_MIO_BOOT_DMA_INT_ENX(offset) (CVMX_ADD_IO_SEG(0x0001180000000150ull) + ((offset) & 3) * 8)
130 return CVMX_ADD_IO_SEG(
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H A Dcvmx-ipd-defs.h55 #define CVMX_IPD_1ST_MBUFF_SKIP (CVMX_ADD_IO_SEG(0x00014F0000000000ull))
56 #define CVMX_IPD_1st_NEXT_PTR_BACK (CVMX_ADD_IO_SEG(0x00014F0000000150ull))
57 #define CVMX_IPD_2nd_NEXT_PTR_BACK (CVMX_ADD_IO_SEG(0x00014F0000000158ull))
58 #define CVMX_IPD_BIST_STATUS (CVMX_ADD_IO_SEG(0x00014F00000007F8ull))
65 return CVMX_ADD_IO_SEG(0x00014F0000002000ull) + ((offset) & 63) * 8;
68 #define CVMX_IPD_BPIDX_MBUF_TH(offset) (CVMX_ADD_IO_SEG(0x00014F0000002000ull) + ((offset) & 63) * 8)
76 return CVMX_ADD_IO_SEG(0x00014F0000003000ull) + ((offset) & 63) * 8;
79 #define CVMX_IPD_BPID_BP_COUNTERX(offset) (CVMX_ADD_IO_SEG(0x00014F0000003000ull) + ((offset) & 63) * 8)
87 return CVMX_ADD_IO_SEG(0x00014F0000000328ull);
90 #define CVMX_IPD_BP_PRT_RED_END (CVMX_ADD_IO_SEG(
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H A Dcvmx-pko-defs.h55 #define CVMX_PKO_MEM_COUNT0 (CVMX_ADD_IO_SEG(0x0001180050001080ull))
56 #define CVMX_PKO_MEM_COUNT1 (CVMX_ADD_IO_SEG(0x0001180050001088ull))
57 #define CVMX_PKO_MEM_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180050001100ull))
58 #define CVMX_PKO_MEM_DEBUG1 (CVMX_ADD_IO_SEG(0x0001180050001108ull))
59 #define CVMX_PKO_MEM_DEBUG10 (CVMX_ADD_IO_SEG(0x0001180050001150ull))
60 #define CVMX_PKO_MEM_DEBUG11 (CVMX_ADD_IO_SEG(0x0001180050001158ull))
61 #define CVMX_PKO_MEM_DEBUG12 (CVMX_ADD_IO_SEG(0x0001180050001160ull))
62 #define CVMX_PKO_MEM_DEBUG13 (CVMX_ADD_IO_SEG(0x0001180050001168ull))
69 return CVMX_ADD_IO_SEG(0x0001180050001170ull);
72 #define CVMX_PKO_MEM_DEBUG14 (CVMX_ADD_IO_SEG(
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H A Dcvmx-gpio-defs.h72 return CVMX_ADD_IO_SEG(0x0001070000000800ull) + ((offset) & 15) * 8;
75 #define CVMX_GPIO_BIT_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000800ull) + ((offset) & 15) * 8)
83 return CVMX_ADD_IO_SEG(0x00010700000008A8ull);
86 #define CVMX_GPIO_BOOT_ENA (CVMX_ADD_IO_SEG(0x00010700000008A8ull))
100 return CVMX_ADD_IO_SEG(0x00010700000008C0ull) + ((offset) & 3) * 8;
103 #define CVMX_GPIO_CLK_GENX(offset) (CVMX_ADD_IO_SEG(0x00010700000008C0ull) + ((offset) & 3) * 8)
115 return CVMX_ADD_IO_SEG(0x00010700000008E0ull) + ((offset) & 1) * 8;
118 #define CVMX_GPIO_CLK_QLMX(offset) (CVMX_ADD_IO_SEG(0x00010700000008E0ull) + ((offset) & 1) * 8)
126 return CVMX_ADD_IO_SEG(0x00010700000008A0ull);
129 #define CVMX_GPIO_DBG_ENA (CVMX_ADD_IO_SEG(
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H A Dcvmx-pescx-defs.h62 return CVMX_ADD_IO_SEG(0x00011800C8000018ull) + ((block_id) & 1) * 0x8000000ull;
65 #define CVMX_PESCX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000018ull) + ((block_id) & 1) * 0x8000000ull)
74 return CVMX_ADD_IO_SEG(0x00011800C8000418ull) + ((block_id) & 1) * 0x8000000ull;
77 #define CVMX_PESCX_BIST_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000418ull) + ((block_id) & 1) * 0x8000000ull)
86 return CVMX_ADD_IO_SEG(0x00011800C8000030ull) + ((block_id) & 1) * 0x8000000ull;
89 #define CVMX_PESCX_CFG_RD(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000030ull) + ((block_id) & 1) * 0x8000000ull)
98 return CVMX_ADD_IO_SEG(0x00011800C8000028ull) + ((block_id) & 1) * 0x8000000ull;
101 #define CVMX_PESCX_CFG_WR(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000028ull) + ((block_id) & 1) * 0x8000000ull)
110 return CVMX_ADD_IO_SEG(0x00011800C8000098ull) + ((block_id) & 1) * 0x8000000ull;
113 #define CVMX_PESCX_CPL_LUT_VALID(block_id) (CVMX_ADD_IO_SEG(
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H A Dcvmx-rnm-defs.h55 #define CVMX_RNM_BIST_STATUS (CVMX_ADD_IO_SEG(0x0001180040000008ull))
56 #define CVMX_RNM_CTL_STATUS (CVMX_ADD_IO_SEG(0x0001180040000000ull))
63 return CVMX_ADD_IO_SEG(0x0001180040000018ull);
66 #define CVMX_RNM_EER_DBG (CVMX_ADD_IO_SEG(0x0001180040000018ull))
74 return CVMX_ADD_IO_SEG(0x0001180040000010ull);
77 #define CVMX_RNM_EER_KEY (CVMX_ADD_IO_SEG(0x0001180040000010ull))
85 return CVMX_ADD_IO_SEG(0x0001180040000020ull);
88 #define CVMX_RNM_SERIAL_NUM (CVMX_ADD_IO_SEG(0x0001180040000020ull))
H A Dcvmx-mixx-defs.h66 return CVMX_ADD_IO_SEG(0x0001070000100078ull) + ((offset) & 1) * 2048;
69 #define CVMX_MIXX_BIST(offset) (CVMX_ADD_IO_SEG(0x0001070000100078ull) + ((offset) & 1) * 2048)
82 return CVMX_ADD_IO_SEG(0x0001070000100020ull) + ((offset) & 1) * 2048;
85 #define CVMX_MIXX_CTL(offset) (CVMX_ADD_IO_SEG(0x0001070000100020ull) + ((offset) & 1) * 2048)
98 return CVMX_ADD_IO_SEG(0x0001070000100050ull) + ((offset) & 1) * 2048;
101 #define CVMX_MIXX_INTENA(offset) (CVMX_ADD_IO_SEG(0x0001070000100050ull) + ((offset) & 1) * 2048)
114 return CVMX_ADD_IO_SEG(0x0001070000100030ull) + ((offset) & 1) * 2048;
117 #define CVMX_MIXX_IRCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100030ull) + ((offset) & 1) * 2048)
130 return CVMX_ADD_IO_SEG(0x0001070000100028ull) + ((offset) & 1) * 2048;
133 #define CVMX_MIXX_IRHWM(offset) (CVMX_ADD_IO_SEG(
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H A Dcvmx-pip-defs.h64 return CVMX_ADD_IO_SEG(0x00011800A0002A00ull) + ((offset) & 3) * 8;
67 #define CVMX_PIP_ALT_SKIP_CFGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002A00ull) + ((offset) & 3) * 8)
75 return CVMX_ADD_IO_SEG(0x00011800A0000038ull);
78 #define CVMX_PIP_BCK_PRS (CVMX_ADD_IO_SEG(0x00011800A0000038ull))
80 #define CVMX_PIP_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011800A0000000ull))
89 return CVMX_ADD_IO_SEG(0x00011800A0002800ull) + ((offset) & 3) * 16;
92 #define CVMX_PIP_BSEL_EXT_CFGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002800ull) + ((offset) & 3) * 16)
102 return CVMX_ADD_IO_SEG(0x00011800A0002808ull) + ((offset) & 3) * 16;
105 #define CVMX_PIP_BSEL_EXT_POSX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002808ull) + ((offset) & 3) * 16)
115 return CVMX_ADD_IO_SEG(
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H A Dcvmx-pow-defs.h61 return CVMX_ADD_IO_SEG(0x00016700000003F8ull);
64 #define CVMX_POW_BIST_STAT (CVMX_ADD_IO_SEG(0x00016700000003F8ull))
72 return CVMX_ADD_IO_SEG(0x0001670000000398ull);
75 #define CVMX_POW_DS_PC (CVMX_ADD_IO_SEG(0x0001670000000398ull))
83 return CVMX_ADD_IO_SEG(0x0001670000000218ull);
86 #define CVMX_POW_ECC_ERR (CVMX_ADD_IO_SEG(0x0001670000000218ull))
94 return CVMX_ADD_IO_SEG(0x0001670000000220ull);
97 #define CVMX_POW_INT_CTL (CVMX_ADD_IO_SEG(0x0001670000000220ull))
115 return CVMX_ADD_IO_SEG(0x0001670000000340ull) + ((offset) & 7) * 8;
118 #define CVMX_POW_IQ_CNTX(offset) (CVMX_ADD_IO_SEG(
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H A Dcvmx-usbnx-defs.h65 return CVMX_ADD_IO_SEG(0x00011800680007F8ull) + ((block_id) & 1) * 0x10000000ull;
68 #define CVMX_USBNX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800680007F8ull) + ((block_id) & 1) * 0x10000000ull)
80 return CVMX_ADD_IO_SEG(0x0001180068000010ull) + ((block_id) & 1) * 0x10000000ull;
83 #define CVMX_USBNX_CLK_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180068000010ull) + ((block_id) & 1) * 0x10000000ull)
95 return CVMX_ADD_IO_SEG(0x00016F0000000800ull) + ((block_id) & 1) * 0x100000000000ull;
98 #define CVMX_USBNX_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000800ull) + ((block_id) & 1) * 0x100000000000ull)
110 return CVMX_ADD_IO_SEG(0x00016F0000000818ull) + ((block_id) & 1) * 0x100000000000ull;
113 #define CVMX_USBNX_DMA0_INB_CHN0(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000818ull) + ((block_id) & 1) * 0x100000000000ull)
125 return CVMX_ADD_IO_SEG(0x00016F0000000820ull) + ((block_id) & 1) * 0x100000000000ull;
128 #define CVMX_USBNX_DMA0_INB_CHN1(block_id) (CVMX_ADD_IO_SEG(
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