contrib/octeon-sdk/cvmx-uahcx-defs.h

65 	return CVMX_ADD_IO_SEG(0x00016F0000000028ull);
68 #define CVMX_UAHCX_EHCI_ASYNCLISTADDR(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000028ull))
80 	return CVMX_ADD_IO_SEG(0x00016F0000000050ull);
83 #define CVMX_UAHCX_EHCI_CONFIGFLAG(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000050ull))
95 	return CVMX_ADD_IO_SEG(0x00016F0000000020ull);
98 #define CVMX_UAHCX_EHCI_CTRLDSSEGMENT(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000020ull))
110 	return CVMX_ADD_IO_SEG(0x00016F000000001Cull);
113 #define CVMX_UAHCX_EHCI_FRINDEX(block_id) (CVMX_ADD_IO_SEG(0x00016F000000001Cull))
125 	return CVMX_ADD_IO_SEG(0x00016F0000000000ull);
128 #define CVMX_UAHCX_EHCI_HCCAPBASE(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000000ull))
140 	return CVMX_ADD_IO_SEG(0x00016F0000000008ull);
143 #define CVMX_UAHCX_EHCI_HCCPARAMS(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000008ull))
155 	return CVMX_ADD_IO_SEG(0x00016F0000000004ull);
158 #define CVMX_UAHCX_EHCI_HCSPARAMS(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000004ull))
170 	return CVMX_ADD_IO_SEG(0x00016F0000000090ull);
173 #define CVMX_UAHCX_EHCI_INSNREG00(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000090ull))
185 	return CVMX_ADD_IO_SEG(0x00016F000000009Cull);
188 #define CVMX_UAHCX_EHCI_INSNREG03(block_id) (CVMX_ADD_IO_SEG(0x00016F000000009Cull))
200 	return CVMX_ADD_IO_SEG(0x00016F00000000A0ull);
203 #define CVMX_UAHCX_EHCI_INSNREG04(block_id) (CVMX_ADD_IO_SEG(0x00016F00000000A0ull))
215 	return CVMX_ADD_IO_SEG(0x00016F00000000E8ull);
218 #define CVMX_UAHCX_EHCI_INSNREG06(block_id) (CVMX_ADD_IO_SEG(0x00016F00000000E8ull))
230 	return CVMX_ADD_IO_SEG(0x00016F00000000ECull);
233 #define CVMX_UAHCX_EHCI_INSNREG07(block_id) (CVMX_ADD_IO_SEG(0x00016F00000000ECull))
245 	return CVMX_ADD_IO_SEG(0x00016F0000000024ull);
248 #define CVMX_UAHCX_EHCI_PERIODICLISTBASE(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000024ull))
260 	return CVMX_ADD_IO_SEG(0x00016F0000000050ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 4;
263 #define CVMX_UAHCX_EHCI_PORTSCX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0000000050ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 4)
275 	return CVMX_ADD_IO_SEG(0x00016F0000000010ull);
278 #define CVMX_UAHCX_EHCI_USBCMD(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000010ull))
290 	return CVMX_ADD_IO_SEG(0x00016F0000000018ull);
293 #define CVMX_UAHCX_EHCI_USBINTR(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000018ull))
305 	return CVMX_ADD_IO_SEG(0x00016F0000000014ull);
308 #define CVMX_UAHCX_EHCI_USBSTS(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000014ull))
320 	return CVMX_ADD_IO_SEG(0x00016F000000042Cull);
323 #define CVMX_UAHCX_OHCI0_HCBULKCURRENTED(block_id) (CVMX_ADD_IO_SEG(0x00016F000000042Cull))
335 	return CVMX_ADD_IO_SEG(0x00016F0000000428ull);
338 #define CVMX_UAHCX_OHCI0_HCBULKHEADED(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000428ull))
350 	return CVMX_ADD_IO_SEG(0x00016F0000000408ull);
353 #define CVMX_UAHCX_OHCI0_HCCOMMANDSTATUS(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000408ull))
365 	return CVMX_ADD_IO_SEG(0x00016F0000000404ull);
368 #define CVMX_UAHCX_OHCI0_HCCONTROL(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000404ull))
380 	return CVMX_ADD_IO_SEG(0x00016F0000000424ull);
383 #define CVMX_UAHCX_OHCI0_HCCONTROLCURRENTED(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000424ull))
395 	return CVMX_ADD_IO_SEG(0x00016F0000000420ull);
398 #define CVMX_UAHCX_OHCI0_HCCONTROLHEADED(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000420ull))
410 	return CVMX_ADD_IO_SEG(0x00016F0000000430ull);
413 #define CVMX_UAHCX_OHCI0_HCDONEHEAD(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000430ull))
425 	return CVMX_ADD_IO_SEG(0x00016F0000000434ull);
428 #define CVMX_UAHCX_OHCI0_HCFMINTERVAL(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000434ull))
440 	return CVMX_ADD_IO_SEG(0x00016F000000043Cull);
443 #define CVMX_UAHCX_OHCI0_HCFMNUMBER(block_id) (CVMX_ADD_IO_SEG(0x00016F000000043Cull))
455 	return CVMX_ADD_IO_SEG(0x00016F0000000438ull);
458 #define CVMX_UAHCX_OHCI0_HCFMREMAINING(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000438ull))
470 	return CVMX_ADD_IO_SEG(0x00016F0000000418ull);
473 #define CVMX_UAHCX_OHCI0_HCHCCA(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000418ull))
485 	return CVMX_ADD_IO_SEG(0x00016F0000000414ull);
488 #define CVMX_UAHCX_OHCI0_HCINTERRUPTDISABLE(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000414ull))
500 	return CVMX_ADD_IO_SEG(0x00016F0000000410ull);
503 #define CVMX_UAHCX_OHCI0_HCINTERRUPTENABLE(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000410ull))
515 	return CVMX_ADD_IO_SEG(0x00016F000000040Cull);
518 #define CVMX_UAHCX_OHCI0_HCINTERRUPTSTATUS(block_id) (CVMX_ADD_IO_SEG(0x00016F000000040Cull))
530 	return CVMX_ADD_IO_SEG(0x00016F0000000444ull);
533 #define CVMX_UAHCX_OHCI0_HCLSTHRESHOLD(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000444ull))
545 	return CVMX_ADD_IO_SEG(0x00016F000000041Cull);
548 #define CVMX_UAHCX_OHCI0_HCPERIODCURRENTED(block_id) (CVMX_ADD_IO_SEG(0x00016F000000041Cull))
560 	return CVMX_ADD_IO_SEG(0x00016F0000000440ull);
563 #define CVMX_UAHCX_OHCI0_HCPERIODICSTART(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000440ull))
575 	return CVMX_ADD_IO_SEG(0x00016F0000000400ull);
578 #define CVMX_UAHCX_OHCI0_HCREVISION(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000400ull))
590 	return CVMX_ADD_IO_SEG(0x00016F0000000448ull);
593 #define CVMX_UAHCX_OHCI0_HCRHDESCRIPTORA(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000448ull))
605 	return CVMX_ADD_IO_SEG(0x00016F000000044Cull);
608 #define CVMX_UAHCX_OHCI0_HCRHDESCRIPTORB(block_id) (CVMX_ADD_IO_SEG(0x00016F000000044Cull))
620 	return CVMX_ADD_IO_SEG(0x00016F0000000450ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 4;
623 #define CVMX_UAHCX_OHCI0_HCRHPORTSTATUSX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0000000450ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 4)
635 	return CVMX_ADD_IO_SEG(0x00016F0000000450ull);
638 #define CVMX_UAHCX_OHCI0_HCRHSTATUS(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000450ull))
650 	return CVMX_ADD_IO_SEG(0x00016F0000000498ull);
653 #define CVMX_UAHCX_OHCI0_INSNREG06(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000498ull))
665 	return CVMX_ADD_IO_SEG(0x00016F000000049Cull);
668 #define CVMX_UAHCX_OHCI0_INSNREG07(block_id) (CVMX_ADD_IO_SEG(0x00016F000000049Cull))