1/***********************license start*************** 2 * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Inc. nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41/** 42 * cvmx-pescx-defs.h 43 * 44 * Configuration and status register (CSR) type definitions for 45 * Octeon pescx. 46 * 47 * This file is auto generated. Do not edit. 48 * 49 * <hr>$Revision$<hr> 50 * 51 */ 52#ifndef __CVMX_PESCX_DEFS_H__ 53#define __CVMX_PESCX_DEFS_H__ 54 55#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56static inline uint64_t CVMX_PESCX_BIST_STATUS(unsigned long block_id) 57{ 58 if (!( 59 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 60 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))))) 61 cvmx_warn("CVMX_PESCX_BIST_STATUS(%lu) is invalid on this chip\n", block_id); 62 return CVMX_ADD_IO_SEG(0x00011800C8000018ull) + ((block_id) & 1) * 0x8000000ull; 63} 64#else 65#define CVMX_PESCX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000018ull) + ((block_id) & 1) * 0x8000000ull) 66#endif 67#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 68static inline uint64_t CVMX_PESCX_BIST_STATUS2(unsigned long block_id) 69{ 70 if (!( 71 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 72 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))))) 73 cvmx_warn("CVMX_PESCX_BIST_STATUS2(%lu) is invalid on this chip\n", block_id); 74 return CVMX_ADD_IO_SEG(0x00011800C8000418ull) + ((block_id) & 1) * 0x8000000ull; 75} 76#else 77#define CVMX_PESCX_BIST_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000418ull) + ((block_id) & 1) * 0x8000000ull) 78#endif 79#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 80static inline uint64_t CVMX_PESCX_CFG_RD(unsigned long block_id) 81{ 82 if (!( 83 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 84 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))))) 85 cvmx_warn("CVMX_PESCX_CFG_RD(%lu) is invalid on this chip\n", block_id); 86 return CVMX_ADD_IO_SEG(0x00011800C8000030ull) + ((block_id) & 1) * 0x8000000ull; 87} 88#else 89#define CVMX_PESCX_CFG_RD(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000030ull) + ((block_id) & 1) * 0x8000000ull) 90#endif 91#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 92static inline uint64_t CVMX_PESCX_CFG_WR(unsigned long block_id) 93{ 94 if (!( 95 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 96 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))))) 97 cvmx_warn("CVMX_PESCX_CFG_WR(%lu) is invalid on this chip\n", block_id); 98 return CVMX_ADD_IO_SEG(0x00011800C8000028ull) + ((block_id) & 1) * 0x8000000ull; 99} 100#else 101#define CVMX_PESCX_CFG_WR(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000028ull) + ((block_id) & 1) * 0x8000000ull) 102#endif 103#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 104static inline uint64_t CVMX_PESCX_CPL_LUT_VALID(unsigned long block_id) 105{ 106 if (!( 107 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 108 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))))) 109 cvmx_warn("CVMX_PESCX_CPL_LUT_VALID(%lu) is invalid on this chip\n", block_id); 110 return CVMX_ADD_IO_SEG(0x00011800C8000098ull) + ((block_id) & 1) * 0x8000000ull; 111} 112#else 113#define CVMX_PESCX_CPL_LUT_VALID(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000098ull) + ((block_id) & 1) * 0x8000000ull) 114#endif 115#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 116static inline uint64_t CVMX_PESCX_CTL_STATUS(unsigned long block_id) 117{ 118 if (!( 119 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 120 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))))) 121 cvmx_warn("CVMX_PESCX_CTL_STATUS(%lu) is invalid on this chip\n", block_id); 122 return CVMX_ADD_IO_SEG(0x00011800C8000000ull) + ((block_id) & 1) * 0x8000000ull; 123} 124#else 125#define CVMX_PESCX_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000000ull) + ((block_id) & 1) * 0x8000000ull) 126#endif 127#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 128static inline uint64_t CVMX_PESCX_CTL_STATUS2(unsigned long block_id) 129{ 130 if (!( 131 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 132 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))))) 133 cvmx_warn("CVMX_PESCX_CTL_STATUS2(%lu) is invalid on this chip\n", block_id); 134 return CVMX_ADD_IO_SEG(0x00011800C8000400ull) + ((block_id) & 1) * 0x8000000ull; 135} 136#else 137#define CVMX_PESCX_CTL_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000400ull) + ((block_id) & 1) * 0x8000000ull) 138#endif 139#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 140static inline uint64_t CVMX_PESCX_DBG_INFO(unsigned long block_id) 141{ 142 if (!( 143 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 144 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))))) 145 cvmx_warn("CVMX_PESCX_DBG_INFO(%lu) is invalid on this chip\n", block_id); 146 return CVMX_ADD_IO_SEG(0x00011800C8000008ull) + ((block_id) & 1) * 0x8000000ull; 147} 148#else 149#define CVMX_PESCX_DBG_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000008ull) + ((block_id) & 1) * 0x8000000ull) 150#endif 151#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 152static inline uint64_t CVMX_PESCX_DBG_INFO_EN(unsigned long block_id) 153{ 154 if (!( 155 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 156 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))))) 157 cvmx_warn("CVMX_PESCX_DBG_INFO_EN(%lu) is invalid on this chip\n", block_id); 158 return CVMX_ADD_IO_SEG(0x00011800C80000A0ull) + ((block_id) & 1) * 0x8000000ull; 159} 160#else 161#define CVMX_PESCX_DBG_INFO_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800C80000A0ull) + ((block_id) & 1) * 0x8000000ull) 162#endif 163#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 164static inline uint64_t CVMX_PESCX_DIAG_STATUS(unsigned long block_id) 165{ 166 if (!( 167 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 168 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))))) 169 cvmx_warn("CVMX_PESCX_DIAG_STATUS(%lu) is invalid on this chip\n", block_id); 170 return CVMX_ADD_IO_SEG(0x00011800C8000020ull) + ((block_id) & 1) * 0x8000000ull; 171} 172#else 173#define CVMX_PESCX_DIAG_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000020ull) + ((block_id) & 1) * 0x8000000ull) 174#endif 175#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 176static inline uint64_t CVMX_PESCX_P2N_BAR0_START(unsigned long block_id) 177{ 178 if (!( 179 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 180 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))))) 181 cvmx_warn("CVMX_PESCX_P2N_BAR0_START(%lu) is invalid on this chip\n", block_id); 182 return CVMX_ADD_IO_SEG(0x00011800C8000080ull) + ((block_id) & 1) * 0x8000000ull; 183} 184#else 185#define CVMX_PESCX_P2N_BAR0_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000080ull) + ((block_id) & 1) * 0x8000000ull) 186#endif 187#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 188static inline uint64_t CVMX_PESCX_P2N_BAR1_START(unsigned long block_id) 189{ 190 if (!( 191 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 192 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))))) 193 cvmx_warn("CVMX_PESCX_P2N_BAR1_START(%lu) is invalid on this chip\n", block_id); 194 return CVMX_ADD_IO_SEG(0x00011800C8000088ull) + ((block_id) & 1) * 0x8000000ull; 195} 196#else 197#define CVMX_PESCX_P2N_BAR1_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000088ull) + ((block_id) & 1) * 0x8000000ull) 198#endif 199#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 200static inline uint64_t CVMX_PESCX_P2N_BAR2_START(unsigned long block_id) 201{ 202 if (!( 203 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 204 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))))) 205 cvmx_warn("CVMX_PESCX_P2N_BAR2_START(%lu) is invalid on this chip\n", block_id); 206 return CVMX_ADD_IO_SEG(0x00011800C8000090ull) + ((block_id) & 1) * 0x8000000ull; 207} 208#else 209#define CVMX_PESCX_P2N_BAR2_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000090ull) + ((block_id) & 1) * 0x8000000ull) 210#endif 211#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 212static inline uint64_t CVMX_PESCX_P2P_BARX_END(unsigned long offset, unsigned long block_id) 213{ 214 if (!( 215 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id <= 1)))) || 216 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))))) 217 cvmx_warn("CVMX_PESCX_P2P_BARX_END(%lu,%lu) is invalid on this chip\n", offset, block_id); 218 return CVMX_ADD_IO_SEG(0x00011800C8000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x800000ull) * 16; 219} 220#else 221#define CVMX_PESCX_P2P_BARX_END(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x800000ull) * 16) 222#endif 223#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 224static inline uint64_t CVMX_PESCX_P2P_BARX_START(unsigned long offset, unsigned long block_id) 225{ 226 if (!( 227 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id <= 1)))) || 228 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))))) 229 cvmx_warn("CVMX_PESCX_P2P_BARX_START(%lu,%lu) is invalid on this chip\n", offset, block_id); 230 return CVMX_ADD_IO_SEG(0x00011800C8000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x800000ull) * 16; 231} 232#else 233#define CVMX_PESCX_P2P_BARX_START(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x800000ull) * 16) 234#endif 235#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 236static inline uint64_t CVMX_PESCX_TLP_CREDITS(unsigned long block_id) 237{ 238 if (!( 239 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 240 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))))) 241 cvmx_warn("CVMX_PESCX_TLP_CREDITS(%lu) is invalid on this chip\n", block_id); 242 return CVMX_ADD_IO_SEG(0x00011800C8000038ull) + ((block_id) & 1) * 0x8000000ull; 243} 244#else 245#define CVMX_PESCX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000038ull) + ((block_id) & 1) * 0x8000000ull) 246#endif 247 248/** 249 * cvmx_pesc#_bist_status 250 * 251 * PESC_BIST_STATUS = PESC Bist Status 252 * 253 * Contains the diffrent interrupt summary bits of the PESC. 254 */ 255union cvmx_pescx_bist_status { 256 uint64_t u64; 257 struct cvmx_pescx_bist_status_s { 258#ifdef __BIG_ENDIAN_BITFIELD 259 uint64_t reserved_13_63 : 51; 260 uint64_t rqdata5 : 1; /**< Rx Queue Data Memory5. */ 261 uint64_t ctlp_or : 1; /**< C-TLP Order Fifo. */ 262 uint64_t ntlp_or : 1; /**< N-TLP Order Fifo. */ 263 uint64_t ptlp_or : 1; /**< P-TLP Order Fifo. */ 264 uint64_t retry : 1; /**< Retry Buffer. */ 265 uint64_t rqdata0 : 1; /**< Rx Queue Data Memory0. */ 266 uint64_t rqdata1 : 1; /**< Rx Queue Data Memory1. */ 267 uint64_t rqdata2 : 1; /**< Rx Queue Data Memory2. */ 268 uint64_t rqdata3 : 1; /**< Rx Queue Data Memory3. */ 269 uint64_t rqdata4 : 1; /**< Rx Queue Data Memory4. */ 270 uint64_t rqhdr1 : 1; /**< Rx Queue Header1. */ 271 uint64_t rqhdr0 : 1; /**< Rx Queue Header0. */ 272 uint64_t sot : 1; /**< SOT Buffer. */ 273#else 274 uint64_t sot : 1; 275 uint64_t rqhdr0 : 1; 276 uint64_t rqhdr1 : 1; 277 uint64_t rqdata4 : 1; 278 uint64_t rqdata3 : 1; 279 uint64_t rqdata2 : 1; 280 uint64_t rqdata1 : 1; 281 uint64_t rqdata0 : 1; 282 uint64_t retry : 1; 283 uint64_t ptlp_or : 1; 284 uint64_t ntlp_or : 1; 285 uint64_t ctlp_or : 1; 286 uint64_t rqdata5 : 1; 287 uint64_t reserved_13_63 : 51; 288#endif 289 } s; 290 struct cvmx_pescx_bist_status_s cn52xx; 291 struct cvmx_pescx_bist_status_cn52xxp1 { 292#ifdef __BIG_ENDIAN_BITFIELD 293 uint64_t reserved_12_63 : 52; 294 uint64_t ctlp_or : 1; /**< C-TLP Order Fifo. */ 295 uint64_t ntlp_or : 1; /**< N-TLP Order Fifo. */ 296 uint64_t ptlp_or : 1; /**< P-TLP Order Fifo. */ 297 uint64_t retry : 1; /**< Retry Buffer. */ 298 uint64_t rqdata0 : 1; /**< Rx Queue Data Memory0. */ 299 uint64_t rqdata1 : 1; /**< Rx Queue Data Memory1. */ 300 uint64_t rqdata2 : 1; /**< Rx Queue Data Memory2. */ 301 uint64_t rqdata3 : 1; /**< Rx Queue Data Memory3. */ 302 uint64_t rqdata4 : 1; /**< Rx Queue Data Memory4. */ 303 uint64_t rqhdr1 : 1; /**< Rx Queue Header1. */ 304 uint64_t rqhdr0 : 1; /**< Rx Queue Header0. */ 305 uint64_t sot : 1; /**< SOT Buffer. */ 306#else 307 uint64_t sot : 1; 308 uint64_t rqhdr0 : 1; 309 uint64_t rqhdr1 : 1; 310 uint64_t rqdata4 : 1; 311 uint64_t rqdata3 : 1; 312 uint64_t rqdata2 : 1; 313 uint64_t rqdata1 : 1; 314 uint64_t rqdata0 : 1; 315 uint64_t retry : 1; 316 uint64_t ptlp_or : 1; 317 uint64_t ntlp_or : 1; 318 uint64_t ctlp_or : 1; 319 uint64_t reserved_12_63 : 52; 320#endif 321 } cn52xxp1; 322 struct cvmx_pescx_bist_status_s cn56xx; 323 struct cvmx_pescx_bist_status_cn52xxp1 cn56xxp1; 324}; 325typedef union cvmx_pescx_bist_status cvmx_pescx_bist_status_t; 326 327/** 328 * cvmx_pesc#_bist_status2 329 * 330 * PESC(0..1)_BIST_STATUS2 = PESC BIST Status Register 331 * 332 * Results from BIST runs of PESC's memories. 333 */ 334union cvmx_pescx_bist_status2 { 335 uint64_t u64; 336 struct cvmx_pescx_bist_status2_s { 337#ifdef __BIG_ENDIAN_BITFIELD 338 uint64_t reserved_14_63 : 50; 339 uint64_t cto_p2e : 1; /**< BIST Status for the cto_p2e_fifo */ 340 uint64_t e2p_cpl : 1; /**< BIST Status for the e2p_cpl_fifo */ 341 uint64_t e2p_n : 1; /**< BIST Status for the e2p_n_fifo */ 342 uint64_t e2p_p : 1; /**< BIST Status for the e2p_p_fifo */ 343 uint64_t e2p_rsl : 1; /**< BIST Status for the e2p_rsl__fifo */ 344 uint64_t dbg_p2e : 1; /**< BIST Status for the dbg_p2e_fifo */ 345 uint64_t peai_p2e : 1; /**< BIST Status for the peai__pesc_fifo */ 346 uint64_t rsl_p2e : 1; /**< BIST Status for the rsl_p2e_fifo */ 347 uint64_t pef_tpf1 : 1; /**< BIST Status for the pef_tlp_p_fifo1 */ 348 uint64_t pef_tpf0 : 1; /**< BIST Status for the pef_tlp_p_fifo0 */ 349 uint64_t pef_tnf : 1; /**< BIST Status for the pef_tlp_n_fifo */ 350 uint64_t pef_tcf1 : 1; /**< BIST Status for the pef_tlp_cpl_fifo1 */ 351 uint64_t pef_tc0 : 1; /**< BIST Status for the pef_tlp_cpl_fifo0 */ 352 uint64_t ppf : 1; /**< BIST Status for the ppf_fifo */ 353#else 354 uint64_t ppf : 1; 355 uint64_t pef_tc0 : 1; 356 uint64_t pef_tcf1 : 1; 357 uint64_t pef_tnf : 1; 358 uint64_t pef_tpf0 : 1; 359 uint64_t pef_tpf1 : 1; 360 uint64_t rsl_p2e : 1; 361 uint64_t peai_p2e : 1; 362 uint64_t dbg_p2e : 1; 363 uint64_t e2p_rsl : 1; 364 uint64_t e2p_p : 1; 365 uint64_t e2p_n : 1; 366 uint64_t e2p_cpl : 1; 367 uint64_t cto_p2e : 1; 368 uint64_t reserved_14_63 : 50; 369#endif 370 } s; 371 struct cvmx_pescx_bist_status2_s cn52xx; 372 struct cvmx_pescx_bist_status2_s cn52xxp1; 373 struct cvmx_pescx_bist_status2_s cn56xx; 374 struct cvmx_pescx_bist_status2_s cn56xxp1; 375}; 376typedef union cvmx_pescx_bist_status2 cvmx_pescx_bist_status2_t; 377 378/** 379 * cvmx_pesc#_cfg_rd 380 * 381 * PESC_CFG_RD = PESC Configuration Read 382 * 383 * Allows read access to the configuration in the PCIe Core. 384 */ 385union cvmx_pescx_cfg_rd { 386 uint64_t u64; 387 struct cvmx_pescx_cfg_rd_s { 388#ifdef __BIG_ENDIAN_BITFIELD 389 uint64_t data : 32; /**< Data. */ 390 uint64_t addr : 32; /**< Address to read. A write to this register 391 starts a read operation. */ 392#else 393 uint64_t addr : 32; 394 uint64_t data : 32; 395#endif 396 } s; 397 struct cvmx_pescx_cfg_rd_s cn52xx; 398 struct cvmx_pescx_cfg_rd_s cn52xxp1; 399 struct cvmx_pescx_cfg_rd_s cn56xx; 400 struct cvmx_pescx_cfg_rd_s cn56xxp1; 401}; 402typedef union cvmx_pescx_cfg_rd cvmx_pescx_cfg_rd_t; 403 404/** 405 * cvmx_pesc#_cfg_wr 406 * 407 * PESC_CFG_WR = PESC Configuration Write 408 * 409 * Allows write access to the configuration in the PCIe Core. 410 */ 411union cvmx_pescx_cfg_wr { 412 uint64_t u64; 413 struct cvmx_pescx_cfg_wr_s { 414#ifdef __BIG_ENDIAN_BITFIELD 415 uint64_t data : 32; /**< Data to write. A write to this register starts 416 a write operation. */ 417 uint64_t addr : 32; /**< Address to write. A write to this register starts 418 a write operation. */ 419#else 420 uint64_t addr : 32; 421 uint64_t data : 32; 422#endif 423 } s; 424 struct cvmx_pescx_cfg_wr_s cn52xx; 425 struct cvmx_pescx_cfg_wr_s cn52xxp1; 426 struct cvmx_pescx_cfg_wr_s cn56xx; 427 struct cvmx_pescx_cfg_wr_s cn56xxp1; 428}; 429typedef union cvmx_pescx_cfg_wr cvmx_pescx_cfg_wr_t; 430 431/** 432 * cvmx_pesc#_cpl_lut_valid 433 * 434 * PESC_CPL_LUT_VALID = PESC Cmpletion Lookup Table Valid 435 * 436 * Bit set for outstanding tag read. 437 */ 438union cvmx_pescx_cpl_lut_valid { 439 uint64_t u64; 440 struct cvmx_pescx_cpl_lut_valid_s { 441#ifdef __BIG_ENDIAN_BITFIELD 442 uint64_t reserved_32_63 : 32; 443 uint64_t tag : 32; /**< Bit vector set cooresponds to an outstanding tag 444 expecting a completion. */ 445#else 446 uint64_t tag : 32; 447 uint64_t reserved_32_63 : 32; 448#endif 449 } s; 450 struct cvmx_pescx_cpl_lut_valid_s cn52xx; 451 struct cvmx_pescx_cpl_lut_valid_s cn52xxp1; 452 struct cvmx_pescx_cpl_lut_valid_s cn56xx; 453 struct cvmx_pescx_cpl_lut_valid_s cn56xxp1; 454}; 455typedef union cvmx_pescx_cpl_lut_valid cvmx_pescx_cpl_lut_valid_t; 456 457/** 458 * cvmx_pesc#_ctl_status 459 * 460 * PESC_CTL_STATUS = PESC Control Status 461 * 462 * General control and status of the PESC. 463 */ 464union cvmx_pescx_ctl_status { 465 uint64_t u64; 466 struct cvmx_pescx_ctl_status_s { 467#ifdef __BIG_ENDIAN_BITFIELD 468 uint64_t reserved_28_63 : 36; 469 uint64_t dnum : 5; /**< Primary bus device number. */ 470 uint64_t pbus : 8; /**< Primary bus number. */ 471 uint64_t qlm_cfg : 2; /**< The QLM configuration pad bits. */ 472 uint64_t lane_swp : 1; /**< Lane Swap. For PEDC1, when 0 NO LANE SWAP when '1' 473 enables LANE SWAP. THis bit has no effect on PEDC0. 474 This bit should be set before enabling PEDC1. */ 475 uint64_t pm_xtoff : 1; /**< When WRITTEN with a '1' a single cycle pulse is 476 to the PCIe core pm_xmt_turnoff port. RC mode. */ 477 uint64_t pm_xpme : 1; /**< When WRITTEN with a '1' a single cycle pulse is 478 to the PCIe core pm_xmt_pme port. EP mode. */ 479 uint64_t ob_p_cmd : 1; /**< When WRITTEN with a '1' a single cycle pulse is 480 to the PCIe core outband_pwrup_cmd port. EP mode. */ 481 uint64_t reserved_7_8 : 2; 482 uint64_t nf_ecrc : 1; /**< Do not forward peer-to-peer ECRC TLPs. */ 483 uint64_t dly_one : 1; /**< When set the output client state machines will 484 wait one cycle before starting a new TLP out. */ 485 uint64_t lnk_enb : 1; /**< When set '1' the link is enabled when '0' the 486 link is disabled. This bit only is active when in 487 RC mode. */ 488 uint64_t ro_ctlp : 1; /**< When set '1' C-TLPs that have the RO bit set will 489 not wait for P-TLPs that normaly would be sent 490 first. */ 491 uint64_t reserved_2_2 : 1; 492 uint64_t inv_ecrc : 1; /**< When '1' causes the LSB of the ECRC to be inverted. */ 493 uint64_t inv_lcrc : 1; /**< When '1' causes the LSB of the LCRC to be inverted. */ 494#else 495 uint64_t inv_lcrc : 1; 496 uint64_t inv_ecrc : 1; 497 uint64_t reserved_2_2 : 1; 498 uint64_t ro_ctlp : 1; 499 uint64_t lnk_enb : 1; 500 uint64_t dly_one : 1; 501 uint64_t nf_ecrc : 1; 502 uint64_t reserved_7_8 : 2; 503 uint64_t ob_p_cmd : 1; 504 uint64_t pm_xpme : 1; 505 uint64_t pm_xtoff : 1; 506 uint64_t lane_swp : 1; 507 uint64_t qlm_cfg : 2; 508 uint64_t pbus : 8; 509 uint64_t dnum : 5; 510 uint64_t reserved_28_63 : 36; 511#endif 512 } s; 513 struct cvmx_pescx_ctl_status_s cn52xx; 514 struct cvmx_pescx_ctl_status_s cn52xxp1; 515 struct cvmx_pescx_ctl_status_cn56xx { 516#ifdef __BIG_ENDIAN_BITFIELD 517 uint64_t reserved_28_63 : 36; 518 uint64_t dnum : 5; /**< Primary bus device number. */ 519 uint64_t pbus : 8; /**< Primary bus number. */ 520 uint64_t qlm_cfg : 2; /**< The QLM configuration pad bits. */ 521 uint64_t reserved_12_12 : 1; 522 uint64_t pm_xtoff : 1; /**< When WRITTEN with a '1' a single cycle pulse is 523 to the PCIe core pm_xmt_turnoff port. RC mode. */ 524 uint64_t pm_xpme : 1; /**< When WRITTEN with a '1' a single cycle pulse is 525 to the PCIe core pm_xmt_pme port. EP mode. */ 526 uint64_t ob_p_cmd : 1; /**< When WRITTEN with a '1' a single cycle pulse is 527 to the PCIe core outband_pwrup_cmd port. EP mode. */ 528 uint64_t reserved_7_8 : 2; 529 uint64_t nf_ecrc : 1; /**< Do not forward peer-to-peer ECRC TLPs. */ 530 uint64_t dly_one : 1; /**< When set the output client state machines will 531 wait one cycle before starting a new TLP out. */ 532 uint64_t lnk_enb : 1; /**< When set '1' the link is enabled when '0' the 533 link is disabled. This bit only is active when in 534 RC mode. */ 535 uint64_t ro_ctlp : 1; /**< When set '1' C-TLPs that have the RO bit set will 536 not wait for P-TLPs that normaly would be sent 537 first. */ 538 uint64_t reserved_2_2 : 1; 539 uint64_t inv_ecrc : 1; /**< When '1' causes the LSB of the ECRC to be inverted. */ 540 uint64_t inv_lcrc : 1; /**< When '1' causes the LSB of the LCRC to be inverted. */ 541#else 542 uint64_t inv_lcrc : 1; 543 uint64_t inv_ecrc : 1; 544 uint64_t reserved_2_2 : 1; 545 uint64_t ro_ctlp : 1; 546 uint64_t lnk_enb : 1; 547 uint64_t dly_one : 1; 548 uint64_t nf_ecrc : 1; 549 uint64_t reserved_7_8 : 2; 550 uint64_t ob_p_cmd : 1; 551 uint64_t pm_xpme : 1; 552 uint64_t pm_xtoff : 1; 553 uint64_t reserved_12_12 : 1; 554 uint64_t qlm_cfg : 2; 555 uint64_t pbus : 8; 556 uint64_t dnum : 5; 557 uint64_t reserved_28_63 : 36; 558#endif 559 } cn56xx; 560 struct cvmx_pescx_ctl_status_cn56xx cn56xxp1; 561}; 562typedef union cvmx_pescx_ctl_status cvmx_pescx_ctl_status_t; 563 564/** 565 * cvmx_pesc#_ctl_status2 566 * 567 * Below are in PESC 568 * 569 * PESC(0..1)_BIST_STATUS2 = PESC BIST Status Register 570 * 571 * Results from BIST runs of PESC's memories. 572 */ 573union cvmx_pescx_ctl_status2 { 574 uint64_t u64; 575 struct cvmx_pescx_ctl_status2_s { 576#ifdef __BIG_ENDIAN_BITFIELD 577 uint64_t reserved_2_63 : 62; 578 uint64_t pclk_run : 1; /**< When the pce_clk is running this bit will be '1'. 579 Writing a '1' to this location will cause the 580 bit to be cleared, but if the pce_clk is running 581 this bit will be re-set. */ 582 uint64_t pcierst : 1; /**< Set to '1' when PCIe is in reset. */ 583#else 584 uint64_t pcierst : 1; 585 uint64_t pclk_run : 1; 586 uint64_t reserved_2_63 : 62; 587#endif 588 } s; 589 struct cvmx_pescx_ctl_status2_s cn52xx; 590 struct cvmx_pescx_ctl_status2_cn52xxp1 { 591#ifdef __BIG_ENDIAN_BITFIELD 592 uint64_t reserved_1_63 : 63; 593 uint64_t pcierst : 1; /**< Set to '1' when PCIe is in reset. */ 594#else 595 uint64_t pcierst : 1; 596 uint64_t reserved_1_63 : 63; 597#endif 598 } cn52xxp1; 599 struct cvmx_pescx_ctl_status2_s cn56xx; 600 struct cvmx_pescx_ctl_status2_cn52xxp1 cn56xxp1; 601}; 602typedef union cvmx_pescx_ctl_status2 cvmx_pescx_ctl_status2_t; 603 604/** 605 * cvmx_pesc#_dbg_info 606 * 607 * PESC(0..1)_DBG_INFO = PESC Debug Information 608 * 609 * General debug info. 610 */ 611union cvmx_pescx_dbg_info { 612 uint64_t u64; 613 struct cvmx_pescx_dbg_info_s { 614#ifdef __BIG_ENDIAN_BITFIELD 615 uint64_t reserved_31_63 : 33; 616 uint64_t ecrc_e : 1; /**< Received a ECRC error. 617 radm_ecrc_err */ 618 uint64_t rawwpp : 1; /**< Received a write with poisoned payload 619 radm_rcvd_wreq_poisoned */ 620 uint64_t racpp : 1; /**< Received a completion with poisoned payload 621 radm_rcvd_cpl_poisoned */ 622 uint64_t ramtlp : 1; /**< Received a malformed TLP 623 radm_mlf_tlp_err */ 624 uint64_t rarwdns : 1; /**< Recieved a request which device does not support 625 radm_rcvd_ur_req */ 626 uint64_t caar : 1; /**< Completer aborted a request 627 radm_rcvd_ca_req 628 This bit will never be set because Octeon does 629 not generate Completer Aborts. */ 630 uint64_t racca : 1; /**< Received a completion with CA status 631 radm_rcvd_cpl_ca */ 632 uint64_t racur : 1; /**< Received a completion with UR status 633 radm_rcvd_cpl_ur */ 634 uint64_t rauc : 1; /**< Received an unexpected completion 635 radm_unexp_cpl_err */ 636 uint64_t rqo : 1; /**< Receive queue overflow. Normally happens only when 637 flow control advertisements are ignored 638 radm_qoverflow */ 639 uint64_t fcuv : 1; /**< Flow Control Update Violation (opt. checks) 640 int_xadm_fc_prot_err */ 641 uint64_t rpe : 1; /**< When the PHY reports 8B/10B decode error 642 (RxStatus = 3b100) or disparity error 643 (RxStatus = 3b111), the signal rmlh_rcvd_err will 644 be asserted. 645 rmlh_rcvd_err */ 646 uint64_t fcpvwt : 1; /**< Flow Control Protocol Violation (Watchdog Timer) 647 rtlh_fc_prot_err */ 648 uint64_t dpeoosd : 1; /**< DLLP protocol error (out of sequence DLLP) 649 rdlh_prot_err */ 650 uint64_t rtwdle : 1; /**< Received TLP with DataLink Layer Error 651 rdlh_bad_tlp_err */ 652 uint64_t rdwdle : 1; /**< Received DLLP with DataLink Layer Error 653 rdlh_bad_dllp_err */ 654 uint64_t mre : 1; /**< Max Retries Exceeded 655 xdlh_replay_num_rlover_err */ 656 uint64_t rte : 1; /**< Replay Timer Expired 657 xdlh_replay_timeout_err 658 This bit is set when the REPLAY_TIMER expires in 659 the PCIE core. The probability of this bit being 660 set will increase with the traffic load. */ 661 uint64_t acto : 1; /**< A Completion Timeout Occured 662 pedc_radm_cpl_timeout */ 663 uint64_t rvdm : 1; /**< Received Vendor-Defined Message 664 pedc_radm_vendor_msg */ 665 uint64_t rumep : 1; /**< Received Unlock Message (EP Mode Only) 666 pedc_radm_msg_unlock */ 667 uint64_t rptamrc : 1; /**< Received PME Turnoff Acknowledge Message 668 (RC Mode only) 669 pedc_radm_pm_to_ack */ 670 uint64_t rpmerc : 1; /**< Received PME Message (RC Mode only) 671 pedc_radm_pm_pme */ 672 uint64_t rfemrc : 1; /**< Received Fatal Error Message (RC Mode only) 673 pedc_radm_fatal_err 674 Bit set when a message with ERR_FATAL is set. */ 675 uint64_t rnfemrc : 1; /**< Received Non-Fatal Error Message (RC Mode only) 676 pedc_radm_nonfatal_err */ 677 uint64_t rcemrc : 1; /**< Received Correctable Error Message (RC Mode only) 678 pedc_radm_correctable_err */ 679 uint64_t rpoison : 1; /**< Received Poisoned TLP 680 pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv */ 681 uint64_t recrce : 1; /**< Received ECRC Error 682 pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot */ 683 uint64_t rtlplle : 1; /**< Received TLP has link layer error 684 pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot */ 685 uint64_t rtlpmal : 1; /**< Received TLP is malformed or a message. 686 pedc_radm_trgt1_tlp_abort & pedc__radm_trgt1_eot 687 If the core receives a MSG (or Vendor Message) 688 this bit will be set. */ 689 uint64_t spoison : 1; /**< Poisoned TLP sent 690 peai__client0_tlp_ep & peai__client0_tlp_hv */ 691#else 692 uint64_t spoison : 1; 693 uint64_t rtlpmal : 1; 694 uint64_t rtlplle : 1; 695 uint64_t recrce : 1; 696 uint64_t rpoison : 1; 697 uint64_t rcemrc : 1; 698 uint64_t rnfemrc : 1; 699 uint64_t rfemrc : 1; 700 uint64_t rpmerc : 1; 701 uint64_t rptamrc : 1; 702 uint64_t rumep : 1; 703 uint64_t rvdm : 1; 704 uint64_t acto : 1; 705 uint64_t rte : 1; 706 uint64_t mre : 1; 707 uint64_t rdwdle : 1; 708 uint64_t rtwdle : 1; 709 uint64_t dpeoosd : 1; 710 uint64_t fcpvwt : 1; 711 uint64_t rpe : 1; 712 uint64_t fcuv : 1; 713 uint64_t rqo : 1; 714 uint64_t rauc : 1; 715 uint64_t racur : 1; 716 uint64_t racca : 1; 717 uint64_t caar : 1; 718 uint64_t rarwdns : 1; 719 uint64_t ramtlp : 1; 720 uint64_t racpp : 1; 721 uint64_t rawwpp : 1; 722 uint64_t ecrc_e : 1; 723 uint64_t reserved_31_63 : 33; 724#endif 725 } s; 726 struct cvmx_pescx_dbg_info_s cn52xx; 727 struct cvmx_pescx_dbg_info_s cn52xxp1; 728 struct cvmx_pescx_dbg_info_s cn56xx; 729 struct cvmx_pescx_dbg_info_s cn56xxp1; 730}; 731typedef union cvmx_pescx_dbg_info cvmx_pescx_dbg_info_t; 732 733/** 734 * cvmx_pesc#_dbg_info_en 735 * 736 * PESC(0..1)_DBG_INFO_EN = PESC Debug Information Enable 737 * 738 * Allows PESC_DBG_INFO to generate interrupts when cooresponding enable bit is set. 739 */ 740union cvmx_pescx_dbg_info_en { 741 uint64_t u64; 742 struct cvmx_pescx_dbg_info_en_s { 743#ifdef __BIG_ENDIAN_BITFIELD 744 uint64_t reserved_31_63 : 33; 745 uint64_t ecrc_e : 1; /**< Allows PESC_DBG_INFO[30] to generate an interrupt. */ 746 uint64_t rawwpp : 1; /**< Allows PESC_DBG_INFO[29] to generate an interrupt. */ 747 uint64_t racpp : 1; /**< Allows PESC_DBG_INFO[28] to generate an interrupt. */ 748 uint64_t ramtlp : 1; /**< Allows PESC_DBG_INFO[27] to generate an interrupt. */ 749 uint64_t rarwdns : 1; /**< Allows PESC_DBG_INFO[26] to generate an interrupt. */ 750 uint64_t caar : 1; /**< Allows PESC_DBG_INFO[25] to generate an interrupt. */ 751 uint64_t racca : 1; /**< Allows PESC_DBG_INFO[24] to generate an interrupt. */ 752 uint64_t racur : 1; /**< Allows PESC_DBG_INFO[23] to generate an interrupt. */ 753 uint64_t rauc : 1; /**< Allows PESC_DBG_INFO[22] to generate an interrupt. */ 754 uint64_t rqo : 1; /**< Allows PESC_DBG_INFO[21] to generate an interrupt. */ 755 uint64_t fcuv : 1; /**< Allows PESC_DBG_INFO[20] to generate an interrupt. */ 756 uint64_t rpe : 1; /**< Allows PESC_DBG_INFO[19] to generate an interrupt. */ 757 uint64_t fcpvwt : 1; /**< Allows PESC_DBG_INFO[18] to generate an interrupt. */ 758 uint64_t dpeoosd : 1; /**< Allows PESC_DBG_INFO[17] to generate an interrupt. */ 759 uint64_t rtwdle : 1; /**< Allows PESC_DBG_INFO[16] to generate an interrupt. */ 760 uint64_t rdwdle : 1; /**< Allows PESC_DBG_INFO[15] to generate an interrupt. */ 761 uint64_t mre : 1; /**< Allows PESC_DBG_INFO[14] to generate an interrupt. */ 762 uint64_t rte : 1; /**< Allows PESC_DBG_INFO[13] to generate an interrupt. */ 763 uint64_t acto : 1; /**< Allows PESC_DBG_INFO[12] to generate an interrupt. */ 764 uint64_t rvdm : 1; /**< Allows PESC_DBG_INFO[11] to generate an interrupt. */ 765 uint64_t rumep : 1; /**< Allows PESC_DBG_INFO[10] to generate an interrupt. */ 766 uint64_t rptamrc : 1; /**< Allows PESC_DBG_INFO[9] to generate an interrupt. */ 767 uint64_t rpmerc : 1; /**< Allows PESC_DBG_INFO[8] to generate an interrupt. */ 768 uint64_t rfemrc : 1; /**< Allows PESC_DBG_INFO[7] to generate an interrupt. */ 769 uint64_t rnfemrc : 1; /**< Allows PESC_DBG_INFO[6] to generate an interrupt. */ 770 uint64_t rcemrc : 1; /**< Allows PESC_DBG_INFO[5] to generate an interrupt. */ 771 uint64_t rpoison : 1; /**< Allows PESC_DBG_INFO[4] to generate an interrupt. */ 772 uint64_t recrce : 1; /**< Allows PESC_DBG_INFO[3] to generate an interrupt. */ 773 uint64_t rtlplle : 1; /**< Allows PESC_DBG_INFO[2] to generate an interrupt. */ 774 uint64_t rtlpmal : 1; /**< Allows PESC_DBG_INFO[1] to generate an interrupt. */ 775 uint64_t spoison : 1; /**< Allows PESC_DBG_INFO[0] to generate an interrupt. */ 776#else 777 uint64_t spoison : 1; 778 uint64_t rtlpmal : 1; 779 uint64_t rtlplle : 1; 780 uint64_t recrce : 1; 781 uint64_t rpoison : 1; 782 uint64_t rcemrc : 1; 783 uint64_t rnfemrc : 1; 784 uint64_t rfemrc : 1; 785 uint64_t rpmerc : 1; 786 uint64_t rptamrc : 1; 787 uint64_t rumep : 1; 788 uint64_t rvdm : 1; 789 uint64_t acto : 1; 790 uint64_t rte : 1; 791 uint64_t mre : 1; 792 uint64_t rdwdle : 1; 793 uint64_t rtwdle : 1; 794 uint64_t dpeoosd : 1; 795 uint64_t fcpvwt : 1; 796 uint64_t rpe : 1; 797 uint64_t fcuv : 1; 798 uint64_t rqo : 1; 799 uint64_t rauc : 1; 800 uint64_t racur : 1; 801 uint64_t racca : 1; 802 uint64_t caar : 1; 803 uint64_t rarwdns : 1; 804 uint64_t ramtlp : 1; 805 uint64_t racpp : 1; 806 uint64_t rawwpp : 1; 807 uint64_t ecrc_e : 1; 808 uint64_t reserved_31_63 : 33; 809#endif 810 } s; 811 struct cvmx_pescx_dbg_info_en_s cn52xx; 812 struct cvmx_pescx_dbg_info_en_s cn52xxp1; 813 struct cvmx_pescx_dbg_info_en_s cn56xx; 814 struct cvmx_pescx_dbg_info_en_s cn56xxp1; 815}; 816typedef union cvmx_pescx_dbg_info_en cvmx_pescx_dbg_info_en_t; 817 818/** 819 * cvmx_pesc#_diag_status 820 * 821 * PESC_DIAG_STATUS = PESC Diagnostic Status 822 * 823 * Selection control for the cores diagnostic bus. 824 */ 825union cvmx_pescx_diag_status { 826 uint64_t u64; 827 struct cvmx_pescx_diag_status_s { 828#ifdef __BIG_ENDIAN_BITFIELD 829 uint64_t reserved_4_63 : 60; 830 uint64_t pm_dst : 1; /**< Current power management DSTATE. */ 831 uint64_t pm_stat : 1; /**< Power Management Status. */ 832 uint64_t pm_en : 1; /**< Power Management Event Enable. */ 833 uint64_t aux_en : 1; /**< Auxilary Power Enable. */ 834#else 835 uint64_t aux_en : 1; 836 uint64_t pm_en : 1; 837 uint64_t pm_stat : 1; 838 uint64_t pm_dst : 1; 839 uint64_t reserved_4_63 : 60; 840#endif 841 } s; 842 struct cvmx_pescx_diag_status_s cn52xx; 843 struct cvmx_pescx_diag_status_s cn52xxp1; 844 struct cvmx_pescx_diag_status_s cn56xx; 845 struct cvmx_pescx_diag_status_s cn56xxp1; 846}; 847typedef union cvmx_pescx_diag_status cvmx_pescx_diag_status_t; 848 849/** 850 * cvmx_pesc#_p2n_bar0_start 851 * 852 * PESC_P2N_BAR0_START = PESC PCIe to Npei BAR0 Start 853 * 854 * The starting address for addresses to forwarded to the NPEI in RC Mode. 855 */ 856union cvmx_pescx_p2n_bar0_start { 857 uint64_t u64; 858 struct cvmx_pescx_p2n_bar0_start_s { 859#ifdef __BIG_ENDIAN_BITFIELD 860 uint64_t addr : 50; /**< The starting address of the 16KB address space that 861 is the BAR0 address space. */ 862 uint64_t reserved_0_13 : 14; 863#else 864 uint64_t reserved_0_13 : 14; 865 uint64_t addr : 50; 866#endif 867 } s; 868 struct cvmx_pescx_p2n_bar0_start_s cn52xx; 869 struct cvmx_pescx_p2n_bar0_start_s cn52xxp1; 870 struct cvmx_pescx_p2n_bar0_start_s cn56xx; 871 struct cvmx_pescx_p2n_bar0_start_s cn56xxp1; 872}; 873typedef union cvmx_pescx_p2n_bar0_start cvmx_pescx_p2n_bar0_start_t; 874 875/** 876 * cvmx_pesc#_p2n_bar1_start 877 * 878 * PESC_P2N_BAR1_START = PESC PCIe to Npei BAR1 Start 879 * 880 * The starting address for addresses to forwarded to the NPEI in RC Mode. 881 */ 882union cvmx_pescx_p2n_bar1_start { 883 uint64_t u64; 884 struct cvmx_pescx_p2n_bar1_start_s { 885#ifdef __BIG_ENDIAN_BITFIELD 886 uint64_t addr : 38; /**< The starting address of the 64KB address space 887 that is the BAR1 address space. */ 888 uint64_t reserved_0_25 : 26; 889#else 890 uint64_t reserved_0_25 : 26; 891 uint64_t addr : 38; 892#endif 893 } s; 894 struct cvmx_pescx_p2n_bar1_start_s cn52xx; 895 struct cvmx_pescx_p2n_bar1_start_s cn52xxp1; 896 struct cvmx_pescx_p2n_bar1_start_s cn56xx; 897 struct cvmx_pescx_p2n_bar1_start_s cn56xxp1; 898}; 899typedef union cvmx_pescx_p2n_bar1_start cvmx_pescx_p2n_bar1_start_t; 900 901/** 902 * cvmx_pesc#_p2n_bar2_start 903 * 904 * PESC_P2N_BAR2_START = PESC PCIe to Npei BAR2 Start 905 * 906 * The starting address for addresses to forwarded to the NPEI in RC Mode. 907 */ 908union cvmx_pescx_p2n_bar2_start { 909 uint64_t u64; 910 struct cvmx_pescx_p2n_bar2_start_s { 911#ifdef __BIG_ENDIAN_BITFIELD 912 uint64_t addr : 25; /**< The starting address of the 2^39 address space 913 that is the BAR2 address space. */ 914 uint64_t reserved_0_38 : 39; 915#else 916 uint64_t reserved_0_38 : 39; 917 uint64_t addr : 25; 918#endif 919 } s; 920 struct cvmx_pescx_p2n_bar2_start_s cn52xx; 921 struct cvmx_pescx_p2n_bar2_start_s cn52xxp1; 922 struct cvmx_pescx_p2n_bar2_start_s cn56xx; 923 struct cvmx_pescx_p2n_bar2_start_s cn56xxp1; 924}; 925typedef union cvmx_pescx_p2n_bar2_start cvmx_pescx_p2n_bar2_start_t; 926 927/** 928 * cvmx_pesc#_p2p_bar#_end 929 * 930 * PESC_P2P_BAR#_END = PESC Peer-To-Peer BAR0 End 931 * 932 * The ending address for addresses to forwarded to the PCIe peer port. 933 */ 934union cvmx_pescx_p2p_barx_end { 935 uint64_t u64; 936 struct cvmx_pescx_p2p_barx_end_s { 937#ifdef __BIG_ENDIAN_BITFIELD 938 uint64_t addr : 52; /**< The ending address of the address window created 939 this field and the PESC_P2P_BAR0_START[63:12] 940 field. The full 64-bits of address are created by: 941 [ADDR[63:12], 12'b0]. */ 942 uint64_t reserved_0_11 : 12; 943#else 944 uint64_t reserved_0_11 : 12; 945 uint64_t addr : 52; 946#endif 947 } s; 948 struct cvmx_pescx_p2p_barx_end_s cn52xx; 949 struct cvmx_pescx_p2p_barx_end_s cn52xxp1; 950 struct cvmx_pescx_p2p_barx_end_s cn56xx; 951 struct cvmx_pescx_p2p_barx_end_s cn56xxp1; 952}; 953typedef union cvmx_pescx_p2p_barx_end cvmx_pescx_p2p_barx_end_t; 954 955/** 956 * cvmx_pesc#_p2p_bar#_start 957 * 958 * PESC_P2P_BAR#_START = PESC Peer-To-Peer BAR0 Start 959 * 960 * The starting address and enable for addresses to forwarded to the PCIe peer port. 961 */ 962union cvmx_pescx_p2p_barx_start { 963 uint64_t u64; 964 struct cvmx_pescx_p2p_barx_start_s { 965#ifdef __BIG_ENDIAN_BITFIELD 966 uint64_t addr : 52; /**< The starting address of the address window created 967 this field and the PESC_P2P_BAR0_END[63:12] field. 968 The full 64-bits of address are created by: 969 [ADDR[63:12], 12'b0]. */ 970 uint64_t reserved_0_11 : 12; 971#else 972 uint64_t reserved_0_11 : 12; 973 uint64_t addr : 52; 974#endif 975 } s; 976 struct cvmx_pescx_p2p_barx_start_s cn52xx; 977 struct cvmx_pescx_p2p_barx_start_s cn52xxp1; 978 struct cvmx_pescx_p2p_barx_start_s cn56xx; 979 struct cvmx_pescx_p2p_barx_start_s cn56xxp1; 980}; 981typedef union cvmx_pescx_p2p_barx_start cvmx_pescx_p2p_barx_start_t; 982 983/** 984 * cvmx_pesc#_tlp_credits 985 * 986 * PESC_TLP_CREDITS = PESC TLP Credits 987 * 988 * Specifies the number of credits the PESC for use in moving TLPs. When this register is written the credit values are 989 * reset to the register value. A write to this register should take place BEFORE traffic flow starts. 990 */ 991union cvmx_pescx_tlp_credits { 992 uint64_t u64; 993 struct cvmx_pescx_tlp_credits_s { 994#ifdef __BIG_ENDIAN_BITFIELD 995 uint64_t reserved_0_63 : 64; 996#else 997 uint64_t reserved_0_63 : 64; 998#endif 999 } s; 1000 struct cvmx_pescx_tlp_credits_cn52xx { 1001#ifdef __BIG_ENDIAN_BITFIELD 1002 uint64_t reserved_56_63 : 8; 1003 uint64_t peai_ppf : 8; /**< TLP credits for Completion TLPs in the Peer. 1004 Legal values are 0x24 to 0x80. */ 1005 uint64_t pesc_cpl : 8; /**< TLP credits for Completion TLPs in the Peer. 1006 Legal values are 0x24 to 0x80. */ 1007 uint64_t pesc_np : 8; /**< TLP credits for Non-Posted TLPs in the Peer. 1008 Legal values are 0x4 to 0x10. */ 1009 uint64_t pesc_p : 8; /**< TLP credits for Posted TLPs in the Peer. 1010 Legal values are 0x24 to 0x80. */ 1011 uint64_t npei_cpl : 8; /**< TLP credits for Completion TLPs in the NPEI. 1012 Legal values are 0x24 to 0x80. */ 1013 uint64_t npei_np : 8; /**< TLP credits for Non-Posted TLPs in the NPEI. 1014 Legal values are 0x4 to 0x10. */ 1015 uint64_t npei_p : 8; /**< TLP credits for Posted TLPs in the NPEI. 1016 Legal values are 0x24 to 0x80. */ 1017#else 1018 uint64_t npei_p : 8; 1019 uint64_t npei_np : 8; 1020 uint64_t npei_cpl : 8; 1021 uint64_t pesc_p : 8; 1022 uint64_t pesc_np : 8; 1023 uint64_t pesc_cpl : 8; 1024 uint64_t peai_ppf : 8; 1025 uint64_t reserved_56_63 : 8; 1026#endif 1027 } cn52xx; 1028 struct cvmx_pescx_tlp_credits_cn52xxp1 { 1029#ifdef __BIG_ENDIAN_BITFIELD 1030 uint64_t reserved_38_63 : 26; 1031 uint64_t peai_ppf : 8; /**< TLP credits in core clk pre-buffer that holds TLPs 1032 being sent from PCIe Core to NPEI or PEER. */ 1033 uint64_t pesc_cpl : 5; /**< TLP credits for Completion TLPs in the Peer. */ 1034 uint64_t pesc_np : 5; /**< TLP credits for Non-Posted TLPs in the Peer. */ 1035 uint64_t pesc_p : 5; /**< TLP credits for Posted TLPs in the Peer. */ 1036 uint64_t npei_cpl : 5; /**< TLP credits for Completion TLPs in the NPEI. */ 1037 uint64_t npei_np : 5; /**< TLP credits for Non-Posted TLPs in the NPEI. */ 1038 uint64_t npei_p : 5; /**< TLP credits for Posted TLPs in the NPEI. */ 1039#else 1040 uint64_t npei_p : 5; 1041 uint64_t npei_np : 5; 1042 uint64_t npei_cpl : 5; 1043 uint64_t pesc_p : 5; 1044 uint64_t pesc_np : 5; 1045 uint64_t pesc_cpl : 5; 1046 uint64_t peai_ppf : 8; 1047 uint64_t reserved_38_63 : 26; 1048#endif 1049 } cn52xxp1; 1050 struct cvmx_pescx_tlp_credits_cn52xx cn56xx; 1051 struct cvmx_pescx_tlp_credits_cn52xxp1 cn56xxp1; 1052}; 1053typedef union cvmx_pescx_tlp_credits cvmx_pescx_tlp_credits_t; 1054 1055#endif 1056