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/freebsd-11-stable/sys/dev/ffec/ | ||
H A D | if_ffecreg.h | diff 327638 Sat Jan 06 21:30:06 MST 2018 ian MFC r325045, r325054-r325056, r325061, r325063, r325065 r325045: Actually release resources in detach() rather than just returning EBUSY. This will enable use of 'devctl disable', allow creation of a module, etc. r325054: Increase the alignment of the rx/tx descriptor ring buffers to 64 bytes. 16 was the correct alignment for older hardware, but the imx7 requires 64-byte alignment, which is a fine value to use on all systems. PR: 222634 Submitted by: sebastian.huber@embedded-brains.de r325055: Add FECFLAG_AVB variant flag to support new features on imx7. This flag is analogous to the Linux driver FEC_QUIRK_HAS_AVB. It indicates an FEC with support for Audio Video Bridging (AVB). This indicator is used for various other parts in the Linux driver (drivers/net/ethernet/freescale/fec_main.c). Use it to customize the receive/transmit buffer alignment. The receive buffer alignment increased to 64-bytes on the i.MX 6SoloX and i.MX 7Dual. There are no hard alignment restrictions for transmit buffers on these chips. Fix the ffec_softc::fectype type to provide enough storage for the feature flags. PR: 222634 Submitted by: sebastian.huber@embedded-brains.de r325056: Avoid AXI bus issues due to a MAC reset on imx6sx and imx7. When the FEC is connected to the AXI bus (indicated by AVB flag), a MAC reset while a bus transaction is pending can hang the bus. Instead of resetting, turn off the ENABLE bit, which allows the hardware to complete any in-progress transfers (appending a bad CRC to any partial packet) and release the AXI bus. This could probably be done unconditionally for all hardware variants, but that hasn't been tested. PR: 222634 Submitted by: sebastian.huber@embedded-brains.de r325061: Support up to 3 IRQs in the ffec driver. Newer hardware splits the interrupts onto 3 different irq lines, but the docs barely mention that there are multiple interrupts, and do not detail how they're split up. The code now supports 1-3 irqs, and uses the same interrupt service routine to handle all of them. I modified the submitted changes to use bus_alloc_resources() instead of using loops to allocate each irq separately. Thus, blame any bugs on me (I can't actually test on imx7 hardware). PR: 222634 Submitted by: sebastian.huber@embedded-brains.de r325063: Use the 16-bit receive shift feature in ffec hardware that supports it. When available, enabling this feature causes the hardware to write data to the receive buffer starting at a 16-bit offset from the start address. This eliminates the need to copy the data after receiving to re-align the protocol headers to a 32-bit boundary. PR: 222634 Submitted by: sebastian.huber@embedded-brains.de r325065: Split the hardware type enum and the hw feature flags bits into separate fields in the softc; they're ORed together in the ofw_compat_data. I already caught myself doing 'sc->fectype == <enum val>' without masking out the feature bits in one place, and that's sure to happen again. Glomming them together is convenient for storing them in the ofw_compat_data array, but there's no reason to keep them together in the softc. |
H A D | if_ffec.c | diff 327638 Sat Jan 06 21:30:06 MST 2018 ian MFC r325045, r325054-r325056, r325061, r325063, r325065 r325045: Actually release resources in detach() rather than just returning EBUSY. This will enable use of 'devctl disable', allow creation of a module, etc. r325054: Increase the alignment of the rx/tx descriptor ring buffers to 64 bytes. 16 was the correct alignment for older hardware, but the imx7 requires 64-byte alignment, which is a fine value to use on all systems. PR: 222634 Submitted by: sebastian.huber@embedded-brains.de r325055: Add FECFLAG_AVB variant flag to support new features on imx7. This flag is analogous to the Linux driver FEC_QUIRK_HAS_AVB. It indicates an FEC with support for Audio Video Bridging (AVB). This indicator is used for various other parts in the Linux driver (drivers/net/ethernet/freescale/fec_main.c). Use it to customize the receive/transmit buffer alignment. The receive buffer alignment increased to 64-bytes on the i.MX 6SoloX and i.MX 7Dual. There are no hard alignment restrictions for transmit buffers on these chips. Fix the ffec_softc::fectype type to provide enough storage for the feature flags. PR: 222634 Submitted by: sebastian.huber@embedded-brains.de r325056: Avoid AXI bus issues due to a MAC reset on imx6sx and imx7. When the FEC is connected to the AXI bus (indicated by AVB flag), a MAC reset while a bus transaction is pending can hang the bus. Instead of resetting, turn off the ENABLE bit, which allows the hardware to complete any in-progress transfers (appending a bad CRC to any partial packet) and release the AXI bus. This could probably be done unconditionally for all hardware variants, but that hasn't been tested. PR: 222634 Submitted by: sebastian.huber@embedded-brains.de r325061: Support up to 3 IRQs in the ffec driver. Newer hardware splits the interrupts onto 3 different irq lines, but the docs barely mention that there are multiple interrupts, and do not detail how they're split up. The code now supports 1-3 irqs, and uses the same interrupt service routine to handle all of them. I modified the submitted changes to use bus_alloc_resources() instead of using loops to allocate each irq separately. Thus, blame any bugs on me (I can't actually test on imx7 hardware). PR: 222634 Submitted by: sebastian.huber@embedded-brains.de r325063: Use the 16-bit receive shift feature in ffec hardware that supports it. When available, enabling this feature causes the hardware to write data to the receive buffer starting at a 16-bit offset from the start address. This eliminates the need to copy the data after receiving to re-align the protocol headers to a 32-bit boundary. PR: 222634 Submitted by: sebastian.huber@embedded-brains.de r325065: Split the hardware type enum and the hw feature flags bits into separate fields in the softc; they're ORed together in the ofw_compat_data. I already caught myself doing 'sc->fectype == <enum val>' without masking out the feature bits in one place, and that's sure to happen again. Glomming them together is convenient for storing them in the ofw_compat_data array, but there's no reason to keep them together in the softc. |
/freebsd-11-stable/sys/dev/sdhci/ | ||
H A D | fsl_sdhci.c | diff 327638 Sat Jan 06 21:30:06 MST 2018 ian MFC r325045, r325054-r325056, r325061, r325063, r325065 r325045: Actually release resources in detach() rather than just returning EBUSY. This will enable use of 'devctl disable', allow creation of a module, etc. r325054: Increase the alignment of the rx/tx descriptor ring buffers to 64 bytes. 16 was the correct alignment for older hardware, but the imx7 requires 64-byte alignment, which is a fine value to use on all systems. PR: 222634 Submitted by: sebastian.huber@embedded-brains.de r325055: Add FECFLAG_AVB variant flag to support new features on imx7. This flag is analogous to the Linux driver FEC_QUIRK_HAS_AVB. It indicates an FEC with support for Audio Video Bridging (AVB). This indicator is used for various other parts in the Linux driver (drivers/net/ethernet/freescale/fec_main.c). Use it to customize the receive/transmit buffer alignment. The receive buffer alignment increased to 64-bytes on the i.MX 6SoloX and i.MX 7Dual. There are no hard alignment restrictions for transmit buffers on these chips. Fix the ffec_softc::fectype type to provide enough storage for the feature flags. PR: 222634 Submitted by: sebastian.huber@embedded-brains.de r325056: Avoid AXI bus issues due to a MAC reset on imx6sx and imx7. When the FEC is connected to the AXI bus (indicated by AVB flag), a MAC reset while a bus transaction is pending can hang the bus. Instead of resetting, turn off the ENABLE bit, which allows the hardware to complete any in-progress transfers (appending a bad CRC to any partial packet) and release the AXI bus. This could probably be done unconditionally for all hardware variants, but that hasn't been tested. PR: 222634 Submitted by: sebastian.huber@embedded-brains.de r325061: Support up to 3 IRQs in the ffec driver. Newer hardware splits the interrupts onto 3 different irq lines, but the docs barely mention that there are multiple interrupts, and do not detail how they're split up. The code now supports 1-3 irqs, and uses the same interrupt service routine to handle all of them. I modified the submitted changes to use bus_alloc_resources() instead of using loops to allocate each irq separately. Thus, blame any bugs on me (I can't actually test on imx7 hardware). PR: 222634 Submitted by: sebastian.huber@embedded-brains.de r325063: Use the 16-bit receive shift feature in ffec hardware that supports it. When available, enabling this feature causes the hardware to write data to the receive buffer starting at a 16-bit offset from the start address. This eliminates the need to copy the data after receiving to re-align the protocol headers to a 32-bit boundary. PR: 222634 Submitted by: sebastian.huber@embedded-brains.de r325065: Split the hardware type enum and the hw feature flags bits into separate fields in the softc; they're ORed together in the ofw_compat_data. I already caught myself doing 'sc->fectype == <enum val>' without masking out the feature bits in one place, and that's sure to happen again. Glomming them together is convenient for storing them in the ofw_compat_data array, but there's no reason to keep them together in the softc. |
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