Searched defs:mpcc_id (Results 1 - 16 of 16) sorted by relevance

/linux-master/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_mpc.c40 mpc1_set_bg_color(struct mpc *mpc, struct tg_color *bg_color, int mpcc_id) argument
76 mpc1_update_blending( struct mpc *mpc, struct mpcc_blnd_cfg *blnd_cfg, int mpcc_id) argument
94 mpc1_update_stereo_mix( struct mpc *mpc, struct mpcc_sm_cfg *sm_cfg, int mpcc_id) argument
119 mpc1_get_mpcc(struct mpc *mpc, int mpcc_id) argument
145 mpc1_is_mpcc_idle(struct mpc *mpc, int mpcc_id) argument
161 mpc1_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id) argument
195 mpc1_insert_plane( struct mpc *mpc, struct mpc_tree *tree, struct mpcc_blnd_cfg *blnd_cfg, struct mpcc_sm_cfg *sm_cfg, struct mpcc *insert_above_mpcc, int dpp_id, int mpcc_id) argument
294 int mpcc_id = mpcc_to_remove->mpcc_id; local
374 int mpcc_id; local
393 mpc1_mpc_init_single_inst(struct mpc *mpc, unsigned int mpcc_id) argument
422 int mpcc_id; local
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/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn201/
H A Ddcn201_hwseq.c425 int mpcc_id, dpp_id; local
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/linux-master/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_mpc.c48 mpc2_update_blending( struct mpc *mpc, struct mpcc_blnd_cfg *blnd_cfg, int mpcc_id) argument
272 mpc20_power_on_ogam_lut( struct mpc *mpc, int mpcc_id, bool power_on) argument
283 mpc20_configure_ogam_lut( struct mpc *mpc, int mpcc_id, bool is_ram_a) argument
296 mpc20_get_ogam_current(struct mpc *mpc, int mpcc_id) argument
322 mpc2_program_lutb(struct mpc *mpc, int mpcc_id, const struct pwl_params *params) argument
349 mpc2_program_luta(struct mpc *mpc, int mpcc_id, const struct pwl_params *params) argument
376 mpc20_program_ogam_pwl( struct mpc *mpc, int mpcc_id, const struct pwl_result_data *rgb, uint32_t num) argument
403 apply_DEDCN20_305_wa(struct mpc *mpc, int mpcc_id, enum dc_lut_mode current_mode, enum dc_lut_mode next_mode) argument
427 mpc2_set_output_gamma( struct mpc *mpc, int mpcc_id, const struct pwl_params *params) argument
483 mpc2_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id) argument
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/linux-master/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_hw_sequencer.c860 int mpcc_id = params->power_on_mpc_mem_pwr_params.mpcc_id; local
H A Ddc.c2208 int mpcc_id = 0; local
/linux-master/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Dhubp.h76 int mpcc_id; member in struct:hubp
H A Dmpc.h206 int mpcc_id; member in struct:mpcc
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/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn30/
H A Ddcn30_hwseq.c246 int mpcc_id = pipe_ctx->plane_res.hubp->inst; local
343 int mpcc_id = pipe_ctx->plane_res.hubp->inst; local
379 int mpcc_id = pipe_ctx->plane_res.hubp->inst; local
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/linux-master/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_mpc.c48 int mpcc_id; local
67 mpc32_power_on_blnd_lut( struct mpc *mpc, uint32_t mpcc_id, bool power_on) argument
92 mpc32_get_post1dlut_current(struct mpc *mpc, uint32_t mpcc_id) argument
124 mpc32_configure_post1dlut( struct mpc *mpc, uint32_t mpcc_id, bool is_ram_a) argument
167 mpc32_program_post1dluta_settings( struct mpc *mpc, uint32_t mpcc_id, const struct pwl_params *params) argument
196 mpc32_program_post1dlutb_settings( struct mpc *mpc, uint32_t mpcc_id, const struct pwl_params *params) argument
224 mpc32_program_post1dlut_pwl( struct mpc *mpc, uint32_t mpcc_id, const struct pwl_result_data *rgb, uint32_t num) argument
261 mpc32_program_post1dlut( struct mpc *mpc, const struct pwl_params *params, uint32_t mpcc_id) argument
301 mpc32_get_shaper_current(struct mpc *mpc, uint32_t mpcc_id) argument
328 mpc32_configure_shaper_lut( struct mpc *mpc, bool is_ram_a, uint32_t mpcc_id) argument
343 mpc32_program_shaper_luta_settings( struct mpc *mpc, const struct pwl_params *params, uint32_t mpcc_id) argument
493 mpc32_program_shaper_lutb_settings( struct mpc *mpc, const struct pwl_params *params, uint32_t mpcc_id) argument
644 mpc32_program_shaper_lut( struct mpc *mpc, const struct pwl_result_data *rgb, uint32_t num, uint32_t mpcc_id) argument
678 mpc32_power_on_shaper_3dlut( struct mpc *mpc, uint32_t mpcc_id, bool power_on) argument
708 mpc32_program_shaper( struct mpc *mpc, const struct pwl_params *params, uint32_t mpcc_id) argument
750 get3dlut_config( struct mpc *mpc, bool *is_17x17x17, bool *is_12bits_color_channel, int mpcc_id) argument
796 mpc32_select_3dlut_ram( struct mpc *mpc, enum dc_lut_mode mode, bool is_color_channel_12bits, uint32_t mpcc_id) argument
810 mpc32_select_3dlut_ram_mask( struct mpc *mpc, uint32_t ram_selection_mask, uint32_t mpcc_id) argument
823 mpc32_set3dlut_ram12( struct mpc *mpc, const struct dc_rgb *lut, uint32_t entries, uint32_t mpcc_id) argument
855 mpc32_set3dlut_ram10( struct mpc *mpc, const struct dc_rgb *lut, uint32_t entries, uint32_t mpcc_id) argument
877 mpc32_set_3dlut_mode( struct mpc *mpc, enum dc_lut_mode mode, bool is_color_channel_12bits, bool is_lut_size17x17x17, uint32_t mpcc_id) argument
904 mpc32_program_3dlut( struct mpc *mpc, const struct tetrahedral_params *params, int mpcc_id) argument
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/linux-master/drivers/gpu/drm/amd/display/dc/hwss/
H A Dhw_sequencer.h115 int mpcc_id; member in struct:update_visual_confirm_params
120 int mpcc_id; member in struct:power_on_mpc_mem_pwr_params
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn32/
H A Ddcn32_hwseq.c439 int mpcc_id = pipe_ctx->plane_res.hubp->inst; local
475 int mpcc_id = pipe_ctx->plane_res.hubp->inst; local
563 int mpcc_id = pipe_ctx->plane_res.hubp->inst; local
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/linux-master/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_mpc.c62 void mpc3_mpc_init_single_inst(struct mpc *mpc, unsigned int mpcc_id) argument
113 enum dc_lut_mode mpc3_get_ogam_current(struct mpc *mpc, int mpcc_id) argument
92 mpc3_set_dwb_mux( struct mpc *mpc, int dwb_id, int mpcc_id) argument
151 mpc3_power_on_ogam_lut( struct mpc *mpc, int mpcc_id, bool power_on) argument
171 mpc3_configure_ogam_lut( struct mpc *mpc, int mpcc_id, bool is_ram_a) argument
218 mpc3_program_luta(struct mpc *mpc, int mpcc_id, const struct pwl_params *params) argument
251 mpc3_program_lutb(struct mpc *mpc, int mpcc_id, const struct pwl_params *params) argument
285 mpc3_program_ogam_pwl( struct mpc *mpc, int mpcc_id, const struct pwl_result_data *rgb, uint32_t num) argument
324 mpc3_set_output_gamma( struct mpc *mpc, int mpcc_id, const struct pwl_params *params) argument
1049 program_gamut_remap( struct dcn30_mpc *mpc30, int mpcc_id, const uint16_t *regval, int select) argument
1108 mpc3_set_gamut_remap( struct mpc *mpc, int mpcc_id, const struct mpc_grph_gamut_adjustment *adjust) argument
1143 read_gamut_remap(struct dcn30_mpc *mpc30, int mpcc_id, uint16_t *regval, uint32_t *select) argument
1181 mpc3_get_gamut_remap(struct mpc *mpc, int mpcc_id, struct mpc_grph_gamut_adjustment *adjust) argument
1398 mpcc3_acquire_rmu(struct mpc *mpc, int mpcc_id, int rmu_idx) argument
1417 mpcc3_release_rmu(struct mpc *mpc, int mpcc_id) argument
1439 int mpcc_id; local
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/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
H A Ddcn20_hwseq.c989 int mpcc_id = pipe_ctx->plane_res.hubp->inst; local
1012 int mpcc_id = pipe_ctx->plane_res.hubp->inst; local
2793 int mpcc_id; local
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn30/
H A Ddcn30_resource.c1432 dcn30_acquire_post_bldn_3dlut( struct resource_context *res_ctx, const struct resource_pool *pool, int mpcc_id, struct dc_3dlut **lut, struct dc_transfer_func **shaper) argument
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
H A Ddcn10_hwseq.c2675 int mpcc_id; local
2658 dcn10_update_visual_confirm_color(struct dc *dc, struct pipe_ctx *pipe_ctx, int mpcc_id) argument
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn32/
H A Ddcn32_resource.c1592 dcn32_acquire_post_bldn_3dlut( struct resource_context *res_ctx, const struct resource_pool *pool, int mpcc_id, struct dc_3dlut **lut, struct dc_transfer_func **shaper) argument

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