| /freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | AllocationOrder.cpp | 29 AllocationOrder::AllocationOrder(unsigned VirtReg, argument
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| H A D | LiveIntervalUnion.cpp | 29 void LiveIntervalUnion::unify(LiveInterval &VirtReg, const LiveRange &Range) { argument
56 void LiveIntervalUnion::extract(LiveInterval &VirtReg, const LiveRange &Range) { argument
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| H A D | RegisterCoalescer.h | 62 CoalescerPair(unsigned VirtReg, unsigned PhysReg, argument
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| H A D | RegAllocBasic.cpp | 144 bool RABasic::LRE_CanEraseVirtReg(unsigned VirtReg) { argument
159 void RABasic::LRE_WillShrinkVirtReg(unsigned VirtReg) { argument
204 spillInterferences(LiveInterval &VirtReg, unsigned PhysReg, SmallVectorImpl<unsigned> &SplitVRegs) argument
256 selectOrSplit(LiveInterval &VirtReg, SmallVectorImpl<unsigned> &SplitVRegs) argument
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| H A D | LiveRegMatrix.cpp | 104 void LiveRegMatrix::assign(LiveInterval &VirtReg, unsigned PhysReg) { argument
121 void LiveRegMatrix::unassign(LiveInterval &VirtReg) { argument
146 checkRegMaskInterference(LiveInterval &VirtReg, unsigned PhysReg) argument
164 checkRegUnitInterference(LiveInterval &VirtReg, unsigned PhysReg) argument
186 checkInterference(LiveInterval &VirtReg, unsigned PhysReg) argument
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| H A D | PHIElimination.cpp | 221 static bool isImplicitlyDefined(unsigned VirtReg, argument
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| H A D | VirtRegMap.cpp | 101 bool VirtRegMap::hasPreferredPhys(Register VirtReg) { argument
110 bool VirtRegMap::hasKnownPreference(Register VirtReg) { argument
314 Register VirtReg = Register::index2VirtReg(Idx); local
517 Register VirtReg local
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| H A D | InlineSpiller.cpp | 543 bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg, MachineInstr &MI) { argument
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| H A D | LiveDebugVariables.cpp | 603 void LDVImpl::mapVirtReg(unsigned VirtReg, UserValue *EC) { argument
609 UserValue *LDVImpl::lookupVirtReg(unsigned VirtReg) { argument
1193 Register VirtReg = Loc.getReg(); local
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| H A D | RegAllocFast.cpp | 86 Register VirtReg; ///< Virtual register number. member in struct:__anon1790::RegAllocFast::LiveReg
91 explicit LiveReg(Register VirtReg) : VirtReg(VirtReg) {} argument
203 LiveRegMap::iterator findLiveVirtReg(Register VirtReg) { argument
248 getStackSpaceFor(Register VirtReg) argument
267 mayLiveOut(Register VirtReg) argument
296 mayLiveIn(Register VirtReg) argument
315 spill(MachineBasicBlock::iterator Before, Register VirtReg, MCPhysReg AssignedReg, bool Kill) argument
343 reload(MachineBasicBlock::iterator Before, Register VirtReg, MCPhysReg PhysReg) argument
397 killVirtReg(Register VirtReg) argument
407 spillVirtReg(MachineBasicBlock::iterator MI, Register VirtReg) argument
612 Register VirtReg = LR.VirtReg; local
663 const Register VirtReg = LR.VirtReg; local
754 Register VirtReg = MO.getReg(); local
778 defineVirtReg(MachineInstr &MI, unsigned OpNum, Register VirtReg, Register Hint) argument
809 reloadVirtReg(MachineInstr &MI, unsigned OpNum, Register VirtReg, Register Hint) argument
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| H A D | RegAllocGreedy.cpp | 259 void setStage(const LiveInterval &VirtReg, LiveRangeStage Stage) { argument
636 LRE_CanEraseVirtReg(unsigned VirtReg) argument
651 LRE_WillShrinkVirtReg(unsigned VirtReg) argument
762 tryAssign(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<unsigned> &NewVRegs, const SmallVirtRegSet &FixedRegisters) argument
809 canReassign(LiveInterval &VirtReg, unsigned PrevReg) argument
872 canEvictInterference(LiveInterval &VirtReg, unsigned PhysReg, bool IsHint, EvictionCost &MaxCost, const SmallVirtRegSet &FixedRegisters) argument
969 canEvictInterferenceInRange(LiveInterval &VirtReg, unsigned PhysReg, SlotIndex Start, SlotIndex End, EvictionCost &MaxCost) argument
1022 getCheapestEvicteeWeight(const AllocationOrder &Order, LiveInterval &VirtReg, SlotIndex Start, SlotIndex End, float *BestEvictweight) argument
1048 evictInterference(LiveInterval &VirtReg, unsigned PhysReg, SmallVectorImpl<unsigned> &NewVRegs) argument
1106 tryEvict(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<unsigned> &NewVRegs, unsigned CostPerUseLimit, const SmallVirtRegSet &FixedRegisters) argument
1821 isSplitBenefitWorthCost(LiveInterval &VirtReg) argument
1829 tryRegionSplit(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<unsigned> &NewVRegs) argument
1872 calculateRegionSplitCost(LiveInterval &VirtReg, AllocationOrder &Order, BlockFrequency &BestCost, unsigned &NumCands, bool IgnoreCSR, bool *CanCauseEvictionChain) argument
1972 doRegionSplit(LiveInterval &VirtReg, unsigned BestCand, bool HasCompact, SmallVectorImpl<unsigned> &NewVRegs) argument
2019 tryBlockSplit(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<unsigned> &NewVRegs) argument
2086 tryInstructionSplit(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<unsigned> &NewVRegs) argument
2229 tryLocalSplit(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<unsigned> &NewVRegs) argument
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIPreAllocateWWMRegs.cpp | 128 const Register VirtReg = MO.getReg(); local
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| /freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ScheduleDAGInstrs.h | 53 unsigned VirtReg; member in struct:llvm::VReg2SUnit
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZRegisterInfo.cpp | 77 SystemZRegisterInfo::getRegAllocationHints(unsigned VirtReg, argument
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMBaseRegisterInfo.cpp | 301 ARMBaseRegisterInfo::getRegAllocationHints(unsigned VirtReg, argument
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