| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCSubtarget.cpp | 54 PPCSubtarget::PPCSubtarget(const Triple &TT, const std::string &CPU, argument
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/ |
| H A D | RISCVMCTargetDesc.cpp | 47 static MCRegisterInfo *createRISCVMCRegisterInfo(const Triple &TT) { argument
65 static MCSubtargetInfo *createRISCVMCSubtargetInfo(const Triple &TT, argument
83 const Triple &TT = STI.getTargetTriple(); local
53 createRISCVMCAsmInfo(const MCRegisterInfo &MRI, const Triple &TT, const MCTargetOptions &Options) argument
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/ |
| H A D | SparcMCTargetDesc.cpp | 61 static MCRegisterInfo *createSparcMCRegisterInfo(const Triple &TT) { argument
68 createSparcMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { argument
35 createSparcMCAsmInfo(const MCRegisterInfo &MRI, const Triple &TT, const MCTargetOptions &Options) argument
45 createSparcV9MCAsmInfo(const MCRegisterInfo &MRI, const Triple &TT, const MCTargetOptions &Options) argument
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/VE/MCTargetDesc/ |
| H A D | VEMCTargetDesc.cpp | 34 static MCAsmInfo *createVEMCAsmInfo(const MCRegisterInfo &MRI, const Triple &TT, argument
49 static MCRegisterInfo *createVEMCRegisterInfo(const Triple &TT) { argument
55 static MCSubtargetInfo *createVEMCSubtargetInfo(const Triple &TT, StringRef CPU, argument
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VETargetMachine.cpp | 67 VETargetMachine::VETargetMachine(const Target &T, const Triple &TT, argument
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/MCTargetDesc/ |
| H A D | WebAssemblyAsmBackend.cpp | 133 MCAsmBackend *llvm::createWebAssemblyAsmBackend(const Triple &TT) { argument
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/XCore/ |
| H A D | XCoreTargetMachine.cpp | 46 XCoreTargetMachine::XCoreTargetMachine(const Target &T, const Triple &TT, argument
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | LLVMTargetMachine.cpp | 76 LLVMTargetMachine(const Target &T, StringRef DataLayoutString, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/ExecutionEngine/Orc/ |
| H A D | LLJIT.cpp | 34 auto &TT = JTMB->getTargetTriple(); local
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/IR/ |
| H A D | Mangler.cpp | 184 emitLinkerFlagsForGlobalCOFF(raw_ostream &OS, const GlobalValue *GV, const Triple &TT, Mangler &Mangler) argument
|
| /freebsd-12-stable/contrib/llvm-project/clang/lib/Basic/Targets/ |
| H A D | AMDGPU.h | 73 static bool isAMDGCN(const llvm::Triple &TT) { argument
77 static bool isR600(const llvm::Triple &TT) { argument
|
| /freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/ExecutionEngine/Orc/ |
| H A D | ObjectLinkingLayer.h | 63 modifyPassConfig(MaterializationResponsibility &MR, const Triple &TT, jitlink::PassConfiguration &Config) argument
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Support/ |
| H A D | AArch64TargetParser.cpp | 182 bool AArch64::isX18ReservedByDefault(const Triple &TT) { argument
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64Subtarget.cpp | 177 AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU, argument
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| H A D | AMDGPUAsmBackend.cpp | 206 ELFAMDGPUAsmBackend(const Target &T, const Triple &TT, uint8_t ABIVersion) : argument
|
| H A D | AMDGPUMCTargetDesc.cpp | 59 static MCRegisterInfo *createAMDGPUMCRegisterInfo(const Triple &TT) { argument
69 createAMDGPUMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { argument
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AVR/MCTargetDesc/ |
| H A D | AVRMCTargetDesc.cpp | 47 static MCRegisterInfo *createAVRMCRegisterInfo(const Triple &TT) { argument
54 static MCSubtargetInfo *createAVRMCSubtargetInfo(const Triple &TT, argument
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/BPF/MCTargetDesc/ |
| H A D | BPFMCTargetDesc.cpp | 41 static MCRegisterInfo *createBPFMCRegisterInfo(const Triple &TT) { argument
47 static MCSubtargetInfo *createBPFMCSubtargetInfo(const Triple &TT, argument
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonTargetMachine.cpp | 204 HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT, argument
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCELFStreamer.cpp | 152 MCStreamer *createHexagonELFStreamer(Triple const &TT, MCContext &Context, argument
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/ |
| H A D | LanaiMCTargetDesc.cpp | 54 createLanaiMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { argument
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsMCTargetDesc.cpp | 48 StringRef MIPS_MC::selectMipsCPU(const Triple &TT, StringRef CPU) { argument
71 static MCRegisterInfo *createMipsMCRegisterInfo(const Triple &TT) { argument
77 static MCSubtargetInfo *createMipsMCSubtargetInfo(const Triple &TT, argument
83 createMipsMCAsmInfo(const MCRegisterInfo &MRI, const Triple &TT, const MCTargetOptions &Options) argument
[all...] |
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSubtarget.cpp | 70 MipsSubtarget::MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS, argument
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| H A D | PPCMCCodeEmitter.cpp | 218 const Triple &TT = STI.getTargetTriple(); local
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVTargetMachine.cpp | 43 static StringRef computeDataLayout(const Triple &TT) { argument
52 static Reloc::Model getEffectiveRelocModel(const Triple &TT, argument
59 RISCVTargetMachine::RISCVTargetMachine(const Target &T, const Triple &TT, argument
|