1//===-- AMDGPUMCTargetDesc.cpp - AMDGPU Target Descriptions ---------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// This file provides AMDGPU specific target descriptions.
11//
12//===----------------------------------------------------------------------===//
13
14#include "AMDGPUMCTargetDesc.h"
15#include "AMDGPUELFStreamer.h"
16#include "AMDGPUInstPrinter.h"
17#include "AMDGPUMCAsmInfo.h"
18#include "AMDGPUTargetStreamer.h"
19#include "SIDefines.h"
20#include "TargetInfo/AMDGPUTargetInfo.h"
21#include "llvm/MC/MCAsmBackend.h"
22#include "llvm/MC/MCCodeEmitter.h"
23#include "llvm/MC/MCContext.h"
24#include "llvm/MC/MCInstrAnalysis.h"
25#include "llvm/MC/MCInstrInfo.h"
26#include "llvm/MC/MCObjectWriter.h"
27#include "llvm/MC/MCRegisterInfo.h"
28#include "llvm/MC/MCStreamer.h"
29#include "llvm/MC/MCSubtargetInfo.h"
30#include "llvm/MC/MachineLocation.h"
31#include "llvm/Support/ErrorHandling.h"
32#include "llvm/Support/TargetRegistry.h"
33
34using namespace llvm;
35
36#define GET_INSTRINFO_MC_DESC
37#include "AMDGPUGenInstrInfo.inc"
38
39#define GET_SUBTARGETINFO_MC_DESC
40#include "AMDGPUGenSubtargetInfo.inc"
41
42#define NoSchedModel NoSchedModelR600
43#define GET_SUBTARGETINFO_MC_DESC
44#include "R600GenSubtargetInfo.inc"
45#undef NoSchedModelR600
46
47#define GET_REGINFO_MC_DESC
48#include "AMDGPUGenRegisterInfo.inc"
49
50#define GET_REGINFO_MC_DESC
51#include "R600GenRegisterInfo.inc"
52
53static MCInstrInfo *createAMDGPUMCInstrInfo() {
54  MCInstrInfo *X = new MCInstrInfo();
55  InitAMDGPUMCInstrInfo(X);
56  return X;
57}
58
59static MCRegisterInfo *createAMDGPUMCRegisterInfo(const Triple &TT) {
60  MCRegisterInfo *X = new MCRegisterInfo();
61  if (TT.getArch() == Triple::r600)
62    InitR600MCRegisterInfo(X, 0);
63  else
64    InitAMDGPUMCRegisterInfo(X, 0);
65  return X;
66}
67
68static MCSubtargetInfo *
69createAMDGPUMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
70  if (TT.getArch() == Triple::r600)
71    return createR600MCSubtargetInfoImpl(TT, CPU, FS);
72  return createAMDGPUMCSubtargetInfoImpl(TT, CPU, FS);
73}
74
75static MCInstPrinter *createAMDGPUMCInstPrinter(const Triple &T,
76                                                unsigned SyntaxVariant,
77                                                const MCAsmInfo &MAI,
78                                                const MCInstrInfo &MII,
79                                                const MCRegisterInfo &MRI) {
80  if (T.getArch() == Triple::r600)
81    return new R600InstPrinter(MAI, MII, MRI);
82  else
83    return new AMDGPUInstPrinter(MAI, MII, MRI);
84}
85
86static MCTargetStreamer *createAMDGPUAsmTargetStreamer(MCStreamer &S,
87                                                      formatted_raw_ostream &OS,
88                                                      MCInstPrinter *InstPrint,
89                                                      bool isVerboseAsm) {
90  return new AMDGPUTargetAsmStreamer(S, OS);
91}
92
93static MCTargetStreamer * createAMDGPUObjectTargetStreamer(
94                                                   MCStreamer &S,
95                                                   const MCSubtargetInfo &STI) {
96  return new AMDGPUTargetELFStreamer(S, STI);
97}
98
99static MCStreamer *createMCStreamer(const Triple &T, MCContext &Context,
100                                    std::unique_ptr<MCAsmBackend> &&MAB,
101                                    std::unique_ptr<MCObjectWriter> &&OW,
102                                    std::unique_ptr<MCCodeEmitter> &&Emitter,
103                                    bool RelaxAll) {
104  return createAMDGPUELFStreamer(T, Context, std::move(MAB), std::move(OW),
105                                 std::move(Emitter), RelaxAll);
106}
107
108namespace {
109
110class AMDGPUMCInstrAnalysis : public MCInstrAnalysis {
111public:
112  explicit AMDGPUMCInstrAnalysis(const MCInstrInfo *Info)
113      : MCInstrAnalysis(Info) {}
114
115  bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
116                      uint64_t &Target) const override {
117    if (Inst.getNumOperands() == 0 || !Inst.getOperand(0).isImm() ||
118        Info->get(Inst.getOpcode()).OpInfo[0].OperandType !=
119            MCOI::OPERAND_PCREL)
120      return false;
121
122    int64_t Imm = Inst.getOperand(0).getImm();
123    // Our branches take a simm16, but we need two extra bits to account for
124    // the factor of 4.
125    APInt SignedOffset(18, Imm * 4, true);
126    Target = (SignedOffset.sext(64) + Addr + Size).getZExtValue();
127    return true;
128  }
129};
130
131} // end anonymous namespace
132
133static MCInstrAnalysis *createAMDGPUMCInstrAnalysis(const MCInstrInfo *Info) {
134  return new AMDGPUMCInstrAnalysis(Info);
135}
136
137extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTargetMC() {
138
139  TargetRegistry::RegisterMCInstrInfo(getTheGCNTarget(), createAMDGPUMCInstrInfo);
140  TargetRegistry::RegisterMCInstrInfo(getTheAMDGPUTarget(), createR600MCInstrInfo);
141  for (Target *T : {&getTheAMDGPUTarget(), &getTheGCNTarget()}) {
142    RegisterMCAsmInfo<AMDGPUMCAsmInfo> X(*T);
143
144    TargetRegistry::RegisterMCRegInfo(*T, createAMDGPUMCRegisterInfo);
145    TargetRegistry::RegisterMCSubtargetInfo(*T, createAMDGPUMCSubtargetInfo);
146    TargetRegistry::RegisterMCInstPrinter(*T, createAMDGPUMCInstPrinter);
147    TargetRegistry::RegisterMCInstrAnalysis(*T, createAMDGPUMCInstrAnalysis);
148    TargetRegistry::RegisterMCAsmBackend(*T, createAMDGPUAsmBackend);
149    TargetRegistry::RegisterELFStreamer(*T, createMCStreamer);
150  }
151
152  // R600 specific registration
153  TargetRegistry::RegisterMCCodeEmitter(getTheAMDGPUTarget(),
154                                        createR600MCCodeEmitter);
155  TargetRegistry::RegisterObjectTargetStreamer(
156      getTheAMDGPUTarget(), createAMDGPUObjectTargetStreamer);
157
158  // GCN specific registration
159  TargetRegistry::RegisterMCCodeEmitter(getTheGCNTarget(),
160                                        createSIMCCodeEmitter);
161
162  TargetRegistry::RegisterAsmTargetStreamer(getTheGCNTarget(),
163                                            createAMDGPUAsmTargetStreamer);
164  TargetRegistry::RegisterObjectTargetStreamer(
165      getTheGCNTarget(), createAMDGPUObjectTargetStreamer);
166}
167