| /freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetInstrInfo.h | 469 unsigned SubIdx; member in struct:llvm::TargetInstrInfo::RegSubRegPairAndIdx
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | DetectDeadLanes.cpp | 242 unsigned SubIdx = MI.getOperand(OpNum + 1).getImm(); local
246 unsigned SubIdx = MI.getOperand(3).getImm(); local
266 unsigned SubIdx = MI.getOperand(2).getImm(); local
316 unsigned SubIdx = MI.getOperand(OpNum + 1).getImm(); local
322 unsigned SubIdx = MI.getOperand(3).getImm(); local
334 unsigned SubIdx = MI.getOperand(2).getImm(); local
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| H A D | ExpandPostRAPseudos.cpp | 86 unsigned SubIdx = MI->getOperand(3).getImm(); local
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| H A D | MachineCopyPropagation.cpp | 343 unsigned SubIdx = TRI->getSubRegIndex(PreviousSrc, Src); local
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| H A D | MachineInstr.cpp | 1139 substituteRegister(Register FromReg, Register ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo) argument
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| H A D | MachineOperand.cpp | 75 void MachineOperand::substVirtReg(Register Reg, unsigned SubIdx, argument
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| H A D | MachineVerifier.cpp | 1679 unsigned SubIdx = MO->getSubReg(); local
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| H A D | RegisterCoalescer.cpp | 1680 updateRegDefsUses(unsigned SrcReg, unsigned DstReg, unsigned SubIdx) argument
2208 const unsigned SubIdx; member in class:__anon1798::JoinVals
2373 JoinVals(LiveRange &LR, unsigned Reg, unsigned SubIdx, LaneBitmask LaneMask, SmallVectorImpl<VNInfo*> &newVNInfo, const CoalescerPair &cp, LiveIntervals *lis, const TargetRegisterInfo *TRI, bool SubRangeJoin, bool TrackSubRegLiveness) argument
2865 usesLanes(const MachineInstr &MI, unsigned Reg, unsigned SubIdx, LaneBitmask Lanes) const argument
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| H A D | SplitKit.cpp | 512 buildSingleSubRegCopy(unsigned FromReg, unsigned ToReg, MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, unsigned SubIdx, LiveInterval &DestLI, bool Late, SlotIndex Def) argument
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| H A D | TargetInstrInfo.cpp | 379 getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx, unsigned &Size, unsigned &Offset, const MachineFunction &MF) const argument
409 reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const argument
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| H A D | TargetRegisterInfo.cpp | 115 OS << ":sub(" << SubIdx << ')'; local
89 printReg(Register Reg, const TargetRegisterInfo *TRI, unsigned SubIdx, const MachineRegisterInfo *MRI) argument
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| H A D | TwoAddressInstructionPass.cpp | 1765 unsigned SubIdx = mi->getOperand(3).getImm(); local
1819 unsigned SubIdx = MI.getOperand(i+1).getImm(); local
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 18296 uint64_t SubIdx = IndexC->getZExtValue() / SubVT.getVectorNumElements(); local
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| H A D | TargetLowering.cpp | 934 unsigned SubIdx = Idx.getZExtValue(); local
936 BaseElts.insertBits(APInt::getNullValue(NumSubElts), SubIdx); local
963 ConstantSDNode *SubIdx = dyn_cast<ConstantSDNode>(Op.getOperand(1)); local
2335 unsigned SubIdx = Idx.getZExtValue(); local
2342 BaseElts.insertBits(APInt::getNullValue(NumSubElts), SubIdx); local
2361 ConstantSDNode *SubIdx = dyn_cast<ConstantSDNode>(Op.getOperand(1)); local
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/MC/ |
| H A D | MCRegisterInfo.cpp | 24 MCRegisterInfo::getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, argument
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 2430 AddSubReg(const MachineInstrBuilder &MIB, unsigned Reg, unsigned SubIdx, unsigned State, const TargetRegisterInfo *TRI) argument
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 715 unsigned SubIdx; local
2247 unsigned SubIdx = SubIndices[Idx]; local
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.cpp | 1013 AddDReg(MachineInstrBuilder &MIB, unsigned Reg, unsigned SubIdx, unsigned State, const TargetRegisterInfo *TRI) const argument
1689 reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const argument
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| H A D | ARMBaseRegisterInfo.cpp | 458 emitLoadConstPool( MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const argument
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| H A D | ARMISelDAGToDAG.cpp | 2807 unsigned SubIdx = is64BitVector ? ARM::dsub_0 : ARM::qsub_0; local
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| H A D | ThumbRegisterInfo.cpp | 61 emitThumb1LoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) argument
81 emitThumb2LoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) argument
103 emitLoadConstPool( MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const argument
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 2398 unsigned SubIdx = Off == 0 ? Hexagon::isub_lo : Hexagon::isub_hi; local
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| H A D | HexagonISelLoweringHVX.cpp | 314 SDValue SubIdx = DAG.getNode(ISD::AND, dl, MVT::i32, {Idx, Mask}); local
742 SDValue SubIdx = getIndexInWord32(IdxV, ElemTy, DAG); local
780 unsigned SubIdx; local
903 unsigned SubIdx = (Idx == 0) ? Hexagon::vsub_lo : Hexagon::vsub_hi; local
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 816 unsigned SubIdx = 0; local
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 640 reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const argument
4017 expandNOVLXLoad(MachineInstrBuilder &MIB, const TargetRegisterInfo *TRI, const MCInstrDesc &LoadDesc, const MCInstrDesc &BroadcastDesc, unsigned SubIdx) argument
4040 expandNOVLXStore(MachineInstrBuilder &MIB, const TargetRegisterInfo *TRI, const MCInstrDesc &StoreDesc, const MCInstrDesc &ExtractDesc, unsigned SubIdx) argument
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