| /freebsd-current/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | ScalarEvolutionDivision.cpp | 151 SmallVector<const SCEV *, 2> Qs, Rs; local
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| /freebsd-current/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCCompound.cpp | 201 MCOperand Rs, Rt; local
[all...] |
| /freebsd-current/contrib/llvm-project/llvm/lib/Target/MSP430/Disassembler/ |
| H A D | MSP430Disassembler.cpp | 154 static AddrMode DecodeSrcAddrMode(unsigned Rs, unsigned As) { argument
182 unsigned Rs = fieldFromInstruction(Insn, 8, 4); local
188 unsigned Rs = fieldFromInstruction(Insn, 0, 4); local
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| /freebsd-current/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonGenInsert.cpp | 128 RegisterSet &insert(const RegisterSet &Rs) { argument
131 RegisterSet &remove(const RegisterSet &Rs) { argument
[all...] |
| H A D | HexagonBitSimplify.cpp | 136 RegisterSet &insert(const RegisterSet &Rs) { argument
141 RegisterSet &remove(const RegisterSet &Rs) { argument
[all...] |
| H A D | HexagonAsmPrinter.cpp | 410 MCOperand &Rs = Inst.getOperand(1); local
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| H A D | HexagonSplitDouble.cpp | 147 const USet &Rs = I.second; local
373 Register Rs = MI->getOperand(1).getReg(); local
474 collectIndRegsForLoop(const MachineLoop *L, USet &Rs) argument
579 USet Rs; local
[all...] |
| H A D | HexagonConstExtenders.cpp | 293 Register Rs; member in struct:__anon2330::HexagonConstExtenders::ExtExpr
447 HCE::Register Rs; member in struct:__anon2330::PrintRegister
1505 Register Rs = ExtI.second.Rs; // Only one reg allowed now. local
1802 Register Rs = MI.getOperand(IsSub ? 3 : 2); local
[all...] |
| H A D | HexagonFrameLowering.cpp | 2511 Register Rd = RdOp.getReg(), Rs = RsOp.getReg(); local
[all...] |
| H A D | HexagonInstrInfo.cpp | 1346 Register Rs = Op2.getReg(); local
[all...] |
| /freebsd-current/contrib/llvm-project/lldb/source/Plugins/Instruction/RISCV/ |
| H A D | RISCVInstructions.h | 28 struct Rs { struct in namespace:lldb_private
[all...] |
| H A D | RISCVCInstructions.h | [all...] |
| /freebsd-current/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVMergeBaseOffset.cpp | 179 Register Rs = TailAdd.getOperand(1).getReg(); local
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| /freebsd-current/contrib/mandoc/ |
| H A D | mdoc.h | 152 struct mdoc_rs Rs; member in union:mdoc_data
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| /freebsd-current/contrib/llvm-project/llvm/lib/Target/Mips/Disassembler/ |
| H A D | MipsDisassembler.cpp | 578 InsnType Rs = fieldFromInstruction(insn, 16, 5); local
592 InsnType Rs = fieldFromInstruction(insn, 21, 5); local
617 InsnType Rs = fieldFromInstruction(insn, 21, 5); local
647 InsnType Rs = fieldFromInstruction(insn, 16, 5); local
690 InsnType Rs = fieldFromInstruction(insn, 21, 5); local
720 InsnType Rs = fieldFromInstruction(insn, 16, 5); local
761 InsnType Rs = fieldFromInstruction(insn, 16, 5); local
800 InsnType Rs = fieldFromInstruction(insn, 16, 5); local
842 InsnType Rs = fieldFromInstruction(insn, 21, 5); local
887 InsnType Rs = fieldFromInstruction(insn, 21, 5); local
929 InsnType Rs = fieldFromInstruction(insn, 21, 5); local
978 InsnType Rs = fieldFromInstruction(insn, 21, 5); local
1034 InsnType Rs = fieldFromInstruction(Insn, 21, 5); local
1076 InsnType Rs = fieldFromInstruction(Insn, 21, 5); local
1094 InsnType Rs = fieldFromInstruction(Insn, 21, 5); local
2441 InsnType Rs = fieldFromInstruction(insn, 16, 5); local
2490 InsnType Rs = fieldFromInstruction(insn, 16, 5); local
[all...] |
| /freebsd-current/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/ |
| H A D | AArch64Disassembler.cpp | 1408 unsigned Rs = fieldFromInstruction(insn, 16, 5); local
2050 unsigned Rs = fieldFromInstruction(insn, 16, 5); local
[all...] |
| /freebsd-current/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 3514 Register Rs = RegInfo.createVirtualRegister(&Mips::GPR32RegClass); local
|
| /freebsd-current/contrib/llvm-project/llvm/lib/Target/Hexagon/AsmParser/ |
| H A D | HexagonAsmParser.cpp | 1627 MCOperand &Rs = Inst.getOperand(2); local
1647 MCOperand &Rs = Inst.getOperand(2); local
1667 MCOperand &Rs = Inst.getOperand(2); local
1690 MCOperand &Rs = Inst.getOperand(1); local
1723 MCOperand &Rs = Inst.getOperand(1); local
1733 MCOperand &Rs = Inst.getOperand(1); local
1775 MCOperand &Rs = Inst.getOperand(1); local
1792 MCOperand &Rs = Inst.getOperand(1); local
1921 MCOperand &Rs = Inst.getOperand(1); local
[all...] |
| /freebsd-current/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 1704 unsigned Rs = fieldFromInstruction(Val, 8, 4); local
|
| /freebsd-current/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM/ |
| H A D | EmulateInstructionARM.cpp | 10134 uint32_t Rs = ReadCoreReg(s, &success); local
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| /freebsd-current/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 5392 unsigned Rs = Inst.getOperand(0).getReg(); local
5405 unsigned Rs = Inst.getOperand(0).getReg(); local
|