| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMFrameLowering.cpp | 2239 const TargetRegisterClass &RC = ARM::GPRRegClass; local
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| H A D | ARMFastISel.cpp | 297 fastEmitInst_r(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0) argument
319 fastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, unsigned Op1) argument
346 fastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, uint64_t Imm) argument
371 fastEmitInst_i(unsigned MachineInstOpcode, const TargetRegisterClass *RC, uint64_t Imm) argument
463 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass : local
479 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass : local
532 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass local
659 const TargetRegisterClass* RC = TLI.getRegClassFor(VT); local
833 const TargetRegisterClass *RC = isThumb2 ? &ARM::tGPRRegClass local
905 const TargetRegisterClass *RC; local
1469 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass local
1641 const TargetRegisterClass *RC; local
2489 const TargetRegisterClass *RC = isThumb2 ? &ARM::tGPRRegClass local
2685 const TargetRegisterClass *RC = RCTbl[isThumb2][isSingleInstr]; local
3053 const TargetRegisterClass *RC = &ARM::rGPRRegClass; local
[all...] |
| /netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | MachineFunction.cpp | 634 addLiveIn(MCRegister PReg, const TargetRegisterClass *RC) argument
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| H A D | MachineVerifier.cpp | 1919 const TargetRegisterClass *RC = MRI->getRegClassOrNull(Reg); local
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| H A D | ModuloSchedule.cpp | 547 const TargetRegisterClass *RC = MRI.getRegClass(Def); local
663 const TargetRegisterClass *RC = MRI.getRegClass(Def); local
1037 const TargetRegisterClass *RC = MRI.getRegClass(reg); local
1440 auto RC = MRI.getRegClass(Reg); local
1457 phi(Register LoopReg, Optional<Register> InitReg, const TargetRegisterClass *RC) argument
1507 undef(const TargetRegisterClass *RC) argument
1636 auto RC = MRI.getRegClass(PhiR); local
1853 auto RC = MRI.getRegClass(MI.getOperand(0).getReg()); local
[all...] |
| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXAsmPrinter.cpp | 286 const TargetRegisterClass *RC = MRI->getRegClass(Reg); local
579 const TargetRegisterClass *RC = MRI->getRegClass(Reg); local
1644 const TargetRegisterClass *RC = MRI->getRegClass(vr); local
1663 const TargetRegisterClass *RC = TRI->getRegClass(i); local
[all...] |
| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 1431 const TargetRegisterClass * RC; local
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| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCFrameLowering.cpp | 2276 const TargetRegisterClass &RC = Subtarget.isPPC64() ? G8RC : GPRC; local
2463 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); local
2638 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); local
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| H A D | PPCFastISel.cpp | 450 PPCEmitLoad(MVT VT, Register &ResultReg, Address &Addr, const TargetRegisterClass *RC, bool IsZExt, unsigned FP64LoadOpc) argument
608 const TargetRegisterClass *RC = local
625 const TargetRegisterClass *RC = MRI.getRegClass(SrcReg); local
987 auto RC = MRI.getRegClass(SrcReg); local
1050 const TargetRegisterClass *RC = &PPC::F8RCRegClass; local
1129 const TargetRegisterClass *RC = &PPC::F8RCRegClass; local
1173 const TargetRegisterClass *RC = local
1224 auto RC = MRI.getRegClass(SrcReg); local
1279 const TargetRegisterClass *RC = local
1441 const TargetRegisterClass *RC = local
1453 const TargetRegisterClass *RC = local
1767 const TargetRegisterClass *RC = local
1776 const TargetRegisterClass *RC = local
1924 const TargetRegisterClass *RC = local
2008 const TargetRegisterClass *RC; local
2069 const TargetRegisterClass *RC = &PPC::G8RC_and_G8RC_NOX0RegClass; local
2120 PPCMaterialize32BitInt(int64_t Imm, const TargetRegisterClass *RC) argument
2152 PPCMaterialize64BitInt(int64_t Imm, const TargetRegisterClass *RC) argument
2223 const TargetRegisterClass *RC = local
2405 const TargetRegisterClass *RC = ((VT == MVT::i64) ? &PPC::G8RCRegClass : local
2424 fastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, uint64_t Imm) argument
2443 fastEmitInst_r(unsigned MachineInstOpcode, const TargetRegisterClass* RC, unsigned Op0) argument
2456 fastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass* RC, unsigned Op0, unsigned Op1) argument
[all...] |
| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| H A D | SystemZInstrInfo.cpp | 547 const TargetRegisterClass *RC = local
574 const TargetRegisterClass *RC = MRI.getRegClass(DstReg); local
862 storeRegToStackSlot( MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
877 loadRegFromStackSlot( MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
1198 const TargetRegisterClass *RC = TRI->getRegClass(MCOI.RegClass); local
1574 getLoadStoreOpcodes(const TargetRegisterClass *RC, unsigned &LoadOpcode, unsigned &StoreOpcode) const argument
[all...] |
| H A D | SystemZISelDAGToDAG.cpp | 1717 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), DL, MVT::i32); local
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| /netbsd-current/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| H A D | CodeGenRegisters.cpp | 944 CodeGenRegisterClass &RC = *I; local
1201 CodeGenRegisterClass &RC = RegClasses.back(); local
1247 addToMaps(CodeGenRegisterClass *RC) argument
1259 getOrCreateSubClass(const CodeGenRegisterClass *RC, const CodeGenRegister::Vec *Members, StringRef Name) argument
2136 inferCommonSubClass(CodeGenRegisterClass *RC) argument
2176 inferSubClassWithSubReg(CodeGenRegisterClass *RC) argument
2226 inferMatchingSuperRegClass(CodeGenRegisterClass *RC, std::list<CodeGenRegisterClass>::iterator FirstSubRegRC) argument
2304 CodeGenRegisterClass *RC = &*I; local
[all...] |
| H A D | GlobalISelEmitter.cpp | 1387 const CodeGenRegisterClass &RC; member in class:__anon3305::RegisterBankOperandMatcher
1390 RegisterBankOperandMatcher(unsigned InsnVarID, unsigned OpIdx, const CodeGenRegisterClass &RC) argument
[all...] |
| /netbsd-current/sys/external/bsd/sljit/dist/sljit_src/ |
| H A D | sljitNativePPC_common.c | 134 #define RC(flags) ((flags & ALT_SET_FLAGS) >> 10) macro
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| /netbsd-current/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | TargetInstrInfo.h | 1024 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
1036 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 845 const TargetRegisterClass *RC = getRegClassFor(RegVT); local
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| H A D | HexagonFrameLowering.cpp | 1421 const TargetRegisterClass *RC = HRI.getMinimalPhysRegClass(Reg); local
1485 const TargetRegisterClass *RC = HRI.getMinimalPhysRegClass(Reg); local
1700 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(S->Reg); local
1712 const TargetRegisterClass *RC local
1579 needToReserveScavengingSpillSlots(MachineFunction &MF, const HexagonRegisterInfo &HRI, const TargetRegisterClass *RC) argument
1847 auto *RC = &Hexagon::HvxVRRegClass; local
1883 auto *RC = &Hexagon::HvxVRRegClass; local
2229 const TargetRegisterClass *RC = nullptr; member in struct:SlotInfo
2291 auto *RC = HII.getRegClass(In.getDesc(), OpNum, &HRI, MF); local
2459 auto *RC = HII.getRegClass(SI.getDesc(), 2, &HRI, MF); local
[all...] |
| H A D | HexagonConstPropagation.cpp | 719 LatticeCell RC = Cells.get(DefR.Reg); local
1397 LatticeCell RC; local
1086 getCell(const RegisterSubReg &R, const CellMap &Inputs, LatticeCell &RC) argument
1413 LatticeCell RC; local
1464 LatticeCell RC; local
1480 LatticeCell RC; local
1529 LatticeCell RC; local
1948 LatticeCell RC; local
1970 LatticeCell RC; local
2004 LatticeCell RC = Outputs.get(DefR.Reg); local
2013 LatticeCell RC = Outputs.get(DefR.Reg); local
2047 LatticeCell RC = Outputs.get(DefR.Reg); local
2059 LatticeCell RC = Outputs.get(DefR.Reg); local
2108 LatticeCell RC = Outputs.get(DefR.Reg); local
2140 LatticeCell RC = Outputs.get(DefR.Reg); local
2162 LatticeCell RC = Outputs.get(DefR.Reg); local
2215 const TargetRegisterClass *RC = MRI->getRegClass(R.Reg); local
2367 const TargetRegisterClass *RC = MRI->getRegClass(Reg); local
2643 LatticeCell RC; local
2700 LatticeCell RC = Outputs.get(DefR.Reg); local
2759 LatticeCell RC = Outputs.get(DefR.Reg); local
2774 LatticeCell RC = Outputs.get(DefR.Reg); local
2875 const TargetRegisterClass *RC = MRI->getRegClass(R); local
3002 const TargetRegisterClass *RC = MRI->getRegClass(DefR.Reg); local
3031 const TargetRegisterClass *RC = MRI->getRegClass(DefR.Reg); local
3068 const TargetRegisterClass *RC = MRI->getRegClass(DefR.Reg); local
3100 const TargetRegisterClass *RC = MRI->getRegClass(DefR.Reg); local
[all...] |
| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64FrameLowering.cpp | 2865 const TargetRegisterClass &RC = AArch64::GPR64RegClass; local
2921 const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg); local
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| H A D | AArch64InstrInfo.cpp | 619 const TargetRegisterClass *RC = local
745 const TargetRegisterClass *RC = nullptr; local
3598 storeRegToStackSlot( MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
3752 loadRegFromStackSlot( MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
[all...] |
| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURegisterBankInfo.cpp | 276 AMDGPURegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC, argument
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| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 894 const TargetRegisterClass *RC; local
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| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 1807 const TargetRegisterClass *RC = &VE::I64RegClass; local
1857 const TargetRegisterClass *RC = &VE::I64RegClass; local
1973 const TargetRegisterClass *RC = MRI.getRegClass(DstReg); local
2276 const TargetRegisterClass *RC = &VE::I64RegClass; local
2618 const TargetRegisterClass *RC = nullptr; local
[all...] |
| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 318 addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) { argument
372 addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) { argument
3038 const TargetRegisterClass *RC = &Mips::GPR32RegClass; local
3107 const TargetRegisterClass *RC = &Mips::GPR32RegClass; local
3522 const TargetRegisterClass *RC = local
3574 const TargetRegisterClass *RC = local
3821 const TargetRegisterClass *RC = &Mips::MSA128WRegClass; local
3850 const TargetRegisterClass *RC = &Mips::MSA128DRegClass; local
[all...] |
| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86FastISel.cpp | 472 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); local
772 const TargetRegisterClass *RC = nullptr; local
1800 const TargetRegisterClass *RC = nullptr; local
1884 const TargetRegisterClass *RC; member in struct:DivRemEntry
2043 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); local
2203 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); local
2344 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); local
2371 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); local
2441 const TargetRegisterClass *RC = TLI.getRegClassFor(DstVT); local
2459 X86SelectFPExtOrFPTrunc(const Instruction *I, unsigned TargetOpc, const TargetRegisterClass *RC) argument
2615 const TargetRegisterClass *RC = TLI.getRegClassFor(MVT::v8i16); local
2674 const TargetRegisterClass *RC = nullptr; local
2830 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); local
3118 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); local
3867 const TargetRegisterClass *RC = TLI.getRegClassFor(TLI.getPointerTy(DL)); local
3953 fastEmitInst_rrrr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, unsigned Op1, unsigned Op2, unsigned Op3) argument
[all...] |