| /freebsd-current/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsOptimizePICCall.cpp | 138 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(Reg); local
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| /freebsd-current/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | RegisterBankInfo.h | 623 getRegBankFromRegClass(const TargetRegisterClass &RC, LLT Ty) const { argument
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| /freebsd-current/contrib/llvm-project/llvm/include/llvm/CodeGen/MIRParser/ |
| H A D | MIParser.h | 45 const TargetRegisterClass *RC; member in union:llvm::VRegInfo::__anon1610
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| /freebsd-current/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86RegisterInfo.cpp | 85 X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, argument
110 X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC, argument
262 getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const argument
[all...] |
| H A D | X86PreTileConfig.cpp | 243 const TargetRegisterClass *RC = TRI->getRegClass(X86::TILERegClassID); local
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| /freebsd-current/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64RegisterBankInfo.cpp | 240 AArch64RegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC, argument
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| /freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MachineSSAUpdater.cpp | 54 void MachineSSAUpdater::Initialize(const TargetRegisterClass *RC) { argument
119 InsertNewDef(unsigned Opcode, MachineBasicBlock *BB, MachineBasicBlock::iterator I, const TargetRegisterClass *RC, MachineRegisterInfo *MRI, const TargetInstrInfo *TII) argument
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| H A D | DetectDeadLanes.cpp | 170 const TargetRegisterClass *RC = MRI->getRegClass(DefReg); local
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| H A D | VirtRegMap.cpp | 95 unsigned VirtRegMap::createSpillSlot(const TargetRegisterClass *RC) { argument
131 const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg); local
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| H A D | RegAllocGreedy.cpp | 325 const TargetRegisterClass &RC = *MRI->getRegClass(Reg); local
540 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg.reg()); local
[all...] |
| H A D | PHIElimination.cpp | 310 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg); local
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| H A D | RegisterScavenging.cpp | 112 BitVector RegScavenger::getRegsAvailable(const TargetRegisterClass *RC) { argument
296 scavengeRegisterBackwards(const TargetRegisterClass &RC, MachineBasicBlock::iterator To, bool RestoreAfter, int SPAdj, bool AllowSpill) argument
381 const TargetRegisterClass &RC = *MRI.getRegClass(VReg); local
[all...] |
| H A D | StackMaps.cpp | 280 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(MOI->getReg()); local
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| /freebsd-current/sys/contrib/zstd/programs/ |
| H A D | Makefile | 266 RC ?= windres macro
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| /freebsd-current/contrib/llvm-project/llvm/lib/Target/XCore/Disassembler/ |
| H A D | XCoreDisassembler.cpp | 69 static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo) { argument
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| /freebsd-current/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYFrameLowering.cpp | 440 const TargetRegisterClass *RC = &CSKY::GPRRegClass; local
478 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); local
500 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); local
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| /freebsd-current/contrib/llvm-project/llvm/lib/MCA/HardwareUnits/ |
| H A D | RegisterFile.cpp | 169 const MCRegisterClass &RC = MRI.getRegClass(RCE.RegisterClassID); local
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| /freebsd-current/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcInstrInfo.cpp | 527 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const argument
567 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const argument
[all...] |
| /freebsd-current/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonRegisterInfo.cpp | 421 getHexagonSubRegIndex( const TargetRegisterClass &RC, unsigned GenIdx) const argument
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| H A D | HexagonBlockRanges.cpp | 278 auto &RC = *MRI.getRegClass(R.Reg); local
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| /freebsd-current/share/mk/ |
| H A D | sys.mk | 246 RC ?= f77 macro
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| /freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | FunctionLoweringInfo.cpp | 539 getCatchPadExceptionPointerVReg( const Value *CPI, const TargetRegisterClass *RC) argument
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| /freebsd-current/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64SIMDInstrOpt.cpp | 91 const TargetRegisterClass RC; member in struct:__anon2209::AArch64SIMDInstrOpt::InstReplInfo
356 const TargetRegisterClass *RC = &AArch64::FPR128RegClass; local
[all...] |
| /freebsd-current/contrib/llvm-project/llvm/lib/LTO/ |
| H A D | LTOCodeGenerator.cpp | 282 int RC = sys::ExecuteAndWait(Args[0], Args); local
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| /freebsd-current/contrib/llvm-project/clang/lib/CodeGen/ |
| H A D | CGHLSLRuntime.cpp | 179 llvm::hlsl::ResourceClass RC = Buf.IsCBuffer local
194 addBufferResourceAnnotation(llvm::GlobalVariable *GV, llvm::hlsl::ResourceClass RC, llvm::hlsl::ResourceKind RK, bool IsROV, llvm::hlsl::ElementType ET, BufferResBinding &Binding) argument
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