Searched defs:RC (Results 176 - 200 of 256) sorted by relevance

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/freebsd-current/contrib/llvm-project/llvm/tools/llvm-cov/
H A DCodeCoverage.cpp624 int RC = local
/freebsd-current/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrInfo.cpp96 auto *RC = TargetInstrInfo::getRegClass(MCID, OpNum, TRI, MF); local
1142 const TargetRegisterClass *RC; local
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.h1380 auto *RC = MRI.getRegClass(P.Reg); local
H A DSIFrameLowering.cpp34 findUnusedRegister(MachineRegisterInfo &MRI, const LiveRegUnits &LiveUnits, const TargetRegisterClass &RC) argument
49 findScratchNonCalleeSaveRegister( MachineRegisterInfo &MRI, LiveRegUnits &LiveUnits, const TargetRegisterClass &RC, bool Unused = false) argument
349 const TargetRegisterClass *RC = TRI.getPhysRegBaseClass(SuperReg); local
1345 const TargetRegisterClass *RC = TRI->getPhysRegBaseClass(Reg); local
1505 const TargetRegisterClass &RC = *TRI->getWaveMaskRegClass(); local
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/freebsd-current/sys/dev/mthca/
H A Dmthca_qp.c285 enum { RC, UC, UD, RD, RDEE, MLX, NUM_TRANS }; enumerator in enum:__anon337
/freebsd-current/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonVLIWPacketizer.cpp1433 const TargetRegisterClass *RC local
375 promoteToDotCur(MachineInstr &MI, SDep::Kind DepType, MachineBasicBlock::iterator &MII, const TargetRegisterClass* RC) argument
406 canPromoteToDotCur(const MachineInstr &MI, const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII, const TargetRegisterClass *RC) argument
457 promoteToDotNew(MachineInstr &MI, SDep::Kind DepType, MachineBasicBlock::iterator &MII, const TargetRegisterClass* RC) argument
849 canPromoteToDotNew(const MachineInstr &MI, const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII, const TargetRegisterClass* RC) argument
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H A DHexagonHardwareLoops.cpp900 const TargetRegisterClass *RC = MRI->getRegClass(R); local
1584 const TargetRegisterClass *RC = MRI->getRegClass(R); local
1890 const TargetRegisterClass *RC = MRI->getRegClass(PR); local
H A DHexagonExpandCondsets.cpp591 const TargetRegisterClass *RC = MRI->getRegClass(LI.reg()); local
615 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(PhysS); local
1118 const TargetRegisterClass *RC = MRI->getRegClass(RR.Reg); local
/freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp1975 Register FastISel::createResultReg(const TargetRegisterClass *RC) { argument
1996 fastEmitInst_(unsigned MachineInstOpcode, const TargetRegisterClass *RC) argument
2005 fastEmitInst_r(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0) argument
2026 fastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, unsigned Op1) argument
2050 fastEmitInst_rrr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, unsigned Op1, unsigned Op2) argument
2077 fastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, uint64_t Imm) argument
2100 fastEmitInst_rii(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, uint64_t Imm1, uint64_t Imm2) argument
2125 fastEmitInst_f(unsigned MachineInstOpcode, const TargetRegisterClass *RC, const ConstantFP *FPImm) argument
2145 fastEmitInst_rri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, unsigned Op1, uint64_t Imm) argument
2171 fastEmitInst_i(unsigned MachineInstOpcode, const TargetRegisterClass *RC, uint64_t Imm) argument
2193 const TargetRegisterClass *RC = MRI.getRegClass(Op0); local
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/freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/
H A DScheduleDAGInstrs.cpp380 const TargetRegisterClass &RC = *MRI.getRegClass(Reg); local
H A DRegAllocFast.cpp420 const TargetRegisterClass &RC = *MRI->getRegClass(Reg); local
447 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); local
546 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); local
604 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); local
869 const TargetRegisterClass &RC local
965 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); local
1043 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); local
1071 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); local
1134 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); local
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H A DTargetLoweringBase.cpp1308 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy]; local
H A DTargetInstrInfo.cpp388 bool TargetInstrInfo::getStackSlotRange(const TargetRegisterClass *RC, argument
471 const TargetRegisterClass *RC = MRI.getRegClass(FoldReg); local
545 const TargetRegisterClass *RC local
714 const TargetRegisterClass *RC = canFoldCopy(MI, *this, Ops[0]); local
1066 const TargetRegisterClass *RC = Root.getRegClassConstraint(0, TII, TRI); local
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/freebsd-current/contrib/llvm-project/clang/lib/CodeGen/
H A DCGExprComplex.cpp939 llvm::Value *RC = Builder.CreateFMul(CdD, RHSr); // rc local
/freebsd-current/contrib/llvm-project/clang/lib/AST/
H A DDeclTemplate.cpp132 const Expr *RC = getRequiresClause(); local
/freebsd-current/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp1425 const TargetRegisterClass * RC; local
/freebsd-current/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelDAGToDAG.cpp1797 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), DL, MVT::i32); local
/freebsd-current/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp1410 const TargetRegisterClass *RC; local
1779 const TargetRegisterClass *RC; local
2319 const TargetRegisterClass *RC = local
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXAsmPrinter.cpp296 const TargetRegisterClass *RC = MRI->getRegClass(Reg); local
584 const TargetRegisterClass *RC = MRI->getRegClass(Reg); local
1733 const TargetRegisterClass *RC = MRI->getRegClass(vr); local
1752 const TargetRegisterClass *RC = TRI->getRegClass(i); local
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/X86/Disassembler/
H A DX86DisassemblerDecoder.h784 uint8_t RC; member in struct:llvm::X86Disassembler::InternalInstruction
/freebsd-current/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86InstructionSelector.cpp210 static unsigned getSubRegIndex(const TargetRegisterClass *RC) { argument
252 const TargetRegisterClass *RC = local
1552 const TargetRegisterClass *RC local
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFrameLowering.cpp2769 const TargetRegisterClass &RC = ARM::GPRRegClass; local
/freebsd-current/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp696 const TargetRegisterClass *RC = MRI->getRegClass(MI->getOperand(0).getReg()); local
785 const TargetRegisterClass *RC = MRI.getRegClass(RegC); local
1528 const TargetRegisterClass *RC = local
1561 const TargetRegisterClass *RC = local
1911 StoreRegToStackSlot( MachineFunction &MF, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr *> &NewMIs) const argument
1933 storeRegToStackSlotNoUpd( MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
1953 storeRegToStackSlot( MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const argument
1968 LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr *> &NewMIs) const argument
1978 loadRegFromStackSlotNoUpd( MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
2000 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const argument
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp231 unsigned fastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC, argument
354 const TargetRegisterClass *RC = &Mips::GPR32RegClass; local
389 const TargetRegisterClass *RC = &Mips::FGR32RegClass; local
359 materialize32BitInt(int64_t Imm, const TargetRegisterClass *RC) argument
395 const TargetRegisterClass *RC = &Mips::AFGR64RegClass; local
410 const TargetRegisterClass *RC = &Mips::GPR32RegClass; local
432 const TargetRegisterClass *RC = &Mips::GPR32RegClass; local
1022 const TargetRegisterClass *RC; local
1334 const TargetRegisterClass *RC; member in struct:AllocatedReg
1336 AllocatedReg(const TargetRegisterClass *RC, unsigned Reg) argument
2116 fastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, unsigned Op1) argument
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUInstPrinter.cpp756 const MCRegisterClass RC = MRI.getRegClass(RCID); local

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