/freebsd-current/contrib/llvm-project/llvm/tools/llvm-cov/ |
H A D | CodeCoverage.cpp | 624 int RC = local
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86InstrInfo.cpp | 96 auto *RC = TargetInstrInfo::getRegClass(MCID, OpNum, TRI, MF); local 1142 const TargetRegisterClass *RC; local [all...] |
/freebsd-current/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIInstrInfo.h | 1380 auto *RC = MRI.getRegClass(P.Reg); local
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H A D | SIFrameLowering.cpp | 34 findUnusedRegister(MachineRegisterInfo &MRI, const LiveRegUnits &LiveUnits, const TargetRegisterClass &RC) argument 49 findScratchNonCalleeSaveRegister( MachineRegisterInfo &MRI, LiveRegUnits &LiveUnits, const TargetRegisterClass &RC, bool Unused = false) argument 349 const TargetRegisterClass *RC = TRI.getPhysRegBaseClass(SuperReg); local 1345 const TargetRegisterClass *RC = TRI->getPhysRegBaseClass(Reg); local 1505 const TargetRegisterClass &RC = *TRI->getWaveMaskRegClass(); local [all...] |
/freebsd-current/sys/dev/mthca/ |
H A D | mthca_qp.c | 285 enum { RC, UC, UD, RD, RDEE, MLX, NUM_TRANS }; enumerator in enum:__anon337
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonVLIWPacketizer.cpp | 1433 const TargetRegisterClass *RC local 375 promoteToDotCur(MachineInstr &MI, SDep::Kind DepType, MachineBasicBlock::iterator &MII, const TargetRegisterClass* RC) argument 406 canPromoteToDotCur(const MachineInstr &MI, const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII, const TargetRegisterClass *RC) argument 457 promoteToDotNew(MachineInstr &MI, SDep::Kind DepType, MachineBasicBlock::iterator &MII, const TargetRegisterClass* RC) argument 849 canPromoteToDotNew(const MachineInstr &MI, const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII, const TargetRegisterClass* RC) argument [all...] |
H A D | HexagonHardwareLoops.cpp | 900 const TargetRegisterClass *RC = MRI->getRegClass(R); local 1584 const TargetRegisterClass *RC = MRI->getRegClass(R); local 1890 const TargetRegisterClass *RC = MRI->getRegClass(PR); local
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H A D | HexagonExpandCondsets.cpp | 591 const TargetRegisterClass *RC = MRI->getRegClass(LI.reg()); local 615 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(PhysS); local 1118 const TargetRegisterClass *RC = MRI->getRegClass(RR.Reg); local
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/freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | FastISel.cpp | 1975 Register FastISel::createResultReg(const TargetRegisterClass *RC) { argument 1996 fastEmitInst_(unsigned MachineInstOpcode, const TargetRegisterClass *RC) argument 2005 fastEmitInst_r(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0) argument 2026 fastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, unsigned Op1) argument 2050 fastEmitInst_rrr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, unsigned Op1, unsigned Op2) argument 2077 fastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, uint64_t Imm) argument 2100 fastEmitInst_rii(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, uint64_t Imm1, uint64_t Imm2) argument 2125 fastEmitInst_f(unsigned MachineInstOpcode, const TargetRegisterClass *RC, const ConstantFP *FPImm) argument 2145 fastEmitInst_rri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, unsigned Op1, uint64_t Imm) argument 2171 fastEmitInst_i(unsigned MachineInstOpcode, const TargetRegisterClass *RC, uint64_t Imm) argument 2193 const TargetRegisterClass *RC = MRI.getRegClass(Op0); local [all...] |
/freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | ScheduleDAGInstrs.cpp | 380 const TargetRegisterClass &RC = *MRI.getRegClass(Reg); local
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H A D | RegAllocFast.cpp | 420 const TargetRegisterClass &RC = *MRI->getRegClass(Reg); local 447 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); local 546 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); local 604 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); local 869 const TargetRegisterClass &RC local 965 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); local 1043 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); local 1071 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); local 1134 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); local [all...] |
H A D | TargetLoweringBase.cpp | 1308 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy]; local
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H A D | TargetInstrInfo.cpp | 388 bool TargetInstrInfo::getStackSlotRange(const TargetRegisterClass *RC, argument 471 const TargetRegisterClass *RC = MRI.getRegClass(FoldReg); local 545 const TargetRegisterClass *RC local 714 const TargetRegisterClass *RC = canFoldCopy(MI, *this, Ops[0]); local 1066 const TargetRegisterClass *RC = Root.getRegClassConstraint(0, TII, TRI); local [all...] |
/freebsd-current/contrib/llvm-project/clang/lib/CodeGen/ |
H A D | CGExprComplex.cpp | 939 llvm::Value *RC = Builder.CreateFMul(CdD, RHSr); // rc local
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/freebsd-current/contrib/llvm-project/clang/lib/AST/ |
H A D | DeclTemplate.cpp | 132 const Expr *RC = getRequiresClause(); local
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.cpp | 1425 const TargetRegisterClass * RC; local
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelDAGToDAG.cpp | 1797 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), DL, MVT::i32); local
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/AVR/ |
H A D | AVRISelLowering.cpp | 1410 const TargetRegisterClass *RC; local 1779 const TargetRegisterClass *RC; local 2319 const TargetRegisterClass *RC = local [all...] |
/freebsd-current/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
H A D | NVPTXAsmPrinter.cpp | 296 const TargetRegisterClass *RC = MRI->getRegClass(Reg); local 584 const TargetRegisterClass *RC = MRI->getRegClass(Reg); local 1733 const TargetRegisterClass *RC = MRI->getRegClass(vr); local 1752 const TargetRegisterClass *RC = TRI->getRegClass(i); local [all...] |
/freebsd-current/contrib/llvm-project/llvm/lib/Target/X86/Disassembler/ |
H A D | X86DisassemblerDecoder.h | 784 uint8_t RC; member in struct:llvm::X86Disassembler::InternalInstruction
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/X86/GISel/ |
H A D | X86InstructionSelector.cpp | 210 static unsigned getSubRegIndex(const TargetRegisterClass *RC) { argument 252 const TargetRegisterClass *RC = local 1552 const TargetRegisterClass *RC local [all...] |
/freebsd-current/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMFrameLowering.cpp | 2769 const TargetRegisterClass &RC = ARM::GPRRegClass; local
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.cpp | 696 const TargetRegisterClass *RC = MRI->getRegClass(MI->getOperand(0).getReg()); local 785 const TargetRegisterClass *RC = MRI.getRegClass(RegC); local 1528 const TargetRegisterClass *RC = local 1561 const TargetRegisterClass *RC = local 1911 StoreRegToStackSlot( MachineFunction &MF, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr *> &NewMIs) const argument 1933 storeRegToStackSlotNoUpd( MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 1953 storeRegToStackSlot( MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const argument 1968 LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr *> &NewMIs) const argument 1978 loadRegFromStackSlotNoUpd( MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 2000 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const argument [all...] |
/freebsd-current/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsFastISel.cpp | 231 unsigned fastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC, argument 354 const TargetRegisterClass *RC = &Mips::GPR32RegClass; local 389 const TargetRegisterClass *RC = &Mips::FGR32RegClass; local 359 materialize32BitInt(int64_t Imm, const TargetRegisterClass *RC) argument 395 const TargetRegisterClass *RC = &Mips::AFGR64RegClass; local 410 const TargetRegisterClass *RC = &Mips::GPR32RegClass; local 432 const TargetRegisterClass *RC = &Mips::GPR32RegClass; local 1022 const TargetRegisterClass *RC; local 1334 const TargetRegisterClass *RC; member in struct:AllocatedReg 1336 AllocatedReg(const TargetRegisterClass *RC, unsigned Reg) argument 2116 fastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, unsigned Op1) argument [all...] |
/freebsd-current/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
H A D | AMDGPUInstPrinter.cpp | 756 const MCRegisterClass RC = MRI.getRegClass(RCID); local
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