1//===-- X86DisassemblerDecoderInternal.h - Disassembler decoder -*- C++ -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file is part of the X86 Disassembler. 10// It contains the public interface of the instruction decoder. 11// Documentation for the disassembler can be found in X86Disassembler.h. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef LLVM_LIB_TARGET_X86_DISASSEMBLER_X86DISASSEMBLERDECODER_H 16#define LLVM_LIB_TARGET_X86_DISASSEMBLER_X86DISASSEMBLERDECODER_H 17 18#include "llvm/ADT/ArrayRef.h" 19#include "llvm/Support/X86DisassemblerDecoderCommon.h" 20 21namespace llvm { 22namespace X86Disassembler { 23// Helper macros 24#define bitFromOffset0(val) ((val) & 0x1) 25#define bitFromOffset1(val) (((val) >> 1) & 0x1) 26#define bitFromOffset2(val) (((val) >> 2) & 0x1) 27#define bitFromOffset3(val) (((val) >> 3) & 0x1) 28#define bitFromOffset4(val) (((val) >> 4) & 0x1) 29#define bitFromOffset5(val) (((val) >> 5) & 0x1) 30#define bitFromOffset6(val) (((val) >> 6) & 0x1) 31#define bitFromOffset7(val) (((val) >> 7) & 0x1) 32#define twoBitsFromOffset0(val) ((val) & 0x3) 33#define twoBitsFromOffset6(val) (((val) >> 6) & 0x3) 34#define threeBitsFromOffset0(val) ((val) & 0x7) 35#define threeBitsFromOffset3(val) (((val) >> 3) & 0x7) 36#define fiveBitsFromOffset0(val) ((val) & 0x1f) 37#define invertedBitFromOffset2(val) (((~(val)) >> 2) & 0x1) 38#define invertedBitFromOffset3(val) (((~(val)) >> 3) & 0x1) 39#define invertedBitFromOffset4(val) (((~(val)) >> 4) & 0x1) 40#define invertedBitFromOffset5(val) (((~(val)) >> 5) & 0x1) 41#define invertedBitFromOffset6(val) (((~(val)) >> 6) & 0x1) 42#define invertedBitFromOffset7(val) (((~(val)) >> 7) & 0x1) 43#define invertedFourBitsFromOffset3(val) (((~(val)) >> 3) & 0xf) 44// MOD/RM 45#define modFromModRM(modRM) twoBitsFromOffset6(modRM) 46#define regFromModRM(modRM) threeBitsFromOffset3(modRM) 47#define rmFromModRM(modRM) threeBitsFromOffset0(modRM) 48// SIB 49#define scaleFromSIB(sib) twoBitsFromOffset6(sib) 50#define indexFromSIB(sib) threeBitsFromOffset3(sib) 51#define baseFromSIB(sib) threeBitsFromOffset0(sib) 52// REX 53#define wFromREX(rex) bitFromOffset3(rex) 54#define rFromREX(rex) bitFromOffset2(rex) 55#define xFromREX(rex) bitFromOffset1(rex) 56#define bFromREX(rex) bitFromOffset0(rex) 57// REX2 58#define mFromREX2(rex2) bitFromOffset7(rex2) 59#define r2FromREX2(rex2) bitFromOffset6(rex2) 60#define x2FromREX2(rex2) bitFromOffset5(rex2) 61#define b2FromREX2(rex2) bitFromOffset4(rex2) 62#define wFromREX2(rex2) bitFromOffset3(rex2) 63#define rFromREX2(rex2) bitFromOffset2(rex2) 64#define xFromREX2(rex2) bitFromOffset1(rex2) 65#define bFromREX2(rex2) bitFromOffset0(rex2) 66// XOP 67#define rFromXOP2of3(xop) invertedBitFromOffset7(xop) 68#define xFromXOP2of3(xop) invertedBitFromOffset6(xop) 69#define bFromXOP2of3(xop) invertedBitFromOffset5(xop) 70#define mmmmmFromXOP2of3(xop) fiveBitsFromOffset0(xop) 71#define wFromXOP3of3(xop) bitFromOffset7(xop) 72#define vvvvFromXOP3of3(xop) invertedFourBitsFromOffset3(xop) 73#define lFromXOP3of3(xop) bitFromOffset2(xop) 74#define ppFromXOP3of3(xop) twoBitsFromOffset0(xop) 75// VEX2 76#define rFromVEX2of2(vex) invertedBitFromOffset7(vex) 77#define vvvvFromVEX2of2(vex) invertedFourBitsFromOffset3(vex) 78#define lFromVEX2of2(vex) bitFromOffset2(vex) 79#define ppFromVEX2of2(vex) twoBitsFromOffset0(vex) 80// VEX3 81#define rFromVEX2of3(vex) invertedBitFromOffset7(vex) 82#define xFromVEX2of3(vex) invertedBitFromOffset6(vex) 83#define bFromVEX2of3(vex) invertedBitFromOffset5(vex) 84#define mmmmmFromVEX2of3(vex) fiveBitsFromOffset0(vex) 85#define wFromVEX3of3(vex) bitFromOffset7(vex) 86#define vvvvFromVEX3of3(vex) invertedFourBitsFromOffset3(vex) 87#define lFromVEX3of3(vex) bitFromOffset2(vex) 88#define ppFromVEX3of3(vex) twoBitsFromOffset0(vex) 89// EVEX 90#define rFromEVEX2of4(evex) invertedBitFromOffset7(evex) 91#define xFromEVEX2of4(evex) invertedBitFromOffset6(evex) 92#define bFromEVEX2of4(evex) invertedBitFromOffset5(evex) 93#define r2FromEVEX2of4(evex) invertedBitFromOffset4(evex) 94#define b2FromEVEX2of4(evex) bitFromOffset3(evex) 95#define mmmFromEVEX2of4(evex) threeBitsFromOffset0(evex) 96#define wFromEVEX3of4(evex) bitFromOffset7(evex) 97#define vvvvFromEVEX3of4(evex) invertedFourBitsFromOffset3(evex) 98#define x2FromEVEX3of4(evex) invertedBitFromOffset2(evex) 99#define ppFromEVEX3of4(evex) twoBitsFromOffset0(evex) 100#define zFromEVEX4of4(evex) bitFromOffset7(evex) 101#define l2FromEVEX4of4(evex) bitFromOffset6(evex) 102#define lFromEVEX4of4(evex) bitFromOffset5(evex) 103#define bFromEVEX4of4(evex) bitFromOffset4(evex) 104#define v2FromEVEX4of4(evex) invertedBitFromOffset3(evex) 105#define aaaFromEVEX4of4(evex) threeBitsFromOffset0(evex) 106#define nfFromEVEX4of4(evex) bitFromOffset2(evex) 107 108// These enums represent Intel registers for use by the decoder. 109#define REGS_8BIT \ 110 ENTRY(AL) \ 111 ENTRY(CL) \ 112 ENTRY(DL) \ 113 ENTRY(BL) \ 114 ENTRY(AH) \ 115 ENTRY(CH) \ 116 ENTRY(DH) \ 117 ENTRY(BH) \ 118 ENTRY(R8B) \ 119 ENTRY(R9B) \ 120 ENTRY(R10B) \ 121 ENTRY(R11B) \ 122 ENTRY(R12B) \ 123 ENTRY(R13B) \ 124 ENTRY(R14B) \ 125 ENTRY(R15B) \ 126 ENTRY(R16B) \ 127 ENTRY(R17B) \ 128 ENTRY(R18B) \ 129 ENTRY(R19B) \ 130 ENTRY(R20B) \ 131 ENTRY(R21B) \ 132 ENTRY(R22B) \ 133 ENTRY(R23B) \ 134 ENTRY(R24B) \ 135 ENTRY(R25B) \ 136 ENTRY(R26B) \ 137 ENTRY(R27B) \ 138 ENTRY(R28B) \ 139 ENTRY(R29B) \ 140 ENTRY(R30B) \ 141 ENTRY(R31B) \ 142 ENTRY(SPL) \ 143 ENTRY(BPL) \ 144 ENTRY(SIL) \ 145 ENTRY(DIL) 146 147#define EA_BASES_16BIT \ 148 ENTRY(BX_SI) \ 149 ENTRY(BX_DI) \ 150 ENTRY(BP_SI) \ 151 ENTRY(BP_DI) \ 152 ENTRY(SI) \ 153 ENTRY(DI) \ 154 ENTRY(BP) \ 155 ENTRY(BX) \ 156 ENTRY(R8W) \ 157 ENTRY(R9W) \ 158 ENTRY(R10W) \ 159 ENTRY(R11W) \ 160 ENTRY(R12W) \ 161 ENTRY(R13W) \ 162 ENTRY(R14W) \ 163 ENTRY(R15W) \ 164 ENTRY(R16W) \ 165 ENTRY(R17W) \ 166 ENTRY(R18W) \ 167 ENTRY(R19W) \ 168 ENTRY(R20W) \ 169 ENTRY(R21W) \ 170 ENTRY(R22W) \ 171 ENTRY(R23W) \ 172 ENTRY(R24W) \ 173 ENTRY(R25W) \ 174 ENTRY(R26W) \ 175 ENTRY(R27W) \ 176 ENTRY(R28W) \ 177 ENTRY(R29W) \ 178 ENTRY(R30W) \ 179 ENTRY(R31W) 180 181#define REGS_16BIT \ 182 ENTRY(AX) \ 183 ENTRY(CX) \ 184 ENTRY(DX) \ 185 ENTRY(BX) \ 186 ENTRY(SP) \ 187 ENTRY(BP) \ 188 ENTRY(SI) \ 189 ENTRY(DI) \ 190 ENTRY(R8W) \ 191 ENTRY(R9W) \ 192 ENTRY(R10W) \ 193 ENTRY(R11W) \ 194 ENTRY(R12W) \ 195 ENTRY(R13W) \ 196 ENTRY(R14W) \ 197 ENTRY(R15W) \ 198 ENTRY(R16W) \ 199 ENTRY(R17W) \ 200 ENTRY(R18W) \ 201 ENTRY(R19W) \ 202 ENTRY(R20W) \ 203 ENTRY(R21W) \ 204 ENTRY(R22W) \ 205 ENTRY(R23W) \ 206 ENTRY(R24W) \ 207 ENTRY(R25W) \ 208 ENTRY(R26W) \ 209 ENTRY(R27W) \ 210 ENTRY(R28W) \ 211 ENTRY(R29W) \ 212 ENTRY(R30W) \ 213 ENTRY(R31W) 214 215#define EA_BASES_32BIT \ 216 ENTRY(EAX) \ 217 ENTRY(ECX) \ 218 ENTRY(EDX) \ 219 ENTRY(EBX) \ 220 ENTRY(sib) \ 221 ENTRY(EBP) \ 222 ENTRY(ESI) \ 223 ENTRY(EDI) \ 224 ENTRY(R8D) \ 225 ENTRY(R9D) \ 226 ENTRY(R10D) \ 227 ENTRY(R11D) \ 228 ENTRY(R12D) \ 229 ENTRY(R13D) \ 230 ENTRY(R14D) \ 231 ENTRY(R15D) \ 232 ENTRY(R16D) \ 233 ENTRY(R17D) \ 234 ENTRY(R18D) \ 235 ENTRY(R19D) \ 236 ENTRY(R20D) \ 237 ENTRY(R21D) \ 238 ENTRY(R22D) \ 239 ENTRY(R23D) \ 240 ENTRY(R24D) \ 241 ENTRY(R25D) \ 242 ENTRY(R26D) \ 243 ENTRY(R27D) \ 244 ENTRY(R28D) \ 245 ENTRY(R29D) \ 246 ENTRY(R30D) \ 247 ENTRY(R31D) 248 249#define REGS_32BIT \ 250 ENTRY(EAX) \ 251 ENTRY(ECX) \ 252 ENTRY(EDX) \ 253 ENTRY(EBX) \ 254 ENTRY(ESP) \ 255 ENTRY(EBP) \ 256 ENTRY(ESI) \ 257 ENTRY(EDI) \ 258 ENTRY(R8D) \ 259 ENTRY(R9D) \ 260 ENTRY(R10D) \ 261 ENTRY(R11D) \ 262 ENTRY(R12D) \ 263 ENTRY(R13D) \ 264 ENTRY(R14D) \ 265 ENTRY(R15D) \ 266 ENTRY(R16D) \ 267 ENTRY(R17D) \ 268 ENTRY(R18D) \ 269 ENTRY(R19D) \ 270 ENTRY(R20D) \ 271 ENTRY(R21D) \ 272 ENTRY(R22D) \ 273 ENTRY(R23D) \ 274 ENTRY(R24D) \ 275 ENTRY(R25D) \ 276 ENTRY(R26D) \ 277 ENTRY(R27D) \ 278 ENTRY(R28D) \ 279 ENTRY(R29D) \ 280 ENTRY(R30D) \ 281 ENTRY(R31D) 282 283#define EA_BASES_64BIT \ 284 ENTRY(RAX) \ 285 ENTRY(RCX) \ 286 ENTRY(RDX) \ 287 ENTRY(RBX) \ 288 ENTRY(sib64) \ 289 ENTRY(RBP) \ 290 ENTRY(RSI) \ 291 ENTRY(RDI) \ 292 ENTRY(R8) \ 293 ENTRY(R9) \ 294 ENTRY(R10) \ 295 ENTRY(R11) \ 296 ENTRY(R12) \ 297 ENTRY(R13) \ 298 ENTRY(R14) \ 299 ENTRY(R15) \ 300 ENTRY(R16) \ 301 ENTRY(R17) \ 302 ENTRY(R18) \ 303 ENTRY(R19) \ 304 ENTRY(R20) \ 305 ENTRY(R21) \ 306 ENTRY(R22) \ 307 ENTRY(R23) \ 308 ENTRY(R24) \ 309 ENTRY(R25) \ 310 ENTRY(R26) \ 311 ENTRY(R27) \ 312 ENTRY(R28) \ 313 ENTRY(R29) \ 314 ENTRY(R30) \ 315 ENTRY(R31) 316 317#define REGS_64BIT \ 318 ENTRY(RAX) \ 319 ENTRY(RCX) \ 320 ENTRY(RDX) \ 321 ENTRY(RBX) \ 322 ENTRY(RSP) \ 323 ENTRY(RBP) \ 324 ENTRY(RSI) \ 325 ENTRY(RDI) \ 326 ENTRY(R8) \ 327 ENTRY(R9) \ 328 ENTRY(R10) \ 329 ENTRY(R11) \ 330 ENTRY(R12) \ 331 ENTRY(R13) \ 332 ENTRY(R14) \ 333 ENTRY(R15) \ 334 ENTRY(R16) \ 335 ENTRY(R17) \ 336 ENTRY(R18) \ 337 ENTRY(R19) \ 338 ENTRY(R20) \ 339 ENTRY(R21) \ 340 ENTRY(R22) \ 341 ENTRY(R23) \ 342 ENTRY(R24) \ 343 ENTRY(R25) \ 344 ENTRY(R26) \ 345 ENTRY(R27) \ 346 ENTRY(R28) \ 347 ENTRY(R29) \ 348 ENTRY(R30) \ 349 ENTRY(R31) 350 351#define REGS_MMX \ 352 ENTRY(MM0) \ 353 ENTRY(MM1) \ 354 ENTRY(MM2) \ 355 ENTRY(MM3) \ 356 ENTRY(MM4) \ 357 ENTRY(MM5) \ 358 ENTRY(MM6) \ 359 ENTRY(MM7) 360 361#define REGS_XMM \ 362 ENTRY(XMM0) \ 363 ENTRY(XMM1) \ 364 ENTRY(XMM2) \ 365 ENTRY(XMM3) \ 366 ENTRY(XMM4) \ 367 ENTRY(XMM5) \ 368 ENTRY(XMM6) \ 369 ENTRY(XMM7) \ 370 ENTRY(XMM8) \ 371 ENTRY(XMM9) \ 372 ENTRY(XMM10) \ 373 ENTRY(XMM11) \ 374 ENTRY(XMM12) \ 375 ENTRY(XMM13) \ 376 ENTRY(XMM14) \ 377 ENTRY(XMM15) \ 378 ENTRY(XMM16) \ 379 ENTRY(XMM17) \ 380 ENTRY(XMM18) \ 381 ENTRY(XMM19) \ 382 ENTRY(XMM20) \ 383 ENTRY(XMM21) \ 384 ENTRY(XMM22) \ 385 ENTRY(XMM23) \ 386 ENTRY(XMM24) \ 387 ENTRY(XMM25) \ 388 ENTRY(XMM26) \ 389 ENTRY(XMM27) \ 390 ENTRY(XMM28) \ 391 ENTRY(XMM29) \ 392 ENTRY(XMM30) \ 393 ENTRY(XMM31) 394 395#define REGS_YMM \ 396 ENTRY(YMM0) \ 397 ENTRY(YMM1) \ 398 ENTRY(YMM2) \ 399 ENTRY(YMM3) \ 400 ENTRY(YMM4) \ 401 ENTRY(YMM5) \ 402 ENTRY(YMM6) \ 403 ENTRY(YMM7) \ 404 ENTRY(YMM8) \ 405 ENTRY(YMM9) \ 406 ENTRY(YMM10) \ 407 ENTRY(YMM11) \ 408 ENTRY(YMM12) \ 409 ENTRY(YMM13) \ 410 ENTRY(YMM14) \ 411 ENTRY(YMM15) \ 412 ENTRY(YMM16) \ 413 ENTRY(YMM17) \ 414 ENTRY(YMM18) \ 415 ENTRY(YMM19) \ 416 ENTRY(YMM20) \ 417 ENTRY(YMM21) \ 418 ENTRY(YMM22) \ 419 ENTRY(YMM23) \ 420 ENTRY(YMM24) \ 421 ENTRY(YMM25) \ 422 ENTRY(YMM26) \ 423 ENTRY(YMM27) \ 424 ENTRY(YMM28) \ 425 ENTRY(YMM29) \ 426 ENTRY(YMM30) \ 427 ENTRY(YMM31) 428 429#define REGS_ZMM \ 430 ENTRY(ZMM0) \ 431 ENTRY(ZMM1) \ 432 ENTRY(ZMM2) \ 433 ENTRY(ZMM3) \ 434 ENTRY(ZMM4) \ 435 ENTRY(ZMM5) \ 436 ENTRY(ZMM6) \ 437 ENTRY(ZMM7) \ 438 ENTRY(ZMM8) \ 439 ENTRY(ZMM9) \ 440 ENTRY(ZMM10) \ 441 ENTRY(ZMM11) \ 442 ENTRY(ZMM12) \ 443 ENTRY(ZMM13) \ 444 ENTRY(ZMM14) \ 445 ENTRY(ZMM15) \ 446 ENTRY(ZMM16) \ 447 ENTRY(ZMM17) \ 448 ENTRY(ZMM18) \ 449 ENTRY(ZMM19) \ 450 ENTRY(ZMM20) \ 451 ENTRY(ZMM21) \ 452 ENTRY(ZMM22) \ 453 ENTRY(ZMM23) \ 454 ENTRY(ZMM24) \ 455 ENTRY(ZMM25) \ 456 ENTRY(ZMM26) \ 457 ENTRY(ZMM27) \ 458 ENTRY(ZMM28) \ 459 ENTRY(ZMM29) \ 460 ENTRY(ZMM30) \ 461 ENTRY(ZMM31) 462 463#define REGS_MASKS \ 464 ENTRY(K0) \ 465 ENTRY(K1) \ 466 ENTRY(K2) \ 467 ENTRY(K3) \ 468 ENTRY(K4) \ 469 ENTRY(K5) \ 470 ENTRY(K6) \ 471 ENTRY(K7) 472 473#define REGS_MASK_PAIRS \ 474 ENTRY(K0_K1) \ 475 ENTRY(K2_K3) \ 476 ENTRY(K4_K5) \ 477 ENTRY(K6_K7) 478 479#define REGS_SEGMENT \ 480 ENTRY(ES) \ 481 ENTRY(CS) \ 482 ENTRY(SS) \ 483 ENTRY(DS) \ 484 ENTRY(FS) \ 485 ENTRY(GS) 486 487#define REGS_DEBUG \ 488 ENTRY(DR0) \ 489 ENTRY(DR1) \ 490 ENTRY(DR2) \ 491 ENTRY(DR3) \ 492 ENTRY(DR4) \ 493 ENTRY(DR5) \ 494 ENTRY(DR6) \ 495 ENTRY(DR7) \ 496 ENTRY(DR8) \ 497 ENTRY(DR9) \ 498 ENTRY(DR10) \ 499 ENTRY(DR11) \ 500 ENTRY(DR12) \ 501 ENTRY(DR13) \ 502 ENTRY(DR14) \ 503 ENTRY(DR15) 504 505#define REGS_CONTROL \ 506 ENTRY(CR0) \ 507 ENTRY(CR1) \ 508 ENTRY(CR2) \ 509 ENTRY(CR3) \ 510 ENTRY(CR4) \ 511 ENTRY(CR5) \ 512 ENTRY(CR6) \ 513 ENTRY(CR7) \ 514 ENTRY(CR8) \ 515 ENTRY(CR9) \ 516 ENTRY(CR10) \ 517 ENTRY(CR11) \ 518 ENTRY(CR12) \ 519 ENTRY(CR13) \ 520 ENTRY(CR14) \ 521 ENTRY(CR15) 522 523#undef REGS_TMM 524#define REGS_TMM \ 525 ENTRY(TMM0) \ 526 ENTRY(TMM1) \ 527 ENTRY(TMM2) \ 528 ENTRY(TMM3) \ 529 ENTRY(TMM4) \ 530 ENTRY(TMM5) \ 531 ENTRY(TMM6) \ 532 ENTRY(TMM7) 533 534#define ALL_EA_BASES \ 535 EA_BASES_16BIT \ 536 EA_BASES_32BIT \ 537 EA_BASES_64BIT 538 539#define ALL_SIB_BASES \ 540 REGS_32BIT \ 541 REGS_64BIT 542 543#define ALL_REGS \ 544 REGS_8BIT \ 545 REGS_16BIT \ 546 REGS_32BIT \ 547 REGS_64BIT \ 548 REGS_MMX \ 549 REGS_XMM \ 550 REGS_YMM \ 551 REGS_ZMM \ 552 REGS_MASKS \ 553 REGS_MASK_PAIRS \ 554 REGS_SEGMENT \ 555 REGS_DEBUG \ 556 REGS_CONTROL \ 557 REGS_TMM \ 558 ENTRY(RIP) 559 560/// All possible values of the base field for effective-address 561/// computations, a.k.a. the Mod and R/M fields of the ModR/M byte. 562/// We distinguish between bases (EA_BASE_*) and registers that just happen 563/// to be referred to when Mod == 0b11 (EA_REG_*). 564enum EABase { 565 EA_BASE_NONE, 566#define ENTRY(x) EA_BASE_##x, 567 ALL_EA_BASES 568#undef ENTRY 569#define ENTRY(x) EA_REG_##x, 570 ALL_REGS 571#undef ENTRY 572 EA_max 573}; 574 575/// All possible values of the SIB index field. 576/// borrows entries from ALL_EA_BASES with the special case that 577/// sib is synonymous with NONE. 578/// Vector SIB: index can be XMM or YMM. 579enum SIBIndex { 580 SIB_INDEX_NONE, 581#define ENTRY(x) SIB_INDEX_##x, 582 ALL_EA_BASES 583 REGS_XMM 584 REGS_YMM 585 REGS_ZMM 586#undef ENTRY 587 SIB_INDEX_max 588}; 589 590/// All possible values of the SIB base field. 591enum SIBBase { 592 SIB_BASE_NONE, 593#define ENTRY(x) SIB_BASE_##x, 594 ALL_SIB_BASES 595#undef ENTRY 596 SIB_BASE_max 597}; 598 599/// Possible displacement types for effective-address computations. 600enum EADisplacement { 601 EA_DISP_NONE, 602 EA_DISP_8, 603 EA_DISP_16, 604 EA_DISP_32 605}; 606 607/// All possible values of the reg field in the ModR/M byte. 608enum Reg { 609#define ENTRY(x) MODRM_REG_##x, 610 ALL_REGS 611#undef ENTRY 612 MODRM_REG_max 613}; 614 615/// All possible segment overrides. 616enum SegmentOverride { 617 SEG_OVERRIDE_NONE, 618 SEG_OVERRIDE_CS, 619 SEG_OVERRIDE_SS, 620 SEG_OVERRIDE_DS, 621 SEG_OVERRIDE_ES, 622 SEG_OVERRIDE_FS, 623 SEG_OVERRIDE_GS, 624 SEG_OVERRIDE_max 625}; 626 627/// Possible values for the VEX.m-mmmm field 628enum VEXLeadingOpcodeByte { 629 VEX_LOB_0F = 0x1, 630 VEX_LOB_0F38 = 0x2, 631 VEX_LOB_0F3A = 0x3, 632 VEX_LOB_MAP4 = 0x4, 633 VEX_LOB_MAP5 = 0x5, 634 VEX_LOB_MAP6 = 0x6, 635 VEX_LOB_MAP7 = 0x7 636}; 637 638enum XOPMapSelect { 639 XOP_MAP_SELECT_8 = 0x8, 640 XOP_MAP_SELECT_9 = 0x9, 641 XOP_MAP_SELECT_A = 0xA 642}; 643 644/// Possible values for the VEX.pp/EVEX.pp field 645enum VEXPrefixCode { 646 VEX_PREFIX_NONE = 0x0, 647 VEX_PREFIX_66 = 0x1, 648 VEX_PREFIX_F3 = 0x2, 649 VEX_PREFIX_F2 = 0x3 650}; 651 652enum VectorExtensionType { 653 TYPE_NO_VEX_XOP = 0x0, 654 TYPE_VEX_2B = 0x1, 655 TYPE_VEX_3B = 0x2, 656 TYPE_EVEX = 0x3, 657 TYPE_XOP = 0x4 658}; 659 660/// The specification for how to extract and interpret a full instruction and 661/// its operands. 662struct InstructionSpecifier { 663 uint16_t operands; 664}; 665 666/// The x86 internal instruction, which is produced by the decoder. 667struct InternalInstruction { 668 // Opaque value passed to the reader 669 llvm::ArrayRef<uint8_t> bytes; 670 // The address of the next byte to read via the reader 671 uint64_t readerCursor; 672 673 // General instruction information 674 675 // The mode to disassemble for (64-bit, protected, real) 676 DisassemblerMode mode; 677 // The start of the instruction, usable with the reader 678 uint64_t startLocation; 679 // The length of the instruction, in bytes 680 size_t length; 681 682 // Prefix state 683 684 // The possible mandatory prefix 685 uint8_t mandatoryPrefix; 686 // The value of the vector extension prefix(EVEX/VEX/XOP), if present 687 uint8_t vectorExtensionPrefix[4]; 688 // The type of the vector extension prefix 689 VectorExtensionType vectorExtensionType; 690 // The value of the REX2 prefix, if present 691 uint8_t rex2ExtensionPrefix[2]; 692 // The value of the REX prefix, if present 693 uint8_t rexPrefix; 694 // The segment override type 695 SegmentOverride segmentOverride; 696 // 1 if the prefix byte, 0xf2 or 0xf3 is xacquire or xrelease 697 bool xAcquireRelease; 698 699 // Address-size override 700 bool hasAdSize; 701 // Operand-size override 702 bool hasOpSize; 703 // Lock prefix 704 bool hasLockPrefix; 705 // The repeat prefix if any 706 uint8_t repeatPrefix; 707 708 // Sizes of various critical pieces of data, in bytes 709 uint8_t registerSize; 710 uint8_t addressSize; 711 uint8_t displacementSize; 712 uint8_t immediateSize; 713 714 // Offsets from the start of the instruction to the pieces of data, which is 715 // needed to find relocation entries for adding symbolic operands. 716 uint8_t displacementOffset; 717 uint8_t immediateOffset; 718 719 // opcode state 720 721 // The last byte of the opcode, not counting any ModR/M extension 722 uint8_t opcode; 723 724 // decode state 725 726 // The type of opcode, used for indexing into the array of decode tables 727 OpcodeType opcodeType; 728 // The instruction ID, extracted from the decode table 729 uint16_t instructionID; 730 // The specifier for the instruction, from the instruction info table 731 const InstructionSpecifier *spec; 732 733 // state for additional bytes, consumed during operand decode. Pattern: 734 // consumed___ indicates that the byte was already consumed and does not 735 // need to be consumed again. 736 737 // The VEX.vvvv field, which contains a third register operand for some AVX 738 // instructions. 739 Reg vvvv; 740 741 // The writemask for AVX-512 instructions which is contained in EVEX.aaa 742 Reg writemask; 743 744 // The ModR/M byte, which contains most register operands and some portion of 745 // all memory operands. 746 bool consumedModRM; 747 uint8_t modRM; 748 749 // The SIB byte, used for more complex 32- or 64-bit memory operands 750 uint8_t sib; 751 752 // The displacement, used for memory operands 753 int32_t displacement; 754 755 // Immediates. There can be two in some cases 756 uint8_t numImmediatesConsumed; 757 uint8_t numImmediatesTranslated; 758 uint64_t immediates[2]; 759 760 // A register or immediate operand encoded into the opcode 761 Reg opcodeRegister; 762 763 // Portions of the ModR/M byte 764 765 // These fields determine the allowable values for the ModR/M fields, which 766 // depend on operand and address widths. 767 EABase eaRegBase; 768 Reg regBase; 769 770 // The Mod and R/M fields can encode a base for an effective address, or a 771 // register. These are separated into two fields here. 772 EABase eaBase; 773 EADisplacement eaDisplacement; 774 // The reg field always encodes a register 775 Reg reg; 776 777 // SIB state 778 SIBIndex sibIndexBase; 779 SIBIndex sibIndex; 780 uint8_t sibScale; 781 SIBBase sibBase; 782 783 // Embedded rounding control. 784 uint8_t RC; 785 786 ArrayRef<OperandSpecifier> operands; 787}; 788 789} // namespace X86Disassembler 790} // namespace llvm 791 792#endif 793