| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | AllocationOrder.h | 32 ArrayRef<MCPhysReg> Order; member in class:llvm::AllocationOrder
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| H A D | BreakFalseDeps.cpp | 153 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(OpRC); local
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| H A D | LocalStackSlotAllocation.cpp | 59 unsigned Order; member in class:__anon3492::FrameRef
304 unsigned Order = 0; local
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| H A D | CriticalAntiDepBreaker.cpp | 404 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(RC); local
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| H A D | RegAllocGreedy.cpp | 755 tryAssign(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<Register> &NewVRegs, const SmallVirtRegSet &FixedRegisters) argument
1015 getCheapestEvicteeWeight(const AllocationOrder &Order, LiveInterval &VirtReg, SlotIndex Start, SlotIndex End, float *BestEvictweight) argument
1099 tryEvict(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<Register> &NewVRegs, unsigned CostPerUseLimit, const SmallVirtRegSet &FixedRegisters) argument
1476 splitCanCauseEvictionChain(unsigned Evictee, GlobalSplitCandidate &Cand, unsigned BBNumber, const AllocationOrder &Order) argument
1536 splitCanCauseLocalSpill(unsigned VirtRegToSplit, GlobalSplitCandidate &Cand, unsigned BBNumber, const AllocationOrder &Order) argument
1576 calcGlobalSplitCost(GlobalSplitCandidate &Cand, const AllocationOrder &Order, bool *CanCauseEvictionChain) argument
1811 tryRegionSplit(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<Register> &NewVRegs) argument
1854 calculateRegionSplitCost(LiveInterval &VirtReg, AllocationOrder &Order, BlockFrequency &BestCost, unsigned &NumCands, bool IgnoreCSR, bool *CanCauseEvictionChain) argument
2001 tryBlockSplit(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<Register> &NewVRegs) argument
2068 tryInstructionSplit(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<Register> &NewVRegs) argument
2211 tryLocalSplit(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<Register> &NewVRegs) argument
[all...] |
| /freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | RegisterClassInfo.h | 37 std::unique_ptr<MCPhysReg[]> Order; member in struct:llvm::RegisterClassInfo::RCInfo
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| H A D | ScheduleDAG.h | 56 Order ///< Any other ordering dependency. enumerator in enum:llvm::SDep::Kind
[all...] |
| H A D | SelectionDAG.h | 378 static uint16_t getSyntheticNodeSubclassData(unsigned Opc, unsigned Order, argument
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Support/ |
| H A D | DynamicLibrary.cpp | 76 void *LibLookup(const char *Symbol, DynamicLibrary::SearchOrdering Order) { argument
91 void *Lookup(const char *Symbol, DynamicLibrary::SearchOrdering Order) { argument
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SDNodeDbgValue.h | 51 unsigned Order; member in class:llvm::SDDbgValue
147 unsigned Order; member in class:llvm::SDDbgLabel
76 SDDbgValue(DIVariable *Var, DIExpression *Expr, unsigned VRegOrFrameIdx, bool IsIndirect, DebugLoc DL, unsigned Order, enum DbgValueKind Kind) argument
[all...] |
| H A D | FastISel.cpp | 247 unsigned Order = 0; local
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelDAGToDAGHVX.cpp | 126 ArrayRef<Node> Order; member in struct:__anon4134::Coloring
375 std::vector<ElemType> Order; member in namespace:__anon4135
[all...] |
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/IR/ |
| H A D | BasicBlock.cpp | 477 unsigned Order = 0; local
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZRegisterInfo.cpp | 59 static void addHints(ArrayRef<MCPhysReg> Order, argument
76 getRegAllocationHints( Register VirtReg, ArrayRef<MCPhysReg> Order, SmallVectorImpl<MCPhysReg> &Hints, const MachineFunction &MF, const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const argument
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| /freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | Instruction.h | 52 mutable unsigned Order = 0; member in class:llvm::Instruction
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | MergeICmps.cpp | 135 unsigned Order = 1; member in class:__anon4690::BaseIdentifier
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| H A D | StructurizeCFG.cpp | 250 SmallVector<RegionNode *, 8> Order; member in class:__anon4717::StructurizeCFG
[all...] |
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMBaseRegisterInfo.cpp | 316 getRegAllocationHints( Register VirtReg, ArrayRef<MCPhysReg> Order, SmallVectorImpl<MCPhysReg> &Hints, const MachineFunction &MF, const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const argument
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| H A D | ARMLowOverheadLoops.cpp | 84 SmallVector<MachineBasicBlock*, 4> Order; member in class:__anon4030::PostOrderLoopTraversal
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| /freebsd-13-stable/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | CodeGenRegisters.h | 519 unsigned Order = 0; // Cache the sort key. member in struct:llvm::RegUnitSet
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| H A D | RegisterInfoEmitter.cpp | 1051 ArrayRef<Record*> Order = RC.getOrder(); local
1234 ArrayRef<Record*> Order = RC.getOrder(); local
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/BinaryFormat/ |
| H A D | Dwarf.cpp | 419 StringRef llvm::dwarf::ArrayOrderString(unsigned Order) { argument
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| /freebsd-13-stable/sys/contrib/dev/acpica/include/ |
| H A D | acbuffer.h | 252 UINT8 Order; member in struct:acpi_pld_info
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| /freebsd-13-stable/contrib/llvm-project/clang/lib/CodeGen/ |
| H A D | CGAtomic.cpp | 514 EmitAtomicOp(CodeGenFunction &CGF, AtomicExpr *E, Address Dest, Address Ptr, Address Val1, Address Val2, llvm::Value *IsWeak, llvm::Value *FailureOrder, uint64_t Size, llvm::AtomicOrdering Order, llvm::SyncScope::ID Scope) argument
700 EmitAtomicOp(CodeGenFunction &CGF, AtomicExpr *Expr, Address Dest, Address Ptr, Address Val1, Address Val2, llvm::Value *IsWeak, llvm::Value *FailureOrder, uint64_t Size, llvm::AtomicOrdering Order, llvm::Value *Scope) argument
816 llvm::Value *Order = EmitScalarExpr(E->getOrder()); local
[all...] |
| H A D | CGOpenMPRuntime.h | 507 explicit OffloadEntryInfo(OffloadingEntryInfoKinds Kind, unsigned Order, argument
535 unsigned Order = ~0u; variable
568 explicit OffloadEntryInfoTargetRegion(unsigned Order, argument
628 OffloadEntryInfoDeviceGlobalVar(unsigned Order, OMPTargetGlobalVarEntryKind Flags) argument
631 OffloadEntryInfoDeviceGlobalVar( unsigned Order, llvm::Constant *Addr, CharUnits VarSize, OMPTargetGlobalVarEntryKind Flags, llvm::GlobalValue::LinkageTypes Linkage) argument
[all...] |