/macosx-10.10/llvmCore-3425.0.34/lib/MC/ |
H A D | MCAsmStreamer.cpp | 777 EmitValueToOffset(const MCExpr *Offset, unsigned char Value) argument 909 EmitCFIDefCfa(int64_t Register, int64_t Offset) argument 917 OS << ", " << Offset; local 921 EmitCFIDefCfaOffset(int64_t Offset) argument 942 EmitCFIOffset(int64_t Register, int64_t Offset) argument 950 OS << ", " << Offset; local 1006 EmitCFIRelOffset(int64_t Register, int64_t Offset) argument 1014 OS << ", " << Offset; local 1115 EmitWin64EHSetFrame(unsigned Register, unsigned Offset) argument 1118 OS << "\\t.seh_setframe " << Register << ", " << Offset; local 1129 EmitWin64EHSaveReg(unsigned Register, unsigned Offset) argument 1132 OS << "\\t.seh_savereg " << Register << ", " << Offset; local 1136 EmitWin64EHSaveXMM(unsigned Register, unsigned Offset) argument 1139 OS << "\\t.seh_savexmm " << Register << ", " << Offset; local [all...] |
H A D | MCDwarf.cpp | 970 int Offset = Dst.getOffset(); local [all...] |
/macosx-10.10/llvmCore-3425.0.34/lib/Target/ARM/ |
H A D | ARMAsmPrinter.cpp | 1190 int64_t Offset = 0; local
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H A D | ARMConstantIslandPass.cpp | 97 unsigned Offset; member in struct:__anon10390::ARMConstantIslands::BasicBlockInfo 831 unsigned Offset = BBInfo[MBB->getNumber()].Offset; local 1076 unsigned Offset = BBInfo[i - 1].postOffset(LogAlign); local [all...] |
H A D | ARMFastISel.cpp | 66 int Offset; member in struct:__anon10393::Address 963 int Offset = Addr.Offset; local [all...] |
H A D | ARMISelDAGToDAG.cpp | 114 bool SelectAddrMode2Base(SDValue N, SDValue &Base, SDValue &Offset, argument 119 bool SelectAddrMode2ShOp(SDValue N, SDValue &Base, SDValue &Offset, argument 124 bool SelectAddrMode2(SDValue N, SDValue &Base, SDValue &Offset, argument 488 SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc) argument 585 SelectAddrMode2Worker(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc) argument 721 SelectAddrMode2OffsetReg(SDNode *Op, SDValue N, SDValue &Offset, SDValue &Opc) argument 757 SelectAddrMode2OffsetImmPre(SDNode *Op, SDValue N, SDValue &Offset, SDValue &Opc) argument 777 SelectAddrMode2OffsetImm(SDNode *Op, SDValue N, SDValue &Offset, SDValue &Opc) argument 802 SelectAddrMode3(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc) argument 850 SelectAddrMode3Offset(SDNode *Op, SDValue N, SDValue &Offset, SDValue &Opc) argument 870 SelectAddrMode5(SDValue N, SDValue &Base, SDValue &Offset) argument 936 SelectAddrMode6Offset(SDNode *Op, SDValue N, SDValue &Offset) argument 950 SelectAddrModePC(SDValue N, SDValue &Offset, SDValue &Label) argument 968 SelectThumbAddrModeRR(SDValue N, SDValue &Base, SDValue &Offset) argument 985 SelectThumbAddrModeRI(SDValue N, SDValue &Base, SDValue &Offset, unsigned Scale) argument 1020 SelectThumbAddrModeRI5S1(SDValue N, SDValue &Base, SDValue &Offset) argument 1027 SelectThumbAddrModeRI5S2(SDValue N, SDValue &Base, SDValue &Offset) argument 1034 SelectThumbAddrModeRI5S4(SDValue N, SDValue &Base, SDValue &Offset) argument 1333 SDValue Offset, AMOpc; local 1407 SDValue Offset; local [all...] |
H A D | ARMLoadStoreOptimizer.cpp | 80 int Offset; member in struct:__anon10400::ARMLoadStoreOpt::MemOpQueueEntry 282 MergeOps(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, int Offset, unsigned Base, bool BaseKill, int Opcode, ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch, DebugLoc dl, ArrayRef<std::pair<unsigned, bool> > Regs, ArrayRef<unsigned> ImpDefs) argument 365 MergeOpsUpdate(MachineBasicBlock &MBB, MemOpQueue &memOps, unsigned memOpsBegin, unsigned memOpsEnd, unsigned insertAfter, int Offset, unsigned Base, bool BaseKill, int Opcode, ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch, DebugLoc dl, SmallVector<MachineBasicBlock::iterator, 4> &Merges) argument 452 int Offset = MemOps[SIndex].Offset; local 940 int Offset = AddSub == ARM_AM::sub ? -Bytes : Bytes; local 945 int Offset = ARM_AM::getAM2Opc(AddSub, Bytes, ARM_AM::no_shift); local 951 int Offset = AddSub == ARM_AM::sub ? -Bytes : Bytes; local 963 int Offset = ARM_AM::getAM2Opc(AddSub, Bytes, ARM_AM::no_shift); local 969 int Offset = AddSub == ARM_AM::sub ? -Bytes : Bytes; local 1060 int Offset = isAM3 ? ARM_AM::getAM3Offset(OffField) local 1072 InsertLDR_STR(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, int Offset, bool isDef, DebugLoc dl, unsigned NewOpc, unsigned Reg, bool RegDeadKill, bool RegUndef, unsigned BaseReg, bool BaseKill, bool BaseUndef, bool OffKill, bool OffUndef, ARMCC::CondCodes Pred, unsigned PredReg, const TargetInstrInfo *TII, bool isT2) argument 1251 int Offset = getMemoryOpOffset(MBBI); local 1560 CanFormLdStDWord(MachineInstr *Op0, MachineInstr *Op1, DebugLoc &dl, unsigned &NewOpc, unsigned &EvenReg, unsigned &OddReg, unsigned &BaseReg, int &Offset, unsigned &PredReg, ARMCC::CondCodes &Pred, bool &isT2) argument 1681 int Offset = getMemoryOpOffset(Op); local 1729 int Offset = 0; local 1829 int Offset = getMemoryOpOffset(MI); local [all...] |
H A D | ARMBaseInstrInfo.cpp | 157 const MachineOperand &Offset = MI->getOperand(NumOps-3); local 1170 emitFrameIndexDebugValue(MachineFunction &MF, int FrameIx, uint64_t Offset, const MDNode *MDPtr, DebugLoc DL) const argument [all...] |
/macosx-10.10/llvmCore-3425.0.34/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 129 unsigned Offset = State.AllocateStack(ArgFlags.getByValSize(), 4); local 172 unsigned Offset = State.AllocateStack(4, 4); local 197 unsigned Offset = State.AllocateStack(8, 8, Hexagon::D2); local 244 unsigned Offset = State.AllocateStack(4, 4); local 259 unsigned Offset = State.AllocateStack(8, 8); local 591 getIndexedAddressParts(SDNode *Ptr, EVT VT, bool isSEXTLoad, SDValue &Base, SDValue &Offset, bool &isInc, SelectionDAG &DAG) argument 629 getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const argument 967 SDValue Offset = DAG.getConstant(4, MVT::i32); local 1015 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); local [all...] |
/macosx-10.10/llvmCore-3425.0.34/lib/Target/NVPTX/ |
H A D | NVPTXAsmPrinter.cpp | 122 int64_t Offset = TD.getIndexedOffset(PtrVal->getType(), IdxVec); local
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/macosx-10.10/llvmCore-3425.0.34/lib/Target/XCore/ |
H A D | XCoreISelLowering.cpp | 419 int64_t Offset; local 353 IsWordAlignedBasePlusConstantOffset(SDValue Addr, SDValue &AlignedBase, int64_t &Offset) argument 966 int Offset = VA.getLocMemOffset(); local [all...] |
/macosx-10.10/llvmCore-3425.0.34/lib/Transforms/InstCombine/ |
H A D | InstCombineCasts.cpp | 26 DecomposeSimpleLinearExpr(Value *Val, unsigned &Scale, uint64_t &Offset) argument 1340 int64_t Offset = TD->getIndexedOffset(GEP->getPointerOperandType(), Ops); local [all...] |
H A D | InstCombineCompares.cpp | 486 int64_t Offset = 0; local 593 Value *Offset local [all...] |
H A D | InstructionCombining.cpp | 741 Type *InstCombiner::FindElementAtOffset(Type *Ty, int64_t Offset, argument 1063 int64_t Offset = TD->getIndexedOffset(GEP.getPointerOperandType(), Ops); local [all...] |
/macosx-10.10/llvmCore-3425.0.34/lib/Transforms/Scalar/ |
H A D | ScalarReplAggregates.cpp | 397 MergeInTypeForLoadOrStore(Type *In, uint64_t Offset) argument 441 MergeInVectorType(VectorType *VInTy, uint64_t Offset) argument 467 CanConvertToScalar(Value *V, uint64_t Offset, Value* NonConstantIdx) argument 596 ConvertUsesToScalar(Value *Ptr, AllocaInst *NewAI, uint64_t Offset, Value* NonConstantIdx) argument 762 ConvertScalar_ExtractValue(Value *FromVal, Type *ToType, uint64_t Offset, Value* NonConstantIdx, IRBuilder<> &Builder) argument 896 ConvertScalar_InsertValue(Value *SV, Value *Old, uint64_t Offset, Value* NonConstantIdx, IRBuilder<> &Builder) argument 1599 isSafeForScalarRepl(Instruction *I, uint64_t Offset, AllocaInfo &Info) argument 1661 isSafePHISelectUseForScalarRepl(Instruction *I, uint64_t Offset, AllocaInfo &Info) argument 1711 isSafeGEP(GetElementPtrInst *GEPI, uint64_t &Offset, AllocaInfo &Info) argument 1792 isSafeMemAccess(uint64_t Offset, uint64_t MemSize, Type *MemOpType, bool isStore, AllocaInfo &Info, Instruction *TheAccess, bool AllowWholeAccess) argument 1831 TypeHasComponent(Type *T, uint64_t Offset, uint64_t Size) argument 1867 RewriteForScalarRepl(Instruction *I, AllocaInst *AI, uint64_t Offset, SmallVector<AllocaInst*, 32> &NewElts) argument 1981 RewriteBitCast(BitCastInst *BC, AllocaInst *AI, uint64_t Offset, SmallVector<AllocaInst*, 32> &NewElts) argument 2009 FindElementAndOffset(Type *&T, uint64_t &Offset, Type *&IdxTy) argument 2039 RewriteGEP(GetElementPtrInst *GEPI, AllocaInst *AI, uint64_t Offset, SmallVector<AllocaInst*, 32> &NewElts) argument 2100 RewriteLifetimeIntrinsic(IntrinsicInst *II, AllocaInst *AI, uint64_t Offset, SmallVector<AllocaInst*, 32> &NewElts) argument [all...] |
H A D | SimplifyLibCalls.cpp | 761 std::string::size_type Offset = SearchStr.find(ToFindStr); local
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H A D | GVN.cpp | 986 int Offset = AnalyzeLoadFromClobberingWrite(LoadTy, LoadPtr, local 1010 static Value *GetStoreValueForLoad(Value *SrcVal, unsigned Offset, argument 1048 static Value *GetLoadValueForLoad(LoadInst *SrcVal, unsigned Offset, argument 1108 GetMemInstValueForLoad(MemIntrinsic *SrcInst, unsigned Offset, Type *LoadTy, Instruction *InsertPt, const TargetData &TD) argument 1176 unsigned Offset; member in struct:__anon10646::AvailableValueInBlock 1387 int Offset = AnalyzeLoadFromClobberingStore(LI->getType(), Address, local 1406 int Offset = AnalyzeLoadFromClobberingLoad(LI->getType(), local 1422 int Offset = AnalyzeLoadFromClobberingMemInst(LI->getType(), Address, local 1819 int Offset = AnalyzeLoadFromClobberingStore(L->getType(), local 1837 int Offset = AnalyzeLoadFromClobberingLoad(L->getType(), local 1847 int Offset = AnalyzeLoadFromClobberingMemInst(L->getType(), local [all...] |
/macosx-10.10/llvmCore-3425.0.34/lib/Transforms/Vectorize/ |
H A D | BBVectorize.cpp | 480 int64_t Offset = IntOff->getSExtValue(); local
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/macosx-10.10/tcl-105/tcl_ext/mk4tcl/metakit/src/ |
H A D | persist.cpp | 67 t4_i32 c4_FileMark::Offset()const { function in class:c4_FileMark
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/macosx-10.10/llvmCore-3425.0.34/include/llvm/CodeGen/ |
H A D | SelectionDAGNodes.h | 1226 int64_t Offset; member in class:llvm::SDNode::GlobalAddressSDNode 1291 int Offset; // It's a MachineConstantPoolValue if top bit is set. member in class:llvm::SDNode::ConstantPoolSDNode 1351 int64_t Offset; member in class:llvm::SDNode::TargetIndexSDNode 1486 int64_t Offset; member in class:llvm::SDNode::BlockAddressSDNode [all...] |
/macosx-10.10/llvmCore-3425.0.34/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeIntegerTypes.cpp | 2829 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet, local
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H A D | LegalizeVectorTypes.cpp | 789 SDValue Offset = DAG.getUNDEF(Ptr.getValueType()); local 2416 unsigned Offset = 0; local 2540 unsigned i = 0, Offset = Increment; local 2581 unsigned Offset = 0; // offset from base to store local 2660 unsigned Offset = Increment; local [all...] |
/macosx-10.10/llvmCore-3425.0.34/lib/Target/CellSPU/ |
H A D | SPUISelLowering.cpp | 2175 int64_t Offset=0; local
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/macosx-10.10/llvmCore-3425.0.34/lib/Target/X86/ |
H A D | X86ISelDAGToDAG.cpp | 578 bool X86DAGToDAGISel::FoldOffsetIntoAddress(uint64_t Offset, argument
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H A D | X86InstrInfo.cpp | 3531 emitFrameIndexDebugValue(MachineFunction &MF, int FrameIx, uint64_t Offset, const MDNode *MDPtr, DebugLoc DL) const argument
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