1//===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains a printer that converts from our internal representation 11// of machine-dependent LLVM code to GAS-format ARM assembly language. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "asm-printer" 16#include "ARMAsmPrinter.h" 17#include "ARM.h" 18#include "ARMBuildAttrs.h" 19#include "ARMConstantPoolValue.h" 20#include "ARMMachineFunctionInfo.h" 21#include "ARMTargetMachine.h" 22#include "ARMTargetObjectFile.h" 23#include "InstPrinter/ARMInstPrinter.h" 24#include "MCTargetDesc/ARMAddressingModes.h" 25#include "MCTargetDesc/ARMMCExpr.h" 26#include "llvm/ADT/SetVector.h" 27#include "llvm/ADT/SmallString.h" 28#include "llvm/Constants.h" 29#include "llvm/DebugInfo.h" 30#include "llvm/Module.h" 31#include "llvm/Type.h" 32#include "llvm/Assembly/Writer.h" 33#include "llvm/CodeGen/MachineModuleInfoImpls.h" 34#include "llvm/CodeGen/MachineFunctionPass.h" 35#include "llvm/CodeGen/MachineJumpTableInfo.h" 36#include "llvm/MC/MCAsmInfo.h" 37#include "llvm/MC/MCAssembler.h" 38#include "llvm/MC/MCContext.h" 39#include "llvm/MC/MCInst.h" 40#include "llvm/MC/MCSectionMachO.h" 41#include "llvm/MC/MCObjectStreamer.h" 42#include "llvm/MC/MCStreamer.h" 43#include "llvm/MC/MCSymbol.h" 44#include "llvm/Target/Mangler.h" 45#include "llvm/Target/TargetData.h" 46#include "llvm/Target/TargetMachine.h" 47#include "llvm/Support/CommandLine.h" 48#include "llvm/Support/Debug.h" 49#include "llvm/Support/ErrorHandling.h" 50#include "llvm/Support/TargetRegistry.h" 51#include "llvm/Support/raw_ostream.h" 52#include <cctype> 53using namespace llvm; 54 55namespace { 56 57 // Per section and per symbol attributes are not supported. 58 // To implement them we would need the ability to delay this emission 59 // until the assembly file is fully parsed/generated as only then do we 60 // know the symbol and section numbers. 61 class AttributeEmitter { 62 public: 63 virtual void MaybeSwitchVendor(StringRef Vendor) = 0; 64 virtual void EmitAttribute(unsigned Attribute, unsigned Value) = 0; 65 virtual void EmitTextAttribute(unsigned Attribute, StringRef String) = 0; 66 virtual void Finish() = 0; 67 virtual ~AttributeEmitter() {} 68 }; 69 70 class AsmAttributeEmitter : public AttributeEmitter { 71 MCStreamer &Streamer; 72 73 public: 74 AsmAttributeEmitter(MCStreamer &Streamer_) : Streamer(Streamer_) {} 75 void MaybeSwitchVendor(StringRef Vendor) { } 76 77 void EmitAttribute(unsigned Attribute, unsigned Value) { 78 Streamer.EmitRawText("\t.eabi_attribute " + 79 Twine(Attribute) + ", " + Twine(Value)); 80 } 81 82 void EmitTextAttribute(unsigned Attribute, StringRef String) { 83 switch (Attribute) { 84 default: llvm_unreachable("Unsupported Text attribute in ASM Mode"); 85 case ARMBuildAttrs::CPU_name: 86 Streamer.EmitRawText(StringRef("\t.cpu ") + String.lower()); 87 break; 88 /* GAS requires .fpu to be emitted regardless of EABI attribute */ 89 case ARMBuildAttrs::Advanced_SIMD_arch: 90 case ARMBuildAttrs::VFP_arch: 91 Streamer.EmitRawText(StringRef("\t.fpu ") + String.lower()); 92 break; 93 } 94 } 95 void Finish() { } 96 }; 97 98 class ObjectAttributeEmitter : public AttributeEmitter { 99 // This structure holds all attributes, accounting for 100 // their string/numeric value, so we can later emmit them 101 // in declaration order, keeping all in the same vector 102 struct AttributeItemType { 103 enum { 104 HiddenAttribute = 0, 105 NumericAttribute, 106 TextAttribute 107 } Type; 108 unsigned Tag; 109 unsigned IntValue; 110 StringRef StringValue; 111 } AttributeItem; 112 113 MCObjectStreamer &Streamer; 114 StringRef CurrentVendor; 115 SmallVector<AttributeItemType, 64> Contents; 116 117 // Account for the ULEB/String size of each item, 118 // not just the number of items 119 size_t ContentsSize; 120 // FIXME: this should be in a more generic place, but 121 // getULEBSize() is in MCAsmInfo and will be moved to MCDwarf 122 size_t getULEBSize(int Value) { 123 size_t Size = 0; 124 do { 125 Value >>= 7; 126 Size += sizeof(int8_t); // Is this really necessary? 127 } while (Value); 128 return Size; 129 } 130 131 public: 132 ObjectAttributeEmitter(MCObjectStreamer &Streamer_) : 133 Streamer(Streamer_), CurrentVendor(""), ContentsSize(0) { } 134 135 void MaybeSwitchVendor(StringRef Vendor) { 136 assert(!Vendor.empty() && "Vendor cannot be empty."); 137 138 if (CurrentVendor.empty()) 139 CurrentVendor = Vendor; 140 else if (CurrentVendor == Vendor) 141 return; 142 else 143 Finish(); 144 145 CurrentVendor = Vendor; 146 147 assert(Contents.size() == 0); 148 } 149 150 void EmitAttribute(unsigned Attribute, unsigned Value) { 151 AttributeItemType attr = { 152 AttributeItemType::NumericAttribute, 153 Attribute, 154 Value, 155 StringRef("") 156 }; 157 ContentsSize += getULEBSize(Attribute); 158 ContentsSize += getULEBSize(Value); 159 Contents.push_back(attr); 160 } 161 162 void EmitTextAttribute(unsigned Attribute, StringRef String) { 163 AttributeItemType attr = { 164 AttributeItemType::TextAttribute, 165 Attribute, 166 0, 167 String 168 }; 169 ContentsSize += getULEBSize(Attribute); 170 // String + \0 171 ContentsSize += String.size()+1; 172 173 Contents.push_back(attr); 174 } 175 176 void Finish() { 177 // Vendor size + Vendor name + '\0' 178 const size_t VendorHeaderSize = 4 + CurrentVendor.size() + 1; 179 180 // Tag + Tag Size 181 const size_t TagHeaderSize = 1 + 4; 182 183 Streamer.EmitIntValue(VendorHeaderSize + TagHeaderSize + ContentsSize, 4); 184 Streamer.EmitBytes(CurrentVendor, 0); 185 Streamer.EmitIntValue(0, 1); // '\0' 186 187 Streamer.EmitIntValue(ARMBuildAttrs::File, 1); 188 Streamer.EmitIntValue(TagHeaderSize + ContentsSize, 4); 189 190 // Size should have been accounted for already, now 191 // emit each field as its type (ULEB or String) 192 for (unsigned int i=0; i<Contents.size(); ++i) { 193 AttributeItemType item = Contents[i]; 194 Streamer.EmitULEB128IntValue(item.Tag, 0); 195 switch (item.Type) { 196 default: llvm_unreachable("Invalid attribute type"); 197 case AttributeItemType::NumericAttribute: 198 Streamer.EmitULEB128IntValue(item.IntValue, 0); 199 break; 200 case AttributeItemType::TextAttribute: 201 Streamer.EmitBytes(item.StringValue.upper(), 0); 202 Streamer.EmitIntValue(0, 1); // '\0' 203 break; 204 } 205 } 206 207 Contents.clear(); 208 } 209 }; 210 211} // end of anonymous namespace 212 213MachineLocation ARMAsmPrinter:: 214getDebugValueLocation(const MachineInstr *MI) const { 215 MachineLocation Location; 216 assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands!"); 217 // Frame address. Currently handles register +- offset only. 218 if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm()) 219 Location.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm()); 220 else { 221 DEBUG(dbgs() << "DBG_VALUE instruction ignored! " << *MI << "\n"); 222 } 223 return Location; 224} 225 226/// EmitDwarfRegOp - Emit dwarf register operation. 227void ARMAsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc) const { 228 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 229 if (RI->getDwarfRegNum(MLoc.getReg(), false) != -1) 230 AsmPrinter::EmitDwarfRegOp(MLoc); 231 else { 232 unsigned Reg = MLoc.getReg(); 233 if (Reg >= ARM::S0 && Reg <= ARM::S31) { 234 assert(ARM::S0 + 31 == ARM::S31 && "Unexpected ARM S register numbering"); 235 // S registers are described as bit-pieces of a register 236 // S[2x] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 0) 237 // S[2x+1] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 32) 238 239 unsigned SReg = Reg - ARM::S0; 240 bool odd = SReg & 0x1; 241 unsigned Rx = 256 + (SReg >> 1); 242 243 OutStreamer.AddComment("DW_OP_regx for S register"); 244 EmitInt8(dwarf::DW_OP_regx); 245 246 OutStreamer.AddComment(Twine(SReg)); 247 EmitULEB128(Rx); 248 249 if (odd) { 250 OutStreamer.AddComment("DW_OP_bit_piece 32 32"); 251 EmitInt8(dwarf::DW_OP_bit_piece); 252 EmitULEB128(32); 253 EmitULEB128(32); 254 } else { 255 OutStreamer.AddComment("DW_OP_bit_piece 32 0"); 256 EmitInt8(dwarf::DW_OP_bit_piece); 257 EmitULEB128(32); 258 EmitULEB128(0); 259 } 260 } else if (Reg >= ARM::Q0 && Reg <= ARM::Q15) { 261 assert(ARM::Q0 + 15 == ARM::Q15 && "Unexpected ARM Q register numbering"); 262 // Q registers Q0-Q15 are described by composing two D registers together. 263 // Qx = DW_OP_regx(256+2x) DW_OP_piece(8) DW_OP_regx(256+2x+1) 264 // DW_OP_piece(8) 265 266 unsigned QReg = Reg - ARM::Q0; 267 unsigned D1 = 256 + 2 * QReg; 268 unsigned D2 = D1 + 1; 269 270 OutStreamer.AddComment("DW_OP_regx for Q register: D1"); 271 EmitInt8(dwarf::DW_OP_regx); 272 EmitULEB128(D1); 273 OutStreamer.AddComment("DW_OP_piece 8"); 274 EmitInt8(dwarf::DW_OP_piece); 275 EmitULEB128(8); 276 277 OutStreamer.AddComment("DW_OP_regx for Q register: D2"); 278 EmitInt8(dwarf::DW_OP_regx); 279 EmitULEB128(D2); 280 OutStreamer.AddComment("DW_OP_piece 8"); 281 EmitInt8(dwarf::DW_OP_piece); 282 EmitULEB128(8); 283 } 284 } 285} 286 287void ARMAsmPrinter::EmitFunctionBodyEnd() { 288 // Make sure to terminate any constant pools that were at the end 289 // of the function. 290 if (!InConstantPool) 291 return; 292 InConstantPool = false; 293 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd); 294} 295 296void ARMAsmPrinter::EmitFunctionEntryLabel() { 297 if (AFI->isThumbFunction()) { 298 OutStreamer.EmitAssemblerFlag(MCAF_Code16); 299 OutStreamer.EmitThumbFunc(CurrentFnSym); 300 } 301 302 OutStreamer.EmitLabel(CurrentFnSym); 303} 304 305void ARMAsmPrinter::EmitXXStructor(const Constant *CV) { 306 uint64_t Size = TM.getTargetData()->getTypeAllocSize(CV->getType()); 307 assert(Size && "C++ constructor pointer had zero size!"); 308 309 const GlobalValue *GV = dyn_cast<GlobalValue>(CV->stripPointerCasts()); 310 assert(GV && "C++ constructor pointer was not a GlobalValue!"); 311 312 const MCExpr *E = MCSymbolRefExpr::Create(Mang->getSymbol(GV), 313 (Subtarget->isTargetDarwin() 314 ? MCSymbolRefExpr::VK_None 315 : MCSymbolRefExpr::VK_ARM_TARGET1), 316 OutContext); 317 318 OutStreamer.EmitValue(E, Size); 319} 320 321/// runOnMachineFunction - This uses the EmitInstruction() 322/// method to print assembly for each instruction. 323/// 324bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) { 325 AFI = MF.getInfo<ARMFunctionInfo>(); 326 MCP = MF.getConstantPool(); 327 328 return AsmPrinter::runOnMachineFunction(MF); 329} 330 331void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum, 332 raw_ostream &O, const char *Modifier) { 333 const MachineOperand &MO = MI->getOperand(OpNum); 334 unsigned TF = MO.getTargetFlags(); 335 336 switch (MO.getType()) { 337 default: llvm_unreachable("<unknown operand type>"); 338 case MachineOperand::MO_Register: { 339 unsigned Reg = MO.getReg(); 340 assert(TargetRegisterInfo::isPhysicalRegister(Reg)); 341 assert(!MO.getSubReg() && "Subregs should be eliminated!"); 342 O << ARMInstPrinter::getRegisterName(Reg); 343 break; 344 } 345 case MachineOperand::MO_Immediate: { 346 int64_t Imm = MO.getImm(); 347 O << '#'; 348 if ((Modifier && strcmp(Modifier, "lo16") == 0) || 349 (TF == ARMII::MO_LO16)) 350 O << ":lower16:"; 351 else if ((Modifier && strcmp(Modifier, "hi16") == 0) || 352 (TF == ARMII::MO_HI16)) 353 O << ":upper16:"; 354 O << Imm; 355 break; 356 } 357 case MachineOperand::MO_MachineBasicBlock: 358 O << *MO.getMBB()->getSymbol(); 359 return; 360 case MachineOperand::MO_GlobalAddress: { 361 const GlobalValue *GV = MO.getGlobal(); 362 if ((Modifier && strcmp(Modifier, "lo16") == 0) || 363 (TF & ARMII::MO_LO16)) 364 O << ":lower16:"; 365 else if ((Modifier && strcmp(Modifier, "hi16") == 0) || 366 (TF & ARMII::MO_HI16)) 367 O << ":upper16:"; 368 O << *Mang->getSymbol(GV); 369 370 printOffset(MO.getOffset(), O); 371 if (TF == ARMII::MO_PLT) 372 O << "(PLT)"; 373 break; 374 } 375 case MachineOperand::MO_ExternalSymbol: { 376 O << *GetExternalSymbolSymbol(MO.getSymbolName()); 377 if (TF == ARMII::MO_PLT) 378 O << "(PLT)"; 379 break; 380 } 381 case MachineOperand::MO_ConstantPoolIndex: 382 O << *GetCPISymbol(MO.getIndex()); 383 break; 384 case MachineOperand::MO_JumpTableIndex: 385 O << *GetJTISymbol(MO.getIndex()); 386 break; 387 } 388} 389 390//===--------------------------------------------------------------------===// 391 392MCSymbol *ARMAsmPrinter:: 393GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2, 394 const MachineBasicBlock *MBB) const { 395 SmallString<60> Name; 396 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() 397 << getFunctionNumber() << '_' << uid << '_' << uid2 398 << "_set_" << MBB->getNumber(); 399 return OutContext.GetOrCreateSymbol(Name.str()); 400} 401 402MCSymbol *ARMAsmPrinter:: 403GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const { 404 SmallString<60> Name; 405 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI" 406 << getFunctionNumber() << '_' << uid << '_' << uid2; 407 return OutContext.GetOrCreateSymbol(Name.str()); 408} 409 410 411MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel(void) const { 412 SmallString<60> Name; 413 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "SJLJEH" 414 << getFunctionNumber(); 415 return OutContext.GetOrCreateSymbol(Name.str()); 416} 417 418bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, 419 unsigned AsmVariant, const char *ExtraCode, 420 raw_ostream &O) { 421 // Does this asm operand have a single letter operand modifier? 422 if (ExtraCode && ExtraCode[0]) { 423 if (ExtraCode[1] != 0) return true; // Unknown modifier. 424 425 switch (ExtraCode[0]) { 426 default: 427 // See if this is a generic print operand 428 return AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O); 429 case 'a': // Print as a memory address. 430 if (MI->getOperand(OpNum).isReg()) { 431 O << "[" 432 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg()) 433 << "]"; 434 return false; 435 } 436 // Fallthrough 437 case 'c': // Don't print "#" before an immediate operand. 438 if (!MI->getOperand(OpNum).isImm()) 439 return true; 440 O << MI->getOperand(OpNum).getImm(); 441 return false; 442 case 'P': // Print a VFP double precision register. 443 case 'q': // Print a NEON quad precision register. 444 printOperand(MI, OpNum, O); 445 return false; 446 case 'y': // Print a VFP single precision register as indexed double. 447 if (MI->getOperand(OpNum).isReg()) { 448 unsigned Reg = MI->getOperand(OpNum).getReg(); 449 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo(); 450 // Find the 'd' register that has this 's' register as a sub-register, 451 // and determine the lane number. 452 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) { 453 if (!ARM::DPRRegClass.contains(*SR)) 454 continue; 455 bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg; 456 O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]"); 457 return false; 458 } 459 } 460 return true; 461 case 'B': // Bitwise inverse of integer or symbol without a preceding #. 462 if (!MI->getOperand(OpNum).isImm()) 463 return true; 464 O << ~(MI->getOperand(OpNum).getImm()); 465 return false; 466 case 'L': // The low 16 bits of an immediate constant. 467 if (!MI->getOperand(OpNum).isImm()) 468 return true; 469 O << (MI->getOperand(OpNum).getImm() & 0xffff); 470 return false; 471 case 'M': { // A register range suitable for LDM/STM. 472 if (!MI->getOperand(OpNum).isReg()) 473 return true; 474 const MachineOperand &MO = MI->getOperand(OpNum); 475 unsigned RegBegin = MO.getReg(); 476 // This takes advantage of the 2 operand-ness of ldm/stm and that we've 477 // already got the operands in registers that are operands to the 478 // inline asm statement. 479 480 O << "{" << ARMInstPrinter::getRegisterName(RegBegin); 481 482 // FIXME: The register allocator not only may not have given us the 483 // registers in sequence, but may not be in ascending registers. This 484 // will require changes in the register allocator that'll need to be 485 // propagated down here if the operands change. 486 unsigned RegOps = OpNum + 1; 487 while (MI->getOperand(RegOps).isReg()) { 488 O << ", " 489 << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg()); 490 RegOps++; 491 } 492 493 O << "}"; 494 495 return false; 496 } 497 case 'R': // The most significant register of a pair. 498 case 'Q': { // The least significant register of a pair. 499 if (OpNum == 0) 500 return true; 501 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1); 502 if (!FlagsOP.isImm()) 503 return true; 504 unsigned Flags = FlagsOP.getImm(); 505 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags); 506 if (NumVals != 2) 507 return true; 508 unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1; 509 if (RegOp >= MI->getNumOperands()) 510 return true; 511 const MachineOperand &MO = MI->getOperand(RegOp); 512 if (!MO.isReg()) 513 return true; 514 unsigned Reg = MO.getReg(); 515 O << ARMInstPrinter::getRegisterName(Reg); 516 return false; 517 } 518 519 case 'e': // The low doubleword register of a NEON quad register. 520 case 'f': { // The high doubleword register of a NEON quad register. 521 if (!MI->getOperand(OpNum).isReg()) 522 return true; 523 unsigned Reg = MI->getOperand(OpNum).getReg(); 524 if (!ARM::QPRRegClass.contains(Reg)) 525 return true; 526 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo(); 527 unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ? 528 ARM::dsub_0 : ARM::dsub_1); 529 O << ARMInstPrinter::getRegisterName(SubReg); 530 return false; 531 } 532 533 // This modifier is not yet supported. 534 case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1. 535 return true; 536 case 'H': { // The highest-numbered register of a pair. 537 const MachineOperand &MO = MI->getOperand(OpNum); 538 if (!MO.isReg()) 539 return true; 540 const TargetRegisterClass &RC = ARM::GPRRegClass; 541 const MachineFunction &MF = *MI->getParent()->getParent(); 542 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo(); 543 544 unsigned RegIdx = TRI->getEncodingValue(MO.getReg()); 545 RegIdx |= 1; //The odd register is also the higher-numbered one of a pair. 546 547 unsigned Reg = RC.getRegister(RegIdx); 548 O << ARMInstPrinter::getRegisterName(Reg); 549 return false; 550 } 551 } 552 } 553 554 printOperand(MI, OpNum, O); 555 return false; 556} 557 558bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, 559 unsigned OpNum, unsigned AsmVariant, 560 const char *ExtraCode, 561 raw_ostream &O) { 562 // Does this asm operand have a single letter operand modifier? 563 if (ExtraCode && ExtraCode[0]) { 564 if (ExtraCode[1] != 0) return true; // Unknown modifier. 565 566 switch (ExtraCode[0]) { 567 case 'A': // A memory operand for a VLD1/VST1 instruction. 568 default: return true; // Unknown modifier. 569 case 'm': // The base register of a memory operand. 570 if (!MI->getOperand(OpNum).isReg()) 571 return true; 572 O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg()); 573 return false; 574 } 575 } 576 577 const MachineOperand &MO = MI->getOperand(OpNum); 578 assert(MO.isReg() && "unexpected inline asm memory operand"); 579 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]"; 580 return false; 581} 582 583void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) { 584 if (Subtarget->isTargetDarwin()) { 585 Reloc::Model RelocM = TM.getRelocationModel(); 586 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) { 587 // Declare all the text sections up front (before the DWARF sections 588 // emitted by AsmPrinter::doInitialization) so the assembler will keep 589 // them together at the beginning of the object file. This helps 590 // avoid out-of-range branches that are due a fundamental limitation of 591 // the way symbol offsets are encoded with the current Darwin ARM 592 // relocations. 593 const TargetLoweringObjectFileMachO &TLOFMacho = 594 static_cast<const TargetLoweringObjectFileMachO &>( 595 getObjFileLowering()); 596 597 // Collect the set of sections our functions will go into. 598 SetVector<const MCSection *, SmallVector<const MCSection *, 8>, 599 SmallPtrSet<const MCSection *, 8> > TextSections; 600 // Default text section comes first. 601 TextSections.insert(TLOFMacho.getTextSection()); 602 // Now any user defined text sections from function attributes. 603 for (Module::iterator F = M.begin(), e = M.end(); F != e; ++F) 604 if (!F->isDeclaration() && !F->hasAvailableExternallyLinkage()) 605 TextSections.insert(TLOFMacho.SectionForGlobal(F, Mang, TM)); 606 // Now the coalescable sections. 607 TextSections.insert(TLOFMacho.getTextCoalSection()); 608 TextSections.insert(TLOFMacho.getConstTextCoalSection()); 609 610 // Emit the sections in the .s file header to fix the order. 611 for (unsigned i = 0, e = TextSections.size(); i != e; ++i) 612 OutStreamer.SwitchSection(TextSections[i]); 613 614 if (RelocM == Reloc::DynamicNoPIC) { 615 const MCSection *sect = 616 OutContext.getMachOSection("__TEXT", "__symbol_stub4", 617 MCSectionMachO::S_SYMBOL_STUBS, 618 12, SectionKind::getText()); 619 OutStreamer.SwitchSection(sect); 620 } else { 621 const MCSection *sect = 622 OutContext.getMachOSection("__TEXT", "__picsymbolstub4", 623 MCSectionMachO::S_SYMBOL_STUBS, 624 16, SectionKind::getText()); 625 OutStreamer.SwitchSection(sect); 626 } 627 const MCSection *StaticInitSect = 628 OutContext.getMachOSection("__TEXT", "__StaticInit", 629 MCSectionMachO::S_REGULAR | 630 MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS, 631 SectionKind::getText()); 632 OutStreamer.SwitchSection(StaticInitSect); 633 } 634 } 635 636 // Use unified assembler syntax. 637 OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified); 638 639 // Emit ARM Build Attributes 640 if (Subtarget->isTargetELF()) 641 emitAttributes(); 642} 643 644 645void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) { 646 if (Subtarget->isTargetDarwin()) { 647 // All darwin targets use mach-o. 648 const TargetLoweringObjectFileMachO &TLOFMacho = 649 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering()); 650 MachineModuleInfoMachO &MMIMacho = 651 MMI->getObjFileInfo<MachineModuleInfoMachO>(); 652 653 // Output non-lazy-pointers for external and common global variables. 654 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList(); 655 656 if (!Stubs.empty()) { 657 // Switch with ".non_lazy_symbol_pointer" directive. 658 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection()); 659 EmitAlignment(2); 660 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) { 661 // L_foo$stub: 662 OutStreamer.EmitLabel(Stubs[i].first); 663 // .indirect_symbol _foo 664 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second; 665 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol); 666 667 if (MCSym.getInt()) 668 // External to current translation unit. 669 OutStreamer.EmitIntValue(0, 4/*size*/, 0/*addrspace*/); 670 else 671 // Internal to current translation unit. 672 // 673 // When we place the LSDA into the TEXT section, the type info 674 // pointers need to be indirect and pc-rel. We accomplish this by 675 // using NLPs; however, sometimes the types are local to the file. 676 // We need to fill in the value for the NLP in those cases. 677 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(), 678 OutContext), 679 4/*size*/, 0/*addrspace*/); 680 } 681 682 Stubs.clear(); 683 OutStreamer.AddBlankLine(); 684 } 685 686 Stubs = MMIMacho.GetHiddenGVStubList(); 687 if (!Stubs.empty()) { 688 OutStreamer.SwitchSection(getObjFileLowering().getDataSection()); 689 EmitAlignment(2); 690 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) { 691 // L_foo$stub: 692 OutStreamer.EmitLabel(Stubs[i].first); 693 // .long _foo 694 OutStreamer.EmitValue(MCSymbolRefExpr:: 695 Create(Stubs[i].second.getPointer(), 696 OutContext), 697 4/*size*/, 0/*addrspace*/); 698 } 699 700 Stubs.clear(); 701 OutStreamer.AddBlankLine(); 702 } 703 704 // Funny Darwin hack: This flag tells the linker that no global symbols 705 // contain code that falls through to other global symbols (e.g. the obvious 706 // implementation of multiple entry points). If this doesn't occur, the 707 // linker can safely perform dead code stripping. Since LLVM never 708 // generates code that does this, it is always safe to set. 709 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols); 710 } 711} 712 713//===----------------------------------------------------------------------===// 714// Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile() 715// FIXME: 716// The following seem like one-off assembler flags, but they actually need 717// to appear in the .ARM.attributes section in ELF. 718// Instead of subclassing the MCELFStreamer, we do the work here. 719 720void ARMAsmPrinter::emitAttributes() { 721 722 emitARMAttributeSection(); 723 724 /* GAS expect .fpu to be emitted, regardless of VFP build attribute */ 725 bool emitFPU = false; 726 AttributeEmitter *AttrEmitter; 727 if (OutStreamer.hasRawTextSupport()) { 728 AttrEmitter = new AsmAttributeEmitter(OutStreamer); 729 emitFPU = true; 730 } else { 731 MCObjectStreamer &O = static_cast<MCObjectStreamer&>(OutStreamer); 732 AttrEmitter = new ObjectAttributeEmitter(O); 733 } 734 735 AttrEmitter->MaybeSwitchVendor("aeabi"); 736 737 std::string CPUString = Subtarget->getCPUString(); 738 739 if (CPUString == "cortex-a8" || 740 Subtarget->isCortexA8()) { 741 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a8"); 742 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v7); 743 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch_profile, 744 ARMBuildAttrs::ApplicationProfile); 745 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use, 746 ARMBuildAttrs::Allowed); 747 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use, 748 ARMBuildAttrs::AllowThumb32); 749 // Fixme: figure out when this is emitted. 750 //AttrEmitter->EmitAttribute(ARMBuildAttrs::WMMX_arch, 751 // ARMBuildAttrs::AllowWMMXv1); 752 // 753 754 /// ADD additional Else-cases here! 755 } else if (CPUString == "xscale") { 756 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v5TEJ); 757 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use, 758 ARMBuildAttrs::Allowed); 759 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use, 760 ARMBuildAttrs::Allowed); 761 } else if (CPUString == "generic") { 762 // FIXME: Why these defaults? 763 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T); 764 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use, 765 ARMBuildAttrs::Allowed); 766 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use, 767 ARMBuildAttrs::Allowed); 768 } 769 770 if (Subtarget->hasNEON() && emitFPU) { 771 /* NEON is not exactly a VFP architecture, but GAS emit one of 772 * neon/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */ 773 if (Subtarget->hasVFP4()) 774 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch, 775 "neon-vfpv4"); 776 else 777 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch, "neon"); 778 /* If emitted for NEON, omit from VFP below, since you can have both 779 * NEON and VFP in build attributes but only one .fpu */ 780 emitFPU = false; 781 } 782 783 /* VFPv4 + .fpu */ 784 if (Subtarget->hasVFP4()) { 785 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch, 786 ARMBuildAttrs::AllowFPv4A); 787 if (emitFPU) 788 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv4"); 789 790 /* VFPv3 + .fpu */ 791 } else if (Subtarget->hasVFP3()) { 792 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch, 793 ARMBuildAttrs::AllowFPv3A); 794 if (emitFPU) 795 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv3"); 796 797 /* VFPv2 + .fpu */ 798 } else if (Subtarget->hasVFP2()) { 799 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch, 800 ARMBuildAttrs::AllowFPv2); 801 if (emitFPU) 802 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv2"); 803 } 804 805 /* TODO: ARMBuildAttrs::Allowed is not completely accurate, 806 * since NEON can have 1 (allowed) or 2 (MAC operations) */ 807 if (Subtarget->hasNEON()) { 808 AttrEmitter->EmitAttribute(ARMBuildAttrs::Advanced_SIMD_arch, 809 ARMBuildAttrs::Allowed); 810 } 811 812 // Signal various FP modes. 813 if (!TM.Options.UnsafeFPMath) { 814 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_denormal, 815 ARMBuildAttrs::Allowed); 816 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_exceptions, 817 ARMBuildAttrs::Allowed); 818 } 819 820 if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath) 821 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model, 822 ARMBuildAttrs::Allowed); 823 else 824 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model, 825 ARMBuildAttrs::AllowIEE754); 826 827 // FIXME: add more flags to ARMBuildAttrs.h 828 // 8-bytes alignment stuff. 829 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_needed, 1); 830 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1); 831 832 // Hard float. Use both S and D registers and conform to AAPCS-VFP. 833 if (Subtarget->isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard) { 834 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_HardFP_use, 3); 835 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_VFP_args, 1); 836 } 837 // FIXME: Should we signal R9 usage? 838 839 if (Subtarget->hasDivide()) 840 AttrEmitter->EmitAttribute(ARMBuildAttrs::DIV_use, 1); 841 842 AttrEmitter->Finish(); 843 delete AttrEmitter; 844} 845 846void ARMAsmPrinter::emitARMAttributeSection() { 847 // <format-version> 848 // [ <section-length> "vendor-name" 849 // [ <file-tag> <size> <attribute>* 850 // | <section-tag> <size> <section-number>* 0 <attribute>* 851 // | <symbol-tag> <size> <symbol-number>* 0 <attribute>* 852 // ]+ 853 // ]* 854 855 if (OutStreamer.hasRawTextSupport()) 856 return; 857 858 const ARMElfTargetObjectFile &TLOFELF = 859 static_cast<const ARMElfTargetObjectFile &> 860 (getObjFileLowering()); 861 862 OutStreamer.SwitchSection(TLOFELF.getAttributesSection()); 863 864 // Format version 865 OutStreamer.EmitIntValue(0x41, 1); 866} 867 868//===----------------------------------------------------------------------===// 869 870static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber, 871 unsigned LabelId, MCContext &Ctx) { 872 873 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix) 874 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId)); 875 return Label; 876} 877 878static MCSymbolRefExpr::VariantKind 879getModifierVariantKind(ARMCP::ARMCPModifier Modifier) { 880 switch (Modifier) { 881 case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None; 882 case ARMCP::TLSGD: return MCSymbolRefExpr::VK_ARM_TLSGD; 883 case ARMCP::TPOFF: return MCSymbolRefExpr::VK_ARM_TPOFF; 884 case ARMCP::GOTTPOFF: return MCSymbolRefExpr::VK_ARM_GOTTPOFF; 885 case ARMCP::GOT: return MCSymbolRefExpr::VK_ARM_GOT; 886 case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_ARM_GOTOFF; 887 } 888 llvm_unreachable("Invalid ARMCPModifier!"); 889} 890 891MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV) { 892 bool isIndirect = Subtarget->isTargetDarwin() && 893 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel()); 894 if (!isIndirect) 895 return Mang->getSymbol(GV); 896 897 // FIXME: Remove this when Darwin transition to @GOT like syntax. 898 MCSymbol *MCSym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr"); 899 MachineModuleInfoMachO &MMIMachO = 900 MMI->getObjFileInfo<MachineModuleInfoMachO>(); 901 MachineModuleInfoImpl::StubValueTy &StubSym = 902 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym) : 903 MMIMachO.getGVStubEntry(MCSym); 904 if (StubSym.getPointer() == 0) 905 StubSym = MachineModuleInfoImpl:: 906 StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage()); 907 return MCSym; 908} 909 910void ARMAsmPrinter:: 911EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) { 912 int Size = TM.getTargetData()->getTypeAllocSize(MCPV->getType()); 913 914 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV); 915 916 MCSymbol *MCSym; 917 if (ACPV->isLSDA()) { 918 SmallString<128> Str; 919 raw_svector_ostream OS(Str); 920 OS << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber(); 921 MCSym = OutContext.GetOrCreateSymbol(OS.str()); 922 } else if (ACPV->isBlockAddress()) { 923 const BlockAddress *BA = 924 cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress(); 925 MCSym = GetBlockAddressSymbol(BA); 926 } else if (ACPV->isGlobalValue()) { 927 const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV(); 928 MCSym = GetARMGVSymbol(GV); 929 } else if (ACPV->isMachineBasicBlock()) { 930 const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB(); 931 MCSym = MBB->getSymbol(); 932 } else { 933 assert(ACPV->isExtSymbol() && "unrecognized constant pool value"); 934 const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol(); 935 MCSym = GetExternalSymbolSymbol(Sym); 936 } 937 938 // Create an MCSymbol for the reference. 939 const MCExpr *Expr = 940 MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()), 941 OutContext); 942 943 if (ACPV->getPCAdjustment()) { 944 MCSymbol *PCLabel = getPICLabel(MAI->getPrivateGlobalPrefix(), 945 getFunctionNumber(), 946 ACPV->getLabelId(), 947 OutContext); 948 const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext); 949 PCRelExpr = 950 MCBinaryExpr::CreateAdd(PCRelExpr, 951 MCConstantExpr::Create(ACPV->getPCAdjustment(), 952 OutContext), 953 OutContext); 954 if (ACPV->mustAddCurrentAddress()) { 955 // We want "(<expr> - .)", but MC doesn't have a concept of the '.' 956 // label, so just emit a local label end reference that instead. 957 MCSymbol *DotSym = OutContext.CreateTempSymbol(); 958 OutStreamer.EmitLabel(DotSym); 959 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext); 960 PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext); 961 } 962 Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext); 963 } 964 OutStreamer.EmitValue(Expr, Size); 965} 966 967void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) { 968 unsigned Opcode = MI->getOpcode(); 969 int OpNum = 1; 970 if (Opcode == ARM::BR_JTadd) 971 OpNum = 2; 972 else if (Opcode == ARM::BR_JTm) 973 OpNum = 3; 974 975 const MachineOperand &MO1 = MI->getOperand(OpNum); 976 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id 977 unsigned JTI = MO1.getIndex(); 978 979 // Emit a label for the jump table. 980 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm()); 981 OutStreamer.EmitLabel(JTISymbol); 982 983 // Mark the jump table as data-in-code. 984 OutStreamer.EmitDataRegion(MCDR_DataRegionJT32); 985 986 // Emit each entry of the table. 987 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo(); 988 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables(); 989 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs; 990 991 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) { 992 MachineBasicBlock *MBB = JTBBs[i]; 993 // Construct an MCExpr for the entry. We want a value of the form: 994 // (BasicBlockAddr - TableBeginAddr) 995 // 996 // For example, a table with entries jumping to basic blocks BB0 and BB1 997 // would look like: 998 // LJTI_0_0: 999 // .word (LBB0 - LJTI_0_0) 1000 // .word (LBB1 - LJTI_0_0) 1001 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext); 1002 1003 if (TM.getRelocationModel() == Reloc::PIC_) 1004 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol, 1005 OutContext), 1006 OutContext); 1007 // If we're generating a table of Thumb addresses in static relocation 1008 // model, we need to add one to keep interworking correctly. 1009 else if (AFI->isThumbFunction()) 1010 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(1,OutContext), 1011 OutContext); 1012 OutStreamer.EmitValue(Expr, 4); 1013 } 1014 // Mark the end of jump table data-in-code region. 1015 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd); 1016} 1017 1018void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) { 1019 unsigned Opcode = MI->getOpcode(); 1020 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1; 1021 const MachineOperand &MO1 = MI->getOperand(OpNum); 1022 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id 1023 unsigned JTI = MO1.getIndex(); 1024 1025 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm()); 1026 OutStreamer.EmitLabel(JTISymbol); 1027 1028 // Emit each entry of the table. 1029 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo(); 1030 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables(); 1031 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs; 1032 unsigned OffsetWidth = 4; 1033 if (MI->getOpcode() == ARM::t2TBB_JT) { 1034 OffsetWidth = 1; 1035 // Mark the jump table as data-in-code. 1036 OutStreamer.EmitDataRegion(MCDR_DataRegionJT8); 1037 } else if (MI->getOpcode() == ARM::t2TBH_JT) { 1038 OffsetWidth = 2; 1039 // Mark the jump table as data-in-code. 1040 OutStreamer.EmitDataRegion(MCDR_DataRegionJT16); 1041 } 1042 1043 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) { 1044 MachineBasicBlock *MBB = JTBBs[i]; 1045 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(), 1046 OutContext); 1047 // If this isn't a TBB or TBH, the entries are direct branch instructions. 1048 if (OffsetWidth == 4) { 1049 MCInst BrInst; 1050 BrInst.setOpcode(ARM::t2B); 1051 BrInst.addOperand(MCOperand::CreateExpr(MBBSymbolExpr)); 1052 BrInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); 1053 BrInst.addOperand(MCOperand::CreateReg(0)); 1054 OutStreamer.EmitInstruction(BrInst); 1055 continue; 1056 } 1057 // Otherwise it's an offset from the dispatch instruction. Construct an 1058 // MCExpr for the entry. We want a value of the form: 1059 // (BasicBlockAddr - TableBeginAddr) / 2 1060 // 1061 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1 1062 // would look like: 1063 // LJTI_0_0: 1064 // .byte (LBB0 - LJTI_0_0) / 2 1065 // .byte (LBB1 - LJTI_0_0) / 2 1066 const MCExpr *Expr = 1067 MCBinaryExpr::CreateSub(MBBSymbolExpr, 1068 MCSymbolRefExpr::Create(JTISymbol, OutContext), 1069 OutContext); 1070 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext), 1071 OutContext); 1072 OutStreamer.EmitValue(Expr, OffsetWidth); 1073 } 1074 // Mark the end of jump table data-in-code region. 32-bit offsets use 1075 // actual branch instructions here, so we don't mark those as a data-region 1076 // at all. 1077 if (OffsetWidth != 4) 1078 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd); 1079} 1080 1081void ARMAsmPrinter::PrintDebugValueComment(const MachineInstr *MI, 1082 raw_ostream &OS) { 1083 unsigned NOps = MI->getNumOperands(); 1084 assert(NOps==4); 1085 OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: "; 1086 // cast away const; DIetc do not take const operands for some reason. 1087 DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata())); 1088 OS << V.getName(); 1089 OS << " <- "; 1090 // Frame address. Currently handles register +- offset only. 1091 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm()); 1092 OS << '['; printOperand(MI, 0, OS); OS << '+'; printOperand(MI, 1, OS); 1093 OS << ']'; 1094 OS << "+"; 1095 printOperand(MI, NOps-2, OS); 1096} 1097 1098static void populateADROperands(MCInst &Inst, unsigned Dest, 1099 const MCSymbol *Label, 1100 unsigned pred, unsigned ccreg, 1101 MCContext &Ctx) { 1102 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, Ctx); 1103 Inst.addOperand(MCOperand::CreateReg(Dest)); 1104 Inst.addOperand(MCOperand::CreateExpr(SymbolExpr)); 1105 // Add predicate operands. 1106 Inst.addOperand(MCOperand::CreateImm(pred)); 1107 Inst.addOperand(MCOperand::CreateReg(ccreg)); 1108} 1109 1110void ARMAsmPrinter::EmitPatchedInstruction(const MachineInstr *MI, 1111 unsigned Opcode) { 1112 MCInst TmpInst; 1113 1114 // Emit the instruction as usual, just patch the opcode. 1115 LowerARMMachineInstrToMCInst(MI, TmpInst, *this); 1116 TmpInst.setOpcode(Opcode); 1117 OutStreamer.EmitInstruction(TmpInst); 1118} 1119 1120void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) { 1121 assert(MI->getFlag(MachineInstr::FrameSetup) && 1122 "Only instruction which are involved into frame setup code are allowed"); 1123 1124 const MachineFunction &MF = *MI->getParent()->getParent(); 1125 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo(); 1126 const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>(); 1127 1128 unsigned FramePtr = RegInfo->getFrameRegister(MF); 1129 unsigned Opc = MI->getOpcode(); 1130 unsigned SrcReg, DstReg; 1131 1132 if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) { 1133 // Two special cases: 1134 // 1) tPUSH does not have src/dst regs. 1135 // 2) for Thumb1 code we sometimes materialize the constant via constpool 1136 // load. Yes, this is pretty fragile, but for now I don't see better 1137 // way... :( 1138 SrcReg = DstReg = ARM::SP; 1139 } else { 1140 SrcReg = MI->getOperand(1).getReg(); 1141 DstReg = MI->getOperand(0).getReg(); 1142 } 1143 1144 // Try to figure out the unwinding opcode out of src / dst regs. 1145 if (MI->mayStore()) { 1146 // Register saves. 1147 assert(DstReg == ARM::SP && 1148 "Only stack pointer as a destination reg is supported"); 1149 1150 SmallVector<unsigned, 4> RegList; 1151 // Skip src & dst reg, and pred ops. 1152 unsigned StartOp = 2 + 2; 1153 // Use all the operands. 1154 unsigned NumOffset = 0; 1155 1156 switch (Opc) { 1157 default: 1158 MI->dump(); 1159 llvm_unreachable("Unsupported opcode for unwinding information"); 1160 case ARM::tPUSH: 1161 // Special case here: no src & dst reg, but two extra imp ops. 1162 StartOp = 2; NumOffset = 2; 1163 case ARM::STMDB_UPD: 1164 case ARM::t2STMDB_UPD: 1165 case ARM::VSTMDDB_UPD: 1166 assert(SrcReg == ARM::SP && 1167 "Only stack pointer as a source reg is supported"); 1168 for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset; 1169 i != NumOps; ++i) { 1170 const MachineOperand &MO = MI->getOperand(i); 1171 // Actually, there should never be any impdef stuff here. Skip it 1172 // temporary to workaround PR11902. 1173 if (MO.isImplicit()) 1174 continue; 1175 RegList.push_back(MO.getReg()); 1176 } 1177 break; 1178 case ARM::STR_PRE_IMM: 1179 case ARM::STR_PRE_REG: 1180 case ARM::t2STR_PRE: 1181 assert(MI->getOperand(2).getReg() == ARM::SP && 1182 "Only stack pointer as a source reg is supported"); 1183 RegList.push_back(SrcReg); 1184 break; 1185 } 1186 OutStreamer.EmitRegSave(RegList, Opc == ARM::VSTMDDB_UPD); 1187 } else { 1188 // Changes of stack / frame pointer. 1189 if (SrcReg == ARM::SP) { 1190 int64_t Offset = 0; 1191 switch (Opc) { 1192 default: 1193 MI->dump(); 1194 llvm_unreachable("Unsupported opcode for unwinding information"); 1195 case ARM::MOVr: 1196 case ARM::tMOVr: 1197 Offset = 0; 1198 break; 1199 case ARM::ADDri: 1200 Offset = -MI->getOperand(2).getImm(); 1201 break; 1202 case ARM::SUBri: 1203 case ARM::t2SUBri: 1204 Offset = MI->getOperand(2).getImm(); 1205 break; 1206 case ARM::tSUBspi: 1207 Offset = MI->getOperand(2).getImm()*4; 1208 break; 1209 case ARM::tADDspi: 1210 case ARM::tADDrSPi: 1211 Offset = -MI->getOperand(2).getImm()*4; 1212 break; 1213 case ARM::tLDRpci: { 1214 // Grab the constpool index and check, whether it corresponds to 1215 // original or cloned constpool entry. 1216 unsigned CPI = MI->getOperand(1).getIndex(); 1217 const MachineConstantPool *MCP = MF.getConstantPool(); 1218 if (CPI >= MCP->getConstants().size()) 1219 CPI = AFI.getOriginalCPIdx(CPI); 1220 assert(CPI != -1U && "Invalid constpool index"); 1221 1222 // Derive the actual offset. 1223 const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI]; 1224 assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry"); 1225 // FIXME: Check for user, it should be "add" instruction! 1226 Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue(); 1227 break; 1228 } 1229 } 1230 1231 if (DstReg == FramePtr && FramePtr != ARM::SP) 1232 // Set-up of the frame pointer. Positive values correspond to "add" 1233 // instruction. 1234 OutStreamer.EmitSetFP(FramePtr, ARM::SP, -Offset); 1235 else if (DstReg == ARM::SP) { 1236 // Change of SP by an offset. Positive values correspond to "sub" 1237 // instruction. 1238 OutStreamer.EmitPad(Offset); 1239 } else { 1240 MI->dump(); 1241 llvm_unreachable("Unsupported opcode for unwinding information"); 1242 } 1243 } else if (DstReg == ARM::SP) { 1244 // FIXME: .movsp goes here 1245 MI->dump(); 1246 llvm_unreachable("Unsupported opcode for unwinding information"); 1247 } 1248 else { 1249 MI->dump(); 1250 llvm_unreachable("Unsupported opcode for unwinding information"); 1251 } 1252 } 1253} 1254 1255extern cl::opt<bool> EnableARMEHABI; 1256 1257// Simple pseudo-instructions have their lowering (with expansion to real 1258// instructions) auto-generated. 1259#include "ARMGenMCPseudoLowering.inc" 1260 1261void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { 1262 // If we just ended a constant pool, mark it as such. 1263 if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) { 1264 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd); 1265 InConstantPool = false; 1266 } 1267 1268 // Emit unwinding stuff for frame-related instructions 1269 if (EnableARMEHABI && MI->getFlag(MachineInstr::FrameSetup)) 1270 EmitUnwindingInstruction(MI); 1271 1272 // Do any auto-generated pseudo lowerings. 1273 if (emitPseudoExpansionLowering(OutStreamer, MI)) 1274 return; 1275 1276 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) && 1277 "Pseudo flag setting opcode should be expanded early"); 1278 1279 // Check for manual lowerings. 1280 unsigned Opc = MI->getOpcode(); 1281 switch (Opc) { 1282 case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass"); 1283 case ARM::DBG_VALUE: { 1284 if (isVerbose() && OutStreamer.hasRawTextSupport()) { 1285 SmallString<128> TmpStr; 1286 raw_svector_ostream OS(TmpStr); 1287 PrintDebugValueComment(MI, OS); 1288 OutStreamer.EmitRawText(StringRef(OS.str())); 1289 } 1290 return; 1291 } 1292 case ARM::LEApcrel: 1293 case ARM::tLEApcrel: 1294 case ARM::t2LEApcrel: { 1295 // FIXME: Need to also handle globals and externals 1296 MCInst TmpInst; 1297 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrel ? ARM::t2ADR 1298 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR 1299 : ARM::ADR)); 1300 populateADROperands(TmpInst, MI->getOperand(0).getReg(), 1301 GetCPISymbol(MI->getOperand(1).getIndex()), 1302 MI->getOperand(2).getImm(), MI->getOperand(3).getReg(), 1303 OutContext); 1304 OutStreamer.EmitInstruction(TmpInst); 1305 return; 1306 } 1307 case ARM::LEApcrelJT: 1308 case ARM::tLEApcrelJT: 1309 case ARM::t2LEApcrelJT: { 1310 MCInst TmpInst; 1311 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrelJT ? ARM::t2ADR 1312 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR 1313 : ARM::ADR)); 1314 populateADROperands(TmpInst, MI->getOperand(0).getReg(), 1315 GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(), 1316 MI->getOperand(2).getImm()), 1317 MI->getOperand(3).getImm(), MI->getOperand(4).getReg(), 1318 OutContext); 1319 OutStreamer.EmitInstruction(TmpInst); 1320 return; 1321 } 1322 // Darwin call instructions are just normal call instructions with different 1323 // clobber semantics (they clobber R9). 1324 case ARM::BX_CALL: { 1325 { 1326 MCInst TmpInst; 1327 TmpInst.setOpcode(ARM::MOVr); 1328 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR)); 1329 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC)); 1330 // Add predicate operands. 1331 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); 1332 TmpInst.addOperand(MCOperand::CreateReg(0)); 1333 // Add 's' bit operand (always reg0 for this) 1334 TmpInst.addOperand(MCOperand::CreateReg(0)); 1335 OutStreamer.EmitInstruction(TmpInst); 1336 } 1337 { 1338 MCInst TmpInst; 1339 TmpInst.setOpcode(ARM::BX); 1340 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg())); 1341 OutStreamer.EmitInstruction(TmpInst); 1342 } 1343 return; 1344 } 1345 case ARM::tBX_CALL: { 1346 { 1347 MCInst TmpInst; 1348 TmpInst.setOpcode(ARM::tMOVr); 1349 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR)); 1350 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC)); 1351 // Add predicate operands. 1352 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); 1353 TmpInst.addOperand(MCOperand::CreateReg(0)); 1354 OutStreamer.EmitInstruction(TmpInst); 1355 } 1356 { 1357 MCInst TmpInst; 1358 TmpInst.setOpcode(ARM::tBX); 1359 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg())); 1360 // Add predicate operands. 1361 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); 1362 TmpInst.addOperand(MCOperand::CreateReg(0)); 1363 OutStreamer.EmitInstruction(TmpInst); 1364 } 1365 return; 1366 } 1367 case ARM::BMOVPCRX_CALL: { 1368 { 1369 MCInst TmpInst; 1370 TmpInst.setOpcode(ARM::MOVr); 1371 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR)); 1372 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC)); 1373 // Add predicate operands. 1374 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); 1375 TmpInst.addOperand(MCOperand::CreateReg(0)); 1376 // Add 's' bit operand (always reg0 for this) 1377 TmpInst.addOperand(MCOperand::CreateReg(0)); 1378 OutStreamer.EmitInstruction(TmpInst); 1379 } 1380 { 1381 MCInst TmpInst; 1382 TmpInst.setOpcode(ARM::MOVr); 1383 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC)); 1384 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg())); 1385 // Add predicate operands. 1386 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); 1387 TmpInst.addOperand(MCOperand::CreateReg(0)); 1388 // Add 's' bit operand (always reg0 for this) 1389 TmpInst.addOperand(MCOperand::CreateReg(0)); 1390 OutStreamer.EmitInstruction(TmpInst); 1391 } 1392 return; 1393 } 1394 case ARM::BMOVPCB_CALL: { 1395 { 1396 MCInst TmpInst; 1397 TmpInst.setOpcode(ARM::MOVr); 1398 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR)); 1399 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC)); 1400 // Add predicate operands. 1401 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); 1402 TmpInst.addOperand(MCOperand::CreateReg(0)); 1403 // Add 's' bit operand (always reg0 for this) 1404 TmpInst.addOperand(MCOperand::CreateReg(0)); 1405 OutStreamer.EmitInstruction(TmpInst); 1406 } 1407 { 1408 MCInst TmpInst; 1409 TmpInst.setOpcode(ARM::Bcc); 1410 const GlobalValue *GV = MI->getOperand(0).getGlobal(); 1411 MCSymbol *GVSym = Mang->getSymbol(GV); 1412 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext); 1413 TmpInst.addOperand(MCOperand::CreateExpr(GVSymExpr)); 1414 // Add predicate operands. 1415 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); 1416 TmpInst.addOperand(MCOperand::CreateReg(0)); 1417 OutStreamer.EmitInstruction(TmpInst); 1418 } 1419 return; 1420 } 1421 case ARM::MOVi16_ga_pcrel: 1422 case ARM::t2MOVi16_ga_pcrel: { 1423 MCInst TmpInst; 1424 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16); 1425 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg())); 1426 1427 unsigned TF = MI->getOperand(1).getTargetFlags(); 1428 bool isPIC = TF == ARMII::MO_LO16_NONLAZY_PIC; 1429 const GlobalValue *GV = MI->getOperand(1).getGlobal(); 1430 MCSymbol *GVSym = GetARMGVSymbol(GV); 1431 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext); 1432 if (isPIC) { 1433 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(), 1434 getFunctionNumber(), 1435 MI->getOperand(2).getImm(), OutContext); 1436 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext); 1437 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4; 1438 const MCExpr *PCRelExpr = 1439 ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr, 1440 MCBinaryExpr::CreateAdd(LabelSymExpr, 1441 MCConstantExpr::Create(PCAdj, OutContext), 1442 OutContext), OutContext), OutContext); 1443 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr)); 1444 } else { 1445 const MCExpr *RefExpr= ARMMCExpr::CreateLower16(GVSymExpr, OutContext); 1446 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr)); 1447 } 1448 1449 // Add predicate operands. 1450 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); 1451 TmpInst.addOperand(MCOperand::CreateReg(0)); 1452 // Add 's' bit operand (always reg0 for this) 1453 TmpInst.addOperand(MCOperand::CreateReg(0)); 1454 OutStreamer.EmitInstruction(TmpInst); 1455 return; 1456 } 1457 case ARM::MOVTi16_ga_pcrel: 1458 case ARM::t2MOVTi16_ga_pcrel: { 1459 MCInst TmpInst; 1460 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel 1461 ? ARM::MOVTi16 : ARM::t2MOVTi16); 1462 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg())); 1463 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg())); 1464 1465 unsigned TF = MI->getOperand(2).getTargetFlags(); 1466 bool isPIC = TF == ARMII::MO_HI16_NONLAZY_PIC; 1467 const GlobalValue *GV = MI->getOperand(2).getGlobal(); 1468 MCSymbol *GVSym = GetARMGVSymbol(GV); 1469 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext); 1470 if (isPIC) { 1471 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(), 1472 getFunctionNumber(), 1473 MI->getOperand(3).getImm(), OutContext); 1474 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext); 1475 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4; 1476 const MCExpr *PCRelExpr = 1477 ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr, 1478 MCBinaryExpr::CreateAdd(LabelSymExpr, 1479 MCConstantExpr::Create(PCAdj, OutContext), 1480 OutContext), OutContext), OutContext); 1481 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr)); 1482 } else { 1483 const MCExpr *RefExpr= ARMMCExpr::CreateUpper16(GVSymExpr, OutContext); 1484 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr)); 1485 } 1486 // Add predicate operands. 1487 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); 1488 TmpInst.addOperand(MCOperand::CreateReg(0)); 1489 // Add 's' bit operand (always reg0 for this) 1490 TmpInst.addOperand(MCOperand::CreateReg(0)); 1491 OutStreamer.EmitInstruction(TmpInst); 1492 return; 1493 } 1494 case ARM::tPICADD: { 1495 // This is a pseudo op for a label + instruction sequence, which looks like: 1496 // LPC0: 1497 // add r0, pc 1498 // This adds the address of LPC0 to r0. 1499 1500 // Emit the label. 1501 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(), 1502 getFunctionNumber(), MI->getOperand(2).getImm(), 1503 OutContext)); 1504 1505 // Form and emit the add. 1506 MCInst AddInst; 1507 AddInst.setOpcode(ARM::tADDhirr); 1508 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg())); 1509 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg())); 1510 AddInst.addOperand(MCOperand::CreateReg(ARM::PC)); 1511 // Add predicate operands. 1512 AddInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); 1513 AddInst.addOperand(MCOperand::CreateReg(0)); 1514 OutStreamer.EmitInstruction(AddInst); 1515 return; 1516 } 1517 case ARM::PICADD: { 1518 // This is a pseudo op for a label + instruction sequence, which looks like: 1519 // LPC0: 1520 // add r0, pc, r0 1521 // This adds the address of LPC0 to r0. 1522 1523 // Emit the label. 1524 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(), 1525 getFunctionNumber(), MI->getOperand(2).getImm(), 1526 OutContext)); 1527 1528 // Form and emit the add. 1529 MCInst AddInst; 1530 AddInst.setOpcode(ARM::ADDrr); 1531 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg())); 1532 AddInst.addOperand(MCOperand::CreateReg(ARM::PC)); 1533 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg())); 1534 // Add predicate operands. 1535 AddInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm())); 1536 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg())); 1537 // Add 's' bit operand (always reg0 for this) 1538 AddInst.addOperand(MCOperand::CreateReg(0)); 1539 OutStreamer.EmitInstruction(AddInst); 1540 return; 1541 } 1542 case ARM::PICSTR: 1543 case ARM::PICSTRB: 1544 case ARM::PICSTRH: 1545 case ARM::PICLDR: 1546 case ARM::PICLDRB: 1547 case ARM::PICLDRH: 1548 case ARM::PICLDRSB: 1549 case ARM::PICLDRSH: { 1550 // This is a pseudo op for a label + instruction sequence, which looks like: 1551 // LPC0: 1552 // OP r0, [pc, r0] 1553 // The LCP0 label is referenced by a constant pool entry in order to get 1554 // a PC-relative address at the ldr instruction. 1555 1556 // Emit the label. 1557 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(), 1558 getFunctionNumber(), MI->getOperand(2).getImm(), 1559 OutContext)); 1560 1561 // Form and emit the load 1562 unsigned Opcode; 1563 switch (MI->getOpcode()) { 1564 default: 1565 llvm_unreachable("Unexpected opcode!"); 1566 case ARM::PICSTR: Opcode = ARM::STRrs; break; 1567 case ARM::PICSTRB: Opcode = ARM::STRBrs; break; 1568 case ARM::PICSTRH: Opcode = ARM::STRH; break; 1569 case ARM::PICLDR: Opcode = ARM::LDRrs; break; 1570 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break; 1571 case ARM::PICLDRH: Opcode = ARM::LDRH; break; 1572 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break; 1573 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break; 1574 } 1575 MCInst LdStInst; 1576 LdStInst.setOpcode(Opcode); 1577 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg())); 1578 LdStInst.addOperand(MCOperand::CreateReg(ARM::PC)); 1579 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg())); 1580 LdStInst.addOperand(MCOperand::CreateImm(0)); 1581 // Add predicate operands. 1582 LdStInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm())); 1583 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg())); 1584 OutStreamer.EmitInstruction(LdStInst); 1585 1586 return; 1587 } 1588 case ARM::CONSTPOOL_ENTRY: { 1589 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool 1590 /// in the function. The first operand is the ID# for this instruction, the 1591 /// second is the index into the MachineConstantPool that this is, the third 1592 /// is the size in bytes of this constant pool entry. 1593 /// The required alignment is specified on the basic block holding this MI. 1594 unsigned LabelId = (unsigned)MI->getOperand(0).getImm(); 1595 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex(); 1596 1597 // If this is the first entry of the pool, mark it. 1598 if (!InConstantPool) { 1599 OutStreamer.EmitDataRegion(MCDR_DataRegion); 1600 InConstantPool = true; 1601 } 1602 1603 OutStreamer.EmitLabel(GetCPISymbol(LabelId)); 1604 1605 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx]; 1606 if (MCPE.isMachineConstantPoolEntry()) 1607 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal); 1608 else 1609 EmitGlobalConstant(MCPE.Val.ConstVal); 1610 return; 1611 } 1612 case ARM::t2BR_JT: { 1613 // Lower and emit the instruction itself, then the jump table following it. 1614 MCInst TmpInst; 1615 TmpInst.setOpcode(ARM::tMOVr); 1616 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC)); 1617 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg())); 1618 // Add predicate operands. 1619 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); 1620 TmpInst.addOperand(MCOperand::CreateReg(0)); 1621 OutStreamer.EmitInstruction(TmpInst); 1622 // Output the data for the jump table itself 1623 EmitJump2Table(MI); 1624 return; 1625 } 1626 case ARM::t2TBB_JT: { 1627 // Lower and emit the instruction itself, then the jump table following it. 1628 MCInst TmpInst; 1629 1630 TmpInst.setOpcode(ARM::t2TBB); 1631 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC)); 1632 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg())); 1633 // Add predicate operands. 1634 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); 1635 TmpInst.addOperand(MCOperand::CreateReg(0)); 1636 OutStreamer.EmitInstruction(TmpInst); 1637 // Output the data for the jump table itself 1638 EmitJump2Table(MI); 1639 // Make sure the next instruction is 2-byte aligned. 1640 EmitAlignment(1); 1641 return; 1642 } 1643 case ARM::t2TBH_JT: { 1644 // Lower and emit the instruction itself, then the jump table following it. 1645 MCInst TmpInst; 1646 1647 TmpInst.setOpcode(ARM::t2TBH); 1648 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC)); 1649 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg())); 1650 // Add predicate operands. 1651 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); 1652 TmpInst.addOperand(MCOperand::CreateReg(0)); 1653 OutStreamer.EmitInstruction(TmpInst); 1654 // Output the data for the jump table itself 1655 EmitJump2Table(MI); 1656 return; 1657 } 1658 case ARM::tBR_JTr: 1659 case ARM::BR_JTr: { 1660 // Lower and emit the instruction itself, then the jump table following it. 1661 // mov pc, target 1662 MCInst TmpInst; 1663 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ? 1664 ARM::MOVr : ARM::tMOVr; 1665 TmpInst.setOpcode(Opc); 1666 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC)); 1667 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg())); 1668 // Add predicate operands. 1669 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); 1670 TmpInst.addOperand(MCOperand::CreateReg(0)); 1671 // Add 's' bit operand (always reg0 for this) 1672 if (Opc == ARM::MOVr) 1673 TmpInst.addOperand(MCOperand::CreateReg(0)); 1674 OutStreamer.EmitInstruction(TmpInst); 1675 1676 // Make sure the Thumb jump table is 4-byte aligned. 1677 if (Opc == ARM::tMOVr) 1678 EmitAlignment(2); 1679 1680 // Output the data for the jump table itself 1681 EmitJumpTable(MI); 1682 return; 1683 } 1684 case ARM::BR_JTm: { 1685 // Lower and emit the instruction itself, then the jump table following it. 1686 // ldr pc, target 1687 MCInst TmpInst; 1688 if (MI->getOperand(1).getReg() == 0) { 1689 // literal offset 1690 TmpInst.setOpcode(ARM::LDRi12); 1691 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC)); 1692 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg())); 1693 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm())); 1694 } else { 1695 TmpInst.setOpcode(ARM::LDRrs); 1696 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC)); 1697 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg())); 1698 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg())); 1699 TmpInst.addOperand(MCOperand::CreateImm(0)); 1700 } 1701 // Add predicate operands. 1702 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); 1703 TmpInst.addOperand(MCOperand::CreateReg(0)); 1704 OutStreamer.EmitInstruction(TmpInst); 1705 1706 // Output the data for the jump table itself 1707 EmitJumpTable(MI); 1708 return; 1709 } 1710 case ARM::BR_JTadd: { 1711 // Lower and emit the instruction itself, then the jump table following it. 1712 // add pc, target, idx 1713 MCInst TmpInst; 1714 TmpInst.setOpcode(ARM::ADDrr); 1715 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC)); 1716 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg())); 1717 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg())); 1718 // Add predicate operands. 1719 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); 1720 TmpInst.addOperand(MCOperand::CreateReg(0)); 1721 // Add 's' bit operand (always reg0 for this) 1722 TmpInst.addOperand(MCOperand::CreateReg(0)); 1723 OutStreamer.EmitInstruction(TmpInst); 1724 1725 // Output the data for the jump table itself 1726 EmitJumpTable(MI); 1727 return; 1728 } 1729 case ARM::TRAP: { 1730 // Non-Darwin binutils don't yet support the "trap" mnemonic. 1731 // FIXME: Remove this special case when they do. 1732 if (!Subtarget->isTargetDarwin()) { 1733 //.long 0xe7ffdefe @ trap 1734 uint32_t Val = 0xe7ffdefeUL; 1735 OutStreamer.AddComment("trap"); 1736 OutStreamer.EmitIntValue(Val, 4); 1737 return; 1738 } 1739 break; 1740 } 1741 case ARM::tTRAP: { 1742 // Non-Darwin binutils don't yet support the "trap" mnemonic. 1743 // FIXME: Remove this special case when they do. 1744 if (!Subtarget->isTargetDarwin()) { 1745 //.short 57086 @ trap 1746 uint16_t Val = 0xdefe; 1747 OutStreamer.AddComment("trap"); 1748 OutStreamer.EmitIntValue(Val, 2); 1749 return; 1750 } 1751 break; 1752 } 1753 case ARM::t2Int_eh_sjlj_setjmp: 1754 case ARM::t2Int_eh_sjlj_setjmp_nofp: 1755 case ARM::tInt_eh_sjlj_setjmp: { 1756 // Two incoming args: GPR:$src, GPR:$val 1757 // mov $val, pc 1758 // adds $val, #7 1759 // str $val, [$src, #4] 1760 // movs r0, #0 1761 // b 1f 1762 // movs r0, #1 1763 // 1: 1764 unsigned SrcReg = MI->getOperand(0).getReg(); 1765 unsigned ValReg = MI->getOperand(1).getReg(); 1766 MCSymbol *Label = GetARMSJLJEHLabel(); 1767 { 1768 MCInst TmpInst; 1769 TmpInst.setOpcode(ARM::tMOVr); 1770 TmpInst.addOperand(MCOperand::CreateReg(ValReg)); 1771 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC)); 1772 // Predicate. 1773 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); 1774 TmpInst.addOperand(MCOperand::CreateReg(0)); 1775 OutStreamer.AddComment("eh_setjmp begin"); 1776 OutStreamer.EmitInstruction(TmpInst); 1777 } 1778 { 1779 MCInst TmpInst; 1780 TmpInst.setOpcode(ARM::tADDi3); 1781 TmpInst.addOperand(MCOperand::CreateReg(ValReg)); 1782 // 's' bit operand 1783 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1784 TmpInst.addOperand(MCOperand::CreateReg(ValReg)); 1785 TmpInst.addOperand(MCOperand::CreateImm(7)); 1786 // Predicate. 1787 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); 1788 TmpInst.addOperand(MCOperand::CreateReg(0)); 1789 OutStreamer.EmitInstruction(TmpInst); 1790 } 1791 { 1792 MCInst TmpInst; 1793 TmpInst.setOpcode(ARM::tSTRi); 1794 TmpInst.addOperand(MCOperand::CreateReg(ValReg)); 1795 TmpInst.addOperand(MCOperand::CreateReg(SrcReg)); 1796 // The offset immediate is #4. The operand value is scaled by 4 for the 1797 // tSTR instruction. 1798 TmpInst.addOperand(MCOperand::CreateImm(1)); 1799 // Predicate. 1800 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); 1801 TmpInst.addOperand(MCOperand::CreateReg(0)); 1802 OutStreamer.EmitInstruction(TmpInst); 1803 } 1804 { 1805 MCInst TmpInst; 1806 TmpInst.setOpcode(ARM::tMOVi8); 1807 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0)); 1808 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1809 TmpInst.addOperand(MCOperand::CreateImm(0)); 1810 // Predicate. 1811 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); 1812 TmpInst.addOperand(MCOperand::CreateReg(0)); 1813 OutStreamer.EmitInstruction(TmpInst); 1814 } 1815 { 1816 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext); 1817 MCInst TmpInst; 1818 TmpInst.setOpcode(ARM::tB); 1819 TmpInst.addOperand(MCOperand::CreateExpr(SymbolExpr)); 1820 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); 1821 TmpInst.addOperand(MCOperand::CreateReg(0)); 1822 OutStreamer.EmitInstruction(TmpInst); 1823 } 1824 { 1825 MCInst TmpInst; 1826 TmpInst.setOpcode(ARM::tMOVi8); 1827 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0)); 1828 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1829 TmpInst.addOperand(MCOperand::CreateImm(1)); 1830 // Predicate. 1831 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); 1832 TmpInst.addOperand(MCOperand::CreateReg(0)); 1833 OutStreamer.AddComment("eh_setjmp end"); 1834 OutStreamer.EmitInstruction(TmpInst); 1835 } 1836 OutStreamer.EmitLabel(Label); 1837 return; 1838 } 1839 1840 case ARM::Int_eh_sjlj_setjmp_nofp: 1841 case ARM::Int_eh_sjlj_setjmp: { 1842 // Two incoming args: GPR:$src, GPR:$val 1843 // add $val, pc, #8 1844 // str $val, [$src, #+4] 1845 // mov r0, #0 1846 // add pc, pc, #0 1847 // mov r0, #1 1848 unsigned SrcReg = MI->getOperand(0).getReg(); 1849 unsigned ValReg = MI->getOperand(1).getReg(); 1850 1851 { 1852 MCInst TmpInst; 1853 TmpInst.setOpcode(ARM::ADDri); 1854 TmpInst.addOperand(MCOperand::CreateReg(ValReg)); 1855 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC)); 1856 TmpInst.addOperand(MCOperand::CreateImm(8)); 1857 // Predicate. 1858 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); 1859 TmpInst.addOperand(MCOperand::CreateReg(0)); 1860 // 's' bit operand (always reg0 for this). 1861 TmpInst.addOperand(MCOperand::CreateReg(0)); 1862 OutStreamer.AddComment("eh_setjmp begin"); 1863 OutStreamer.EmitInstruction(TmpInst); 1864 } 1865 { 1866 MCInst TmpInst; 1867 TmpInst.setOpcode(ARM::STRi12); 1868 TmpInst.addOperand(MCOperand::CreateReg(ValReg)); 1869 TmpInst.addOperand(MCOperand::CreateReg(SrcReg)); 1870 TmpInst.addOperand(MCOperand::CreateImm(4)); 1871 // Predicate. 1872 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); 1873 TmpInst.addOperand(MCOperand::CreateReg(0)); 1874 OutStreamer.EmitInstruction(TmpInst); 1875 } 1876 { 1877 MCInst TmpInst; 1878 TmpInst.setOpcode(ARM::MOVi); 1879 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0)); 1880 TmpInst.addOperand(MCOperand::CreateImm(0)); 1881 // Predicate. 1882 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); 1883 TmpInst.addOperand(MCOperand::CreateReg(0)); 1884 // 's' bit operand (always reg0 for this). 1885 TmpInst.addOperand(MCOperand::CreateReg(0)); 1886 OutStreamer.EmitInstruction(TmpInst); 1887 } 1888 { 1889 MCInst TmpInst; 1890 TmpInst.setOpcode(ARM::ADDri); 1891 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC)); 1892 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC)); 1893 TmpInst.addOperand(MCOperand::CreateImm(0)); 1894 // Predicate. 1895 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); 1896 TmpInst.addOperand(MCOperand::CreateReg(0)); 1897 // 's' bit operand (always reg0 for this). 1898 TmpInst.addOperand(MCOperand::CreateReg(0)); 1899 OutStreamer.EmitInstruction(TmpInst); 1900 } 1901 { 1902 MCInst TmpInst; 1903 TmpInst.setOpcode(ARM::MOVi); 1904 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0)); 1905 TmpInst.addOperand(MCOperand::CreateImm(1)); 1906 // Predicate. 1907 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); 1908 TmpInst.addOperand(MCOperand::CreateReg(0)); 1909 // 's' bit operand (always reg0 for this). 1910 TmpInst.addOperand(MCOperand::CreateReg(0)); 1911 OutStreamer.AddComment("eh_setjmp end"); 1912 OutStreamer.EmitInstruction(TmpInst); 1913 } 1914 return; 1915 } 1916 case ARM::Int_eh_sjlj_longjmp: { 1917 // ldr sp, [$src, #8] 1918 // ldr $scratch, [$src, #4] 1919 // ldr r7, [$src] 1920 // bx $scratch 1921 unsigned SrcReg = MI->getOperand(0).getReg(); 1922 unsigned ScratchReg = MI->getOperand(1).getReg(); 1923 { 1924 MCInst TmpInst; 1925 TmpInst.setOpcode(ARM::LDRi12); 1926 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP)); 1927 TmpInst.addOperand(MCOperand::CreateReg(SrcReg)); 1928 TmpInst.addOperand(MCOperand::CreateImm(8)); 1929 // Predicate. 1930 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); 1931 TmpInst.addOperand(MCOperand::CreateReg(0)); 1932 OutStreamer.EmitInstruction(TmpInst); 1933 } 1934 { 1935 MCInst TmpInst; 1936 TmpInst.setOpcode(ARM::LDRi12); 1937 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg)); 1938 TmpInst.addOperand(MCOperand::CreateReg(SrcReg)); 1939 TmpInst.addOperand(MCOperand::CreateImm(4)); 1940 // Predicate. 1941 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); 1942 TmpInst.addOperand(MCOperand::CreateReg(0)); 1943 OutStreamer.EmitInstruction(TmpInst); 1944 } 1945 { 1946 MCInst TmpInst; 1947 TmpInst.setOpcode(ARM::LDRi12); 1948 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7)); 1949 TmpInst.addOperand(MCOperand::CreateReg(SrcReg)); 1950 TmpInst.addOperand(MCOperand::CreateImm(0)); 1951 // Predicate. 1952 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); 1953 TmpInst.addOperand(MCOperand::CreateReg(0)); 1954 OutStreamer.EmitInstruction(TmpInst); 1955 } 1956 { 1957 MCInst TmpInst; 1958 TmpInst.setOpcode(ARM::BX); 1959 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg)); 1960 // Predicate. 1961 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); 1962 TmpInst.addOperand(MCOperand::CreateReg(0)); 1963 OutStreamer.EmitInstruction(TmpInst); 1964 } 1965 return; 1966 } 1967 case ARM::tInt_eh_sjlj_longjmp: { 1968 // ldr $scratch, [$src, #8] 1969 // mov sp, $scratch 1970 // ldr $scratch, [$src, #4] 1971 // ldr r7, [$src] 1972 // bx $scratch 1973 unsigned SrcReg = MI->getOperand(0).getReg(); 1974 unsigned ScratchReg = MI->getOperand(1).getReg(); 1975 { 1976 MCInst TmpInst; 1977 TmpInst.setOpcode(ARM::tLDRi); 1978 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg)); 1979 TmpInst.addOperand(MCOperand::CreateReg(SrcReg)); 1980 // The offset immediate is #8. The operand value is scaled by 4 for the 1981 // tLDR instruction. 1982 TmpInst.addOperand(MCOperand::CreateImm(2)); 1983 // Predicate. 1984 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); 1985 TmpInst.addOperand(MCOperand::CreateReg(0)); 1986 OutStreamer.EmitInstruction(TmpInst); 1987 } 1988 { 1989 MCInst TmpInst; 1990 TmpInst.setOpcode(ARM::tMOVr); 1991 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP)); 1992 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg)); 1993 // Predicate. 1994 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); 1995 TmpInst.addOperand(MCOperand::CreateReg(0)); 1996 OutStreamer.EmitInstruction(TmpInst); 1997 } 1998 { 1999 MCInst TmpInst; 2000 TmpInst.setOpcode(ARM::tLDRi); 2001 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg)); 2002 TmpInst.addOperand(MCOperand::CreateReg(SrcReg)); 2003 TmpInst.addOperand(MCOperand::CreateImm(1)); 2004 // Predicate. 2005 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); 2006 TmpInst.addOperand(MCOperand::CreateReg(0)); 2007 OutStreamer.EmitInstruction(TmpInst); 2008 } 2009 { 2010 MCInst TmpInst; 2011 TmpInst.setOpcode(ARM::tLDRi); 2012 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7)); 2013 TmpInst.addOperand(MCOperand::CreateReg(SrcReg)); 2014 TmpInst.addOperand(MCOperand::CreateImm(0)); 2015 // Predicate. 2016 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); 2017 TmpInst.addOperand(MCOperand::CreateReg(0)); 2018 OutStreamer.EmitInstruction(TmpInst); 2019 } 2020 { 2021 MCInst TmpInst; 2022 TmpInst.setOpcode(ARM::tBX); 2023 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg)); 2024 // Predicate. 2025 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); 2026 TmpInst.addOperand(MCOperand::CreateReg(0)); 2027 OutStreamer.EmitInstruction(TmpInst); 2028 } 2029 return; 2030 } 2031 } 2032 2033 MCInst TmpInst; 2034 LowerARMMachineInstrToMCInst(MI, TmpInst, *this); 2035 2036 OutStreamer.EmitInstruction(TmpInst); 2037} 2038 2039//===----------------------------------------------------------------------===// 2040// Target Registry Stuff 2041//===----------------------------------------------------------------------===// 2042 2043// Force static initialization. 2044extern "C" void LLVMInitializeARMAsmPrinter() { 2045 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget); 2046 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget); 2047} 2048