| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelDAGToDAG.cpp | 813 int Mask = -cast<ConstantSDNode>(A.getNode())->getSExtValue(); local
1124 uint32_t Mask = MN->getZExtValue(); local
1534 uint64_t Mask = (1 << NumBits) - 1; local
1552 uint64_t Mask = (1 << NumBits) - 1; local
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| H A D | HexagonInstrInfo.cpp | 1765 analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const argument
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| H A D | HexagonISelLowering.cpp | 564 const uint32_t *Mask = HRI.getCallPreservedMask(MF, CallConv); local
1148 const uint32_t *Mask = HRI.getCallPreservedMask(MF, CallingConv::C); local
1919 bool HexagonTargetLowering::isShuffleMaskLegal(ArrayRef<int> Mask, argument
2306 uint64_t Mask = (ElemTy == MVT::i8) ? 0xFFull local
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 498 ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(Op1); local
620 APInt Mask, InvMask; local
1617 APInt Mask = APInt::getHighBitsSet(EltTy.getSizeInBits(), local
1632 APInt Mask = APInt::getLowBitsSet(EltTy.getSizeInBits(), local
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| H A D | MipsISelLowering.cpp | 791 SDValue Mask = N->getOperand(1); local
1666 Register Mask = RegInfo.createVirtualRegister(RC); local
1915 Register Mask = RegInfo.createVirtualRegister(RC); local
3065 const uint32_t *Mask = local
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | IRTranslator.cpp | 1936 SmallVector<int, 8> Mask; local
1937 ShuffleVectorInst::getShuffleMask(cast<Constant>(U.getOperand(2)), Mask); local
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| H A D | LegalizerHelper.cpp | 1457 APInt Mask = APInt::getAllOnesValue(OrigTy.getSizeInBits()); local
4205 ArrayRef<int> Mask = MI.getOperand(3).getShuffleMask(); local
[all...] |
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | TargetTransformInfo.cpp | 1140 SmallVector<int, 16> Mask = Shuffle->getShuffleMask(); local
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| H A D | ValueTracking.cpp | 290 bool llvm::MaskedValueIsZero(const Value *V, const APInt &Mask, argument
460 APInt Mask = APInt::getHighBitsSet(BitWidth, CommonPrefixBits); local
2279 APInt Mask = APInt::getSignedMaxValue(BitWidth); local
2393 MaskedValueIsZero(const Value *V, const APInt &Mask, unsigned Depth, const Query &Q) argument
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/IR/ |
| H A D | AutoUpgrade.cpp | 958 static Value *getX86MaskVec(IRBuilder<> &Builder, Value *Mask, argument
978 static Value *EmitX86Select(IRBuilder<> &Builder, Value *Mask, argument
989 EmitX86ScalarSelect(IRBuilder< &Builder, Value *Mask, Value *Op0, Value *Op1) argument
1007 UpgradeX86ALIGNIntrinsics(IRBuilder< &Builder, Value *Op0, Value *Op1, Value *Shift, Value *Passthru, Value *Mask, bool IsVALIGN) argument
1128 Value *Mask = CI.getOperand(3); local
1155 Value *Mask = CI.getOperand(3); local
1228 Value *Mask = CI.getOperand(NumArgs - 1); local
1234 UpgradeMaskedStore(IRBuilder< &Builder, Value *Ptr, Value *Data, Value *Mask, bool Aligned) argument
1254 UpgradeMaskedLoad(IRBuilder< &Builder, Value *Ptr, Value *Passthru, Value *Mask, bool Aligned) argument
1317 Constant *Mask = ConstantInt::get(Ty, 0xffffffff); local
1331 ApplyX86MaskOn1BitsVec(IRBuilder< &Builder, Value *Vec, Value *Mask) argument
1377 Value *Mask = CI.getArgOperand(CI.getNumArgOperands() - 1); local
1395 Value* Mask = CI.getArgOperand(3); local
1410 Value *Mask = getX86MaskVec(Builder, Op, NumElts); local
1775 Value *Mask = Builder.CreateAnd(CI->getArgOperand(2), Builder.getInt8(1)); local
1849 Value *Mask = CI->getArgOperand(2); local
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| H A D | Constants.cpp | 2228 getShuffleVector(Constant *V1, Constant *V2, Constant *Mask, Type *OnlyIfReducedTy) argument
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| H A D | Instructions.cpp | 1781 ShuffleVectorInst::ShuffleVectorInst(Value *V1, Value *V2, Value *Mask, argument
1798 ShuffleVectorInst::ShuffleVectorInst(Value *V1, Value *V2, Value *Mask, argument
1835 isValidOperands(const Value *V1, const Value *V2, const Value *Mask) argument
1882 getMaskValue(const Constant *Mask, unsigned i) argument
1892 getShuffleMask(const Constant *Mask, SmallVectorImpl<int> &Result) argument
1908 isSingleSourceMaskImpl(ArrayRef<int> Mask, int NumOpElts) argument
1926 isSingleSourceMask(ArrayRef<int> Mask) argument
1932 isIdentityMaskImpl(ArrayRef<int> Mask, int NumOpElts) argument
1944 isIdentityMask(ArrayRef<int> Mask) argument
1950 isReverseMask(ArrayRef<int> Mask) argument
1962 isZeroEltSplatMask(ArrayRef<int> Mask) argument
1974 isSelectMask(ArrayRef<int> Mask) argument
1987 isTransposeMask(ArrayRef<int> Mask) argument
2021 isExtractSubvectorMask(ArrayRef<int> Mask, int NumSrcElts, int &Index) argument
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 4473 SDValue Mask = N->getOperand(1); local
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 963 const uint32_t *Mask = local
1263 const uint32_t *Mask = local
2057 const uint32_t *Mask = Subtarget->getRegisterInfo()->getCallPreservedMask( local
2247 SDValue Mask = DAG.getConstant(1, DL, Result.getValueType()); local
2280 SDValue Mask = DAG.getConstant(3, DL, Result.getValueType()); local
2287 SDValue Mask = DAG.getConstant(3, DL, Result.getValueType()); local
[all...] |
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/IPO/ |
| H A D | LowerTypeTests.cpp | 158 uint64_t Mask = 0; local
621 uint8_t Mask; local
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineAndOrXor.cpp | 279 static unsigned conjugateICmpMask(unsigned Mask) { argument
295 APInt Mask; local
618 unsigned Mask = LHSMask & RHSMask; local
888 Value *Mask = Builder.CreateOr(B, D); local
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| /freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | Instructions.h | 2046 SmallVector<int, 16> Mask; local
2075 static bool isSingleSourceMask(const Constant *Mask) { argument
2096 isIdentityMask(const Constant *Mask) argument
2133 isSelectMask(const Constant *Mask) argument
2157 isReverseMask(const Constant *Mask) argument
2177 isZeroEltSplatMask(const Constant *Mask) argument
2227 isTransposeMask(const Constant *Mask) argument
2248 isExtractSubvectorMask(const Constant *Mask, int NumSrcElts, int &Index) argument
2264 commuteShuffleMask(MutableArrayRef<int> Mask, unsigned InVecNumElts) argument
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| H A D | IRBuilder.h | 2547 Value *CreateShuffleVector(Value *V1, Value *V2, Value *Mask, argument
2558 Value *Mask = ConstantDataVector::get(Context, IntMask); local
2796 CreateAlignmentAssumptionHelper(const DataLayout &DL, Value *PtrValue, Value *Mask, Type *IntPtrTy, Value *OffsetValue, Value **TheCheck) argument
2844 Value *Mask = ConstantInt::get(IntPtrTy, Alignment - 1); local
2874 Value *Mask = CreateSub(Alignment, ConstantInt::get(IntPtrTy, 1), "mask"); local
[all...] |
| /freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | SelectionDAGNodes.h | 1509 const int *Mask; member in class:llvm::ShuffleVectorSDNode
1546 static void commuteMask(MutableArrayRef<int> Mask) { argument
[all...] |
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 5300 uint64_t Mask = AArch64_AM::decodeLogicalImmediate( local
5368 const unsigned Mask = AArch64II::MO_FRAGMENT; local
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| H A D | AArch64FastISel.cpp | 1685 uint64_t Mask = (RetVT == MVT::i8) ? 0xff : 0xffff; local
1731 uint64_t Mask = (RetVT == MVT::i8) ? 0xff : 0xffff; local
1774 uint64_t Mask = (RetVT == MVT::i8) ? 0xff : 0xffff; local
3981 uint64_t Mask = 0; local
4090 uint64_t Mask = 0; local
4196 uint64_t Mask = 0; local
4317 uint64_t Mask = 0; local
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| H A D | AArch64InstructionSelector.cpp | 3781 ArrayRef<int> Mask = I.getOperand(3).getShuffleMask(); local
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 71 void setITState(char Firstcond, char Mask) { argument
110 void setVPTState(char Mask) { argument
958 unsigned Mask = MI.getOperand(1).getImm(); local
991 unsigned Mask = MI.getOperand(0).getImm(); local
4704 unsigned Mask = fieldFromInstruction(Val, 10, 2); local
[all...] |
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.cpp | 2635 unsigned Mask = (1 << NumBits) - 1; local
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| H A D | ARMISelDAGToDAG.cpp | 4607 int Mask = 0; local
4866 int Mask = getARClassRegisterMask(Reg, Flags); local
[all...] |