| /freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/Analysis/ |
| H A D | InstructionPrecedenceTracking.h | 115 bool isDominatedByICFIFromSameBlock(const Instruction *Insn) { argument
140 isDominatedByMemoryWriteFromSameBlock(const Instruction *Insn) argument
[all...] |
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | InstructionPrecedenceTracking.cpp | 58 isPreceededBySpecialInstruction( const Instruction *Insn) argument
[all...] |
| H A D | MemorySSAUpdater.cpp | 591 Instruction *Insn = MUD->getMemoryInst(); local
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/Disassembler/ |
| H A D | AVRDisassembler.cpp | 117 uint32_t Insn; local
77 readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn) argument
90 readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn) argument
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/ExecutionEngine/RuntimeDyld/Targets/ |
| H A D | RuntimeDyldELFMips.cpp | 215 uint32_t Insn = readBytesUnaligned(TargetPtr, 4); local
[all...] |
| H A D | RuntimeDyldMachOARM.h | 272 uint32_t Insn = readBytesUnaligned(LocalAddress, 4); variable
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| /freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | PseudoLoweringEmitter.cpp | 73 addDagOperandMapping(Record *Rec, DagInit *Dag, CodeGenInstruction &Insn, argument
[all...] |
| H A D | FixedLenDecoderEmitter.cpp | 420 void insnWithID(insn_t &Insn, unsigned Opcode) const { argument
562 insn_t Insn; local
[all...] |
| H A D | GlobalISelEmitter.cpp | 1481 InstructionMatcher &Insn; member in class:__anon2930::OperandMatcher
1491 OperandMatcher(InstructionMatcher &Insn, unsigned OpIdx, argument
[all...] |
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARC/Disassembler/ |
| H A D | ARCDisassembler.cpp | 145 static unsigned decodeCField(unsigned Insn) { argument
50 readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn) argument
59 readInstruction64(ArrayRef<uint8_t> Bytes, uint64_t Address, uint64_t &Size, uint64_t &Insn) argument
69 readInstruction48(ArrayRef<uint8_t> Bytes, uint64_t Address, uint64_t &Size, uint64_t &Insn) argument
78 readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn) argument
149 decodeBField(unsigned Insn) argument
154 decodeAField(unsigned Insn) argument
158 DecodeMEMrs9(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Dec) argument
[all...] |
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ExpandImm.cpp | 44 tryToreplicateChunks(uint64_t UImm, SmallVectorImpl<ImmInsnModel> &Insn) argument
152 trySequenceOfOnes(uint64_t UImm, SmallVectorImpl<ImmInsnModel> &Insn) argument
246 expandMOVImmSimple(uint64_t Imm, unsigned BitSize, unsigned OneChunks, unsigned ZeroChunks, SmallVectorImpl<ImmInsnModel> &Insn) argument
305 expandMOVImm(uint64_t Imm, unsigned BitSize, SmallVectorImpl<ImmInsnModel> &Insn) argument
[all...] |
| H A D | AArch64ExpandPseudoInsts.cpp | 124 SmallVector<AArch64_IMM::ImmInsnModel, 4> Insn; local
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| H A D | AArch64TargetTransformInfo.cpp | 54 SmallVector<AArch64_IMM::ImmInsnModel, 4> Insn; local
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/Disassembler/ |
| H A D | LanaiDisassembler.cpp | 90 static void PostOperandDecodeAdjust(MCInst &Instr, uint32_t Insn) { argument
75 readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t &Size, uint32_t &Insn) argument
135 uint32_t Insn; local
174 decodeRiMemoryValue(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
186 decodeRrMemoryValue(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
198 decodeSplsValue(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
219 decodeBranch(MCInst &MI, unsigned Insn, uint64_t Address, const void *Decoder) argument
227 decodeShiftImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
[all...] |
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64MCTargetDesc.cpp | 336 uint32_t Insn = support::endian::read32le(PltContents.data() + Byte); variable
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/Disassembler/ |
| H A D | MSP430Disassembler.cpp | 181 static AddrMode DecodeSrcAddrModeI(unsigned Insn) { argument
187 static AddrMode DecodeSrcAddrModeII(unsigned Insn) { argument
193 static AddrMode DecodeDstAddrMode(unsigned Insn) { argument
[all...] |
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/Disassembler/ |
| H A D | BPFDisassembler.cpp | 126 static DecodeStatus decodeMemoryOpValue(MCInst &Inst, unsigned Insn, argument
166 uint64_t Insn, Hi; local
137 readInstruction64(ArrayRef<uint8_t> Bytes, uint64_t Address, uint64_t &Size, uint64_t &Insn, bool IsLittleEndian) argument
[all...] |
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/Disassembler/ |
| H A D | RISCVDisassembler.cpp | 259 static DecodeStatus decodeRVCInstrSImm(MCInst &Inst, unsigned Insn, argument
269 static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, unsigned Insn, argument
281 decodeRVCInstrRdRs1UImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
294 decodeRVCInstrRdRs2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
303 decodeRVCInstrRdRs1Rs2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
320 uint32_t Insn; local
[all...] |
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | GuardWidening.cpp | 284 static bool isSupportedGuardInstruction(const Instruction *Insn) { argument
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| H A D | GVNHoist.cpp | 398 Instruction *Insn = MU->getMemoryInst(); local
601 Instruction *Insn = CHI.I; local
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/XCore/Disassembler/ |
| H A D | XCoreDisassembler.cpp | 44 readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address, uint64_t &Size, uint16_t &Insn) argument
56 readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn) argument
240 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) argument
258 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2, unsigned &Op3) argument
274 Decode2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
344 Decode2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
357 Decode2RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
370 DecodeR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
383 Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
397 DecodeRUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
410 DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
423 DecodeRUSSrcDstBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
437 DecodeL2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
508 DecodeL2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
522 DecodeLR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
536 Decode3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
549 Decode3RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
562 Decode2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
575 Decode2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
588 DecodeL3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
602 DecodeL3RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
617 DecodeL2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
631 DecodeL2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
645 DecodeL6RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
665 DecodeL5RInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
679 DecodeL5RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
699 DecodeL4RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
718 DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
[all...] |
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/Disassembler/ |
| H A D | SparcDisassembler.cpp | 335 uint32_t Insn; local
313 readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn, bool IsLittleEndian) argument
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/Disassembler/ |
| H A D | MipsDisassembler.cpp | 1066 DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address, const void *Decoder) argument
1108 DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address, const void *Decoder) argument
1150 DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address, const void *Decoder) argument
1165 readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn, bool IsBigEndian) argument
1185 readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn, bool IsBigEndian, bool IsMicroMips) argument
1223 uint32_t Insn; local
1532 DecodeMem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1554 DecodeMemEVA(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1575 DecodeLoadByte15(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1593 DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1610 DecodeCacheOpMM(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1627 DecodePrefeOpMM(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1644 DecodeCacheeOp_CacheOpR6(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1661 DecodeSyncI(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1676 DecodeSyncI_MM(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1689 DecodeSynciR6(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1704 DecodeMSA128Mem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1750 DecodeMemMMImm4(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1808 DecodeMemMMSPImm5Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1824 DecodeMemMMGPImm7Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1840 DecodeMemMMReglistImm4Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1865 DecodeMemMMImm9(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1886 DecodeMemMMImm12(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1921 DecodeMemMMImm16(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1939 DecodeFMem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1957 DecodeFMemMMR2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1975 DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1993 DecodeFMem3(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2011 DecodeFMemCop2R6(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2029 DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2045 DecodeSpecial3LlSc(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2228 DecodeJumpTarget(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2304 DecodeJumpTargetMM(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2313 DecodeJumpTargetXMM(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2373 DecodeInsSize(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2386 DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2392 DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2398 DecodeSimm9SP(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2412 DecodeANDI16Imm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2451 DecodeRegListOperand16(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2475 DecodeMovePOperands(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2543 DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
[all...] |
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/ |
| H A D | AArch64Disassembler.cpp | 264 uint32_t Insn = local
840 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, argument
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/Disassembler/ |
| H A D | X86Disassembler.cpp | 1705 InternalInstruction Insn; local
[all...] |