| /freebsd-10-stable/contrib/llvm/lib/Transforms/IPO/ |
| H A D | IPConstantPropagation.cpp | 250 Instruction *Ins = cast<Instruction>(*I); local
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| H A D | PartialInlining.cpp | 93 BasicBlock::iterator Ins = newReturnBlock->begin(); local
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| /freebsd-10-stable/contrib/llvm/lib/CodeGen/ |
| H A D | CallingConvLower.cpp | 67 CCState::AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins, argument
155 void CCState::AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins, argument
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| H A D | RegAllocGreedy.cpp | 778 unsigned Ins = 0; local
783 BC.Entry = SpillPlacement::MustSpill, ++Ins; local
785 BC.Entry = SpillPlacement::PrefSpill, ++Ins; local
793 BC.Exit = SpillPlacement::MustSpill, ++Ins; local
795 BC.Exit = SpillPlacement::PrefSpill, ++Ins; local
989 unsigned Ins = 0; local
[all...] |
| /freebsd-10-stable/contrib/llvm/lib/Target/Hexagon/ |
| H A D | HexagonCallingConvLower.cpp | 180 Hexagon_CCState::AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins, argument
66 AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins, Hexagon_CCAssignFn Fn, unsigned SretValueInRegs) argument
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| H A D | HexagonISelLowering.cpp | 400 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; local
362 LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, const SmallVectorImpl<SDValue> &OutVals, SDValue Callee) const argument
824 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1682 IsEligibleForTailCallOptimization( SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, bool isCalleeStructRet, bool isCallerStructRet, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG& DAG) const argument
[all...] |
| /freebsd-10-stable/contrib/llvm/include/llvm/Transforms/Utils/ |
| H A D | SSAUpdaterImpl.h | 70 SSAUpdaterImpl(UpdaterT *U, AvailableValsTy *A, SmallVectorImpl<PhiT*> *Ins) argument
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| /freebsd-10-stable/contrib/llvm/lib/Target/PowerPC/ |
| H A D | PPCRegisterInfo.cpp | 800 MachineBasicBlock::iterator Ins = MBB->begin(); local
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| /freebsd-10-stable/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMBaseRegisterInfo.cpp | 575 MachineBasicBlock::iterator Ins = MBB->begin(); local
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| /freebsd-10-stable/contrib/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 401 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; local
274 AnalyzeVarArgs(CCState &State, const SmallVectorImpl<ISD::InputArg> &Ins) argument
349 AnalyzeRetResult(CCState &State, const SmallVectorImpl<ISD::InputArg> &Ins) argument
371 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
427 LowerCCCArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
578 LowerCCCCallTo(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
718 LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
[all...] |
| /freebsd-10-stable/contrib/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.h | 105 Ins, enumerator in enum:llvm::MipsISD::NodeType
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| H A D | MipsISelLowering.cpp | 2308 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; local
2512 LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, const SDNode *CallNode, const Type *RetTy) const argument
2550 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
3333 analyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins, bool IsSoftFloat, const SDNode *CallNode, const Type *RetTy) const argument
[all...] |
| /freebsd-10-stable/contrib/llvm/lib/Target/R600/ |
| H A D | AMDGPUISelLowering.cpp | 735 getOriginalFunctionArgs( SelectionDAG &DAG, const Function *F, const SmallVectorImpl<ISD::InputArg> &Ins, SmallVectorImpl<ISD::InputArg> &OrigIns) const argument
[all...] |
| H A D | SIISelLowering.cpp | 182 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
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| H A D | R600ISelLowering.cpp | 1338 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
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| /freebsd-10-stable/contrib/llvm/utils/TableGen/ |
| H A D | CodeGenRegisters.h | 82 std::pair<CompMap::iterator, bool> Ins = local
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| H A D | CodeGenRegisters.cpp | 327 DenseMap<const CodeGenRegister*, CodeGenSubRegIndex*>::iterator Ins = local
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| /freebsd-10-stable/contrib/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 525 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; local
1385 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
[all...] |
| /freebsd-10-stable/contrib/llvm/lib/Target/X86/ |
| H A D | X86FastISel.cpp | 2233 SmallVector<ISD::InputArg, 32> Ins; local
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| /freebsd-10-stable/contrib/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.cpp | 883 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; local
910 LowerCCCCallTo(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1036 LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1070 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1094 LowerCCCArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
[all...] |
| /freebsd-10-stable/contrib/llvm/include/llvm/TableGen/ |
| H A D | Record.h | 1672 bool Ins = Classes.insert(std::make_pair(R->getName(), R)).second; local
1677 bool Ins = Defs.insert(std::make_pair(R->getName(), R)).second; local
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| /freebsd-10-stable/contrib/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 688 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; local
321 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
339 LowerFormalArguments_32(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
539 LowerFormalArguments_64(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
[all...] |
| /freebsd-10-stable/contrib/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 777 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; local
636 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
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| /freebsd-10-stable/contrib/llvm/lib/Transforms/Instrumentation/ |
| H A D | AddressSanitizer.cpp | 1197 Instruction *Ins = SplitBlockAndInsertIfThen(cast<Instruction>(Cmp), false); local
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| /freebsd-10-stable/contrib/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1325 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; local
1131 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1583 LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1628 IsEligibleForTailCallOptimization(SDValue Callee, CallingConv::ID CalleeCC, bool IsVarArg, bool IsCalleeStructRet, bool IsCallerStructRet, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG& DAG) const argument
[all...] |