1234353Sdim//===-- XCoreISelLowering.cpp - XCore DAG Lowering Implementation ---------===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This file implements the XCoreTargetLowering class. 11193323Sed// 12193323Sed//===----------------------------------------------------------------------===// 13193323Sed 14193323Sed#define DEBUG_TYPE "xcore-lower" 15193323Sed 16193323Sed#include "XCoreISelLowering.h" 17249423Sdim#include "XCore.h" 18193323Sed#include "XCoreMachineFunctionInfo.h" 19249423Sdim#include "XCoreSubtarget.h" 20249423Sdim#include "XCoreTargetMachine.h" 21198090Srdivacky#include "XCoreTargetObjectFile.h" 22193323Sed#include "llvm/CodeGen/CallingConvLower.h" 23193323Sed#include "llvm/CodeGen/MachineFrameInfo.h" 24193323Sed#include "llvm/CodeGen/MachineFunction.h" 25193323Sed#include "llvm/CodeGen/MachineInstrBuilder.h" 26204642Srdivacky#include "llvm/CodeGen/MachineJumpTableInfo.h" 27193323Sed#include "llvm/CodeGen/MachineRegisterInfo.h" 28193323Sed#include "llvm/CodeGen/SelectionDAGISel.h" 29193323Sed#include "llvm/CodeGen/ValueTypes.h" 30249423Sdim#include "llvm/IR/CallingConv.h" 31249423Sdim#include "llvm/IR/DerivedTypes.h" 32249423Sdim#include "llvm/IR/Function.h" 33249423Sdim#include "llvm/IR/GlobalAlias.h" 34249423Sdim#include "llvm/IR/GlobalVariable.h" 35249423Sdim#include "llvm/IR/Intrinsics.h" 36193323Sed#include "llvm/Support/Debug.h" 37198090Srdivacky#include "llvm/Support/ErrorHandling.h" 38198090Srdivacky#include "llvm/Support/raw_ostream.h" 39251662Sdim#include <algorithm> 40251662Sdim 41193323Sedusing namespace llvm; 42193323Sed 43193323Sedconst char *XCoreTargetLowering:: 44219077SdimgetTargetNodeName(unsigned Opcode) const 45193323Sed{ 46219077Sdim switch (Opcode) 47193323Sed { 48193323Sed case XCoreISD::BL : return "XCoreISD::BL"; 49193323Sed case XCoreISD::PCRelativeWrapper : return "XCoreISD::PCRelativeWrapper"; 50193323Sed case XCoreISD::DPRelativeWrapper : return "XCoreISD::DPRelativeWrapper"; 51193323Sed case XCoreISD::CPRelativeWrapper : return "XCoreISD::CPRelativeWrapper"; 52193323Sed case XCoreISD::STWSP : return "XCoreISD::STWSP"; 53193323Sed case XCoreISD::RETSP : return "XCoreISD::RETSP"; 54198090Srdivacky case XCoreISD::LADD : return "XCoreISD::LADD"; 55198090Srdivacky case XCoreISD::LSUB : return "XCoreISD::LSUB"; 56204961Srdivacky case XCoreISD::LMUL : return "XCoreISD::LMUL"; 57204961Srdivacky case XCoreISD::MACCU : return "XCoreISD::MACCU"; 58204961Srdivacky case XCoreISD::MACCS : return "XCoreISD::MACCS"; 59249423Sdim case XCoreISD::CRC8 : return "XCoreISD::CRC8"; 60204642Srdivacky case XCoreISD::BR_JT : return "XCoreISD::BR_JT"; 61204642Srdivacky case XCoreISD::BR_JT32 : return "XCoreISD::BR_JT32"; 62263508Sdim case XCoreISD::MEMBARRIER : return "XCoreISD::MEMBARRIER"; 63204961Srdivacky default : return NULL; 64193323Sed } 65193323Sed} 66193323Sed 67193323SedXCoreTargetLowering::XCoreTargetLowering(XCoreTargetMachine &XTM) 68198090Srdivacky : TargetLowering(XTM, new XCoreTargetObjectFile()), 69193323Sed TM(XTM), 70193323Sed Subtarget(*XTM.getSubtargetImpl()) { 71193323Sed 72193323Sed // Set up the register classes. 73239462Sdim addRegisterClass(MVT::i32, &XCore::GRRegsRegClass); 74193323Sed 75193323Sed // Compute derived properties from the register classes 76193323Sed computeRegisterProperties(); 77193323Sed 78193323Sed // Division is expensive 79193323Sed setIntDivIsCheap(false); 80193323Sed 81193323Sed setStackPointerRegisterToSaveRestore(XCore::SP); 82193323Sed 83263508Sdim setSchedulingPreference(Sched::Source); 84193323Sed 85193323Sed // Use i32 for setcc operations results (slt, sgt, ...). 86193323Sed setBooleanContents(ZeroOrOneBooleanContent); 87226633Sdim setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct? 88193323Sed 89193323Sed // XCore does not have the NodeTypes below. 90249423Sdim setOperationAction(ISD::BR_CC, MVT::i32, Expand); 91193323Sed setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 92193323Sed setOperationAction(ISD::ADDC, MVT::i32, Expand); 93193323Sed setOperationAction(ISD::ADDE, MVT::i32, Expand); 94193323Sed setOperationAction(ISD::SUBC, MVT::i32, Expand); 95193323Sed setOperationAction(ISD::SUBE, MVT::i32, Expand); 96193323Sed 97193323Sed // Stop the combiner recombining select and set_cc 98193323Sed setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); 99219077Sdim 100193323Sed // 64bit 101198090Srdivacky setOperationAction(ISD::ADD, MVT::i64, Custom); 102198090Srdivacky setOperationAction(ISD::SUB, MVT::i64, Custom); 103204961Srdivacky setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom); 104204961Srdivacky setOperationAction(ISD::UMUL_LOHI, MVT::i32, Custom); 105193323Sed setOperationAction(ISD::MULHS, MVT::i32, Expand); 106193323Sed setOperationAction(ISD::MULHU, MVT::i32, Expand); 107193323Sed setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 108193323Sed setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 109193323Sed setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 110219077Sdim 111193323Sed // Bit Manipulation 112193323Sed setOperationAction(ISD::CTPOP, MVT::i32, Expand); 113193323Sed setOperationAction(ISD::ROTL , MVT::i32, Expand); 114193323Sed setOperationAction(ISD::ROTR , MVT::i32, Expand); 115234353Sdim setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand); 116234353Sdim setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand); 117219077Sdim 118193323Sed setOperationAction(ISD::TRAP, MVT::Other, Legal); 119219077Sdim 120204642Srdivacky // Jump tables. 121204642Srdivacky setOperationAction(ISD::BR_JT, MVT::Other, Custom); 122193323Sed 123193323Sed setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 124199511Srdivacky setOperationAction(ISD::BlockAddress, MVT::i32 , Custom); 125199511Srdivacky 126193323Sed // Conversion of i64 -> double produces constantpool nodes 127193323Sed setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 128193323Sed 129193323Sed // Loads 130193323Sed setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 131193323Sed setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 132193323Sed setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 133193323Sed 134193323Sed setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand); 135193323Sed setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Expand); 136198090Srdivacky 137198090Srdivacky // Custom expand misaligned loads / stores. 138198090Srdivacky setOperationAction(ISD::LOAD, MVT::i32, Custom); 139198090Srdivacky setOperationAction(ISD::STORE, MVT::i32, Custom); 140198090Srdivacky 141193323Sed // Varargs 142193323Sed setOperationAction(ISD::VAEND, MVT::Other, Expand); 143193323Sed setOperationAction(ISD::VACOPY, MVT::Other, Expand); 144193323Sed setOperationAction(ISD::VAARG, MVT::Other, Custom); 145193323Sed setOperationAction(ISD::VASTART, MVT::Other, Custom); 146219077Sdim 147193323Sed // Dynamic stack 148193323Sed setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 149193323Sed setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 150193323Sed setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 151198090Srdivacky 152263508Sdim // Exception handling 153263508Sdim setExceptionPointerRegister(XCore::R0); 154263508Sdim setExceptionSelectorRegister(XCore::R1); 155263508Sdim 156263508Sdim // Atomic operations 157263508Sdim setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom); 158263508Sdim 159218893Sdim // TRAMPOLINE is custom lowered. 160226633Sdim setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom); 161226633Sdim setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom); 162218893Sdim 163249423Sdim // We want to custom lower some of our intrinsics. 164249423Sdim setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 165218893Sdim 166249423Sdim MaxStoresPerMemset = MaxStoresPerMemsetOptSize = 4; 167249423Sdim MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize 168249423Sdim = MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = 2; 169249423Sdim 170198090Srdivacky // We have target-specific dag combine patterns for the following nodes: 171198090Srdivacky setTargetDAGCombine(ISD::STORE); 172204961Srdivacky setTargetDAGCombine(ISD::ADD); 173223017Sdim 174223017Sdim setMinFunctionAlignment(1); 175193323Sed} 176193323Sed 177263508Sdimbool XCoreTargetLowering::isZExtFree(SDValue Val, EVT VT2) const { 178263508Sdim if (Val.getOpcode() != ISD::LOAD) 179263508Sdim return false; 180263508Sdim 181263508Sdim EVT VT1 = Val.getValueType(); 182263508Sdim if (!VT1.isSimple() || !VT1.isInteger() || 183263508Sdim !VT2.isSimple() || !VT2.isInteger()) 184263508Sdim return false; 185263508Sdim 186263508Sdim switch (VT1.getSimpleVT().SimpleTy) { 187263508Sdim default: break; 188263508Sdim case MVT::i8: 189263508Sdim return true; 190263508Sdim } 191263508Sdim 192263508Sdim return false; 193263508Sdim} 194263508Sdim 195193323SedSDValue XCoreTargetLowering:: 196207618SrdivackyLowerOperation(SDValue Op, SelectionDAG &DAG) const { 197219077Sdim switch (Op.getOpcode()) 198193323Sed { 199249423Sdim case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 200249423Sdim case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 201249423Sdim case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 202249423Sdim case ISD::BR_JT: return LowerBR_JT(Op, DAG); 203249423Sdim case ISD::LOAD: return LowerLOAD(Op, DAG); 204249423Sdim case ISD::STORE: return LowerSTORE(Op, DAG); 205249423Sdim case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 206249423Sdim case ISD::VAARG: return LowerVAARG(Op, DAG); 207249423Sdim case ISD::VASTART: return LowerVASTART(Op, DAG); 208249423Sdim case ISD::SMUL_LOHI: return LowerSMUL_LOHI(Op, DAG); 209249423Sdim case ISD::UMUL_LOHI: return LowerUMUL_LOHI(Op, DAG); 210193323Sed // FIXME: Remove these when LegalizeDAGTypes lands. 211193323Sed case ISD::ADD: 212249423Sdim case ISD::SUB: return ExpandADDSUB(Op.getNode(), DAG); 213249423Sdim case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 214249423Sdim case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG); 215249423Sdim case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG); 216249423Sdim case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 217263508Sdim case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG); 218193323Sed default: 219198090Srdivacky llvm_unreachable("unimplemented operand"); 220193323Sed } 221193323Sed} 222193323Sed 223193323Sed/// ReplaceNodeResults - Replace the results of node with an illegal result 224193323Sed/// type with new values built out of custom code. 225193323Sedvoid XCoreTargetLowering::ReplaceNodeResults(SDNode *N, 226193323Sed SmallVectorImpl<SDValue>&Results, 227207618Srdivacky SelectionDAG &DAG) const { 228193323Sed switch (N->getOpcode()) { 229193323Sed default: 230198090Srdivacky llvm_unreachable("Don't know how to custom expand this!"); 231193323Sed case ISD::ADD: 232193323Sed case ISD::SUB: 233193323Sed Results.push_back(ExpandADDSUB(N, DAG)); 234193323Sed return; 235193323Sed } 236193323Sed} 237193323Sed 238193323Sed//===----------------------------------------------------------------------===// 239193323Sed// Misc Lower Operation implementation 240193323Sed//===----------------------------------------------------------------------===// 241193323Sed 242193323SedSDValue XCoreTargetLowering:: 243207618SrdivackyLowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const 244193323Sed{ 245263508Sdim SDLoc dl(Op); 246193323Sed SDValue Cond = DAG.getNode(ISD::SETCC, dl, MVT::i32, Op.getOperand(2), 247193323Sed Op.getOperand(3), Op.getOperand(4)); 248193323Sed return DAG.getNode(ISD::SELECT, dl, MVT::i32, Cond, Op.getOperand(0), 249193323Sed Op.getOperand(1)); 250193323Sed} 251193323Sed 252193323SedSDValue XCoreTargetLowering:: 253207618SrdivackygetGlobalAddressWrapper(SDValue GA, const GlobalValue *GV, 254207618Srdivacky SelectionDAG &DAG) const 255193323Sed{ 256193323Sed // FIXME there is no actual debug info here 257263508Sdim SDLoc dl(GA); 258249423Sdim const GlobalValue *UnderlyingGV = GV; 259249423Sdim // If GV is an alias then use the aliasee to determine the wrapper type 260249423Sdim if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 261249423Sdim UnderlyingGV = GA->resolveAliasedGlobal(); 262249423Sdim if (const GlobalVariable *GVar = dyn_cast<GlobalVariable>(UnderlyingGV)) { 263249423Sdim if (GVar->isConstant()) 264249423Sdim return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, GA); 265249423Sdim return DAG.getNode(XCoreISD::DPRelativeWrapper, dl, MVT::i32, GA); 266193323Sed } 267249423Sdim return DAG.getNode(XCoreISD::PCRelativeWrapper, dl, MVT::i32, GA); 268193323Sed} 269193323Sed 270193323SedSDValue XCoreTargetLowering:: 271207618SrdivackyLowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const 272193323Sed{ 273263508Sdim SDLoc DL(Op); 274251662Sdim const GlobalAddressSDNode *GN = cast<GlobalAddressSDNode>(Op); 275251662Sdim const GlobalValue *GV = GN->getGlobal(); 276251662Sdim int64_t Offset = GN->getOffset(); 277251662Sdim // We can only fold positive offsets that are a multiple of the word size. 278251662Sdim int64_t FoldedOffset = std::max(Offset & ~3, (int64_t)0); 279251662Sdim SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i32, FoldedOffset); 280251662Sdim GA = getGlobalAddressWrapper(GA, GV, DAG); 281251662Sdim // Handle the rest of the offset. 282251662Sdim if (Offset != FoldedOffset) { 283251662Sdim SDValue Remaining = DAG.getConstant(Offset - FoldedOffset, MVT::i32); 284251662Sdim GA = DAG.getNode(ISD::ADD, DL, MVT::i32, GA, Remaining); 285251662Sdim } 286251662Sdim return GA; 287193323Sed} 288193323Sed 289193323SedSDValue XCoreTargetLowering:: 290207618SrdivackyLowerBlockAddress(SDValue Op, SelectionDAG &DAG) const 291199511Srdivacky{ 292263508Sdim SDLoc DL(Op); 293199511Srdivacky 294207618Srdivacky const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 295243830Sdim SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy()); 296199511Srdivacky 297199511Srdivacky return DAG.getNode(XCoreISD::PCRelativeWrapper, DL, getPointerTy(), Result); 298199511Srdivacky} 299199511Srdivacky 300199511SrdivackySDValue XCoreTargetLowering:: 301207618SrdivackyLowerConstantPool(SDValue Op, SelectionDAG &DAG) const 302193323Sed{ 303193323Sed ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 304193323Sed // FIXME there isn't really debug info here 305263508Sdim SDLoc dl(CP); 306198090Srdivacky EVT PtrVT = Op.getValueType(); 307198090Srdivacky SDValue Res; 308198090Srdivacky if (CP->isMachineConstantPoolEntry()) { 309198090Srdivacky Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT, 310198090Srdivacky CP->getAlignment()); 311193323Sed } else { 312198090Srdivacky Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, 313198090Srdivacky CP->getAlignment()); 314193323Sed } 315198090Srdivacky return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, Res); 316193323Sed} 317193323Sed 318205218Srdivackyunsigned XCoreTargetLowering::getJumpTableEncoding() const { 319205218Srdivacky return MachineJumpTableInfo::EK_Inline; 320205218Srdivacky} 321205218Srdivacky 322193323SedSDValue XCoreTargetLowering:: 323207618SrdivackyLowerBR_JT(SDValue Op, SelectionDAG &DAG) const 324193323Sed{ 325204642Srdivacky SDValue Chain = Op.getOperand(0); 326204642Srdivacky SDValue Table = Op.getOperand(1); 327204642Srdivacky SDValue Index = Op.getOperand(2); 328263508Sdim SDLoc dl(Op); 329204642Srdivacky JumpTableSDNode *JT = cast<JumpTableSDNode>(Table); 330204642Srdivacky unsigned JTI = JT->getIndex(); 331204642Srdivacky MachineFunction &MF = DAG.getMachineFunction(); 332204642Srdivacky const MachineJumpTableInfo *MJTI = MF.getJumpTableInfo(); 333204642Srdivacky SDValue TargetJT = DAG.getTargetJumpTable(JT->getIndex(), MVT::i32); 334204642Srdivacky 335204642Srdivacky unsigned NumEntries = MJTI->getJumpTables()[JTI].MBBs.size(); 336204642Srdivacky if (NumEntries <= 32) { 337204642Srdivacky return DAG.getNode(XCoreISD::BR_JT, dl, MVT::Other, Chain, TargetJT, Index); 338204642Srdivacky } 339204642Srdivacky assert((NumEntries >> 31) == 0); 340204642Srdivacky SDValue ScaledIndex = DAG.getNode(ISD::SHL, dl, MVT::i32, Index, 341204642Srdivacky DAG.getConstant(1, MVT::i32)); 342204642Srdivacky return DAG.getNode(XCoreISD::BR_JT32, dl, MVT::Other, Chain, TargetJT, 343204642Srdivacky ScaledIndex); 344193323Sed} 345193323Sed 346251662SdimSDValue XCoreTargetLowering:: 347263508SdimlowerLoadWordFromAlignedBasePlusOffset(SDLoc DL, SDValue Chain, SDValue Base, 348251662Sdim int64_t Offset, SelectionDAG &DAG) const 349198090Srdivacky{ 350251662Sdim if ((Offset & 0x3) == 0) { 351251662Sdim return DAG.getLoad(getPointerTy(), DL, Chain, Base, MachinePointerInfo(), 352251662Sdim false, false, false, 0); 353198090Srdivacky } 354251662Sdim // Lower to pair of consecutive word aligned loads plus some bit shifting. 355251662Sdim int32_t HighOffset = RoundUpToAlignment(Offset, 4); 356251662Sdim int32_t LowOffset = HighOffset - 4; 357251662Sdim SDValue LowAddr, HighAddr; 358251662Sdim if (GlobalAddressSDNode *GASD = 359251662Sdim dyn_cast<GlobalAddressSDNode>(Base.getNode())) { 360251662Sdim LowAddr = DAG.getGlobalAddress(GASD->getGlobal(), DL, Base.getValueType(), 361251662Sdim LowOffset); 362251662Sdim HighAddr = DAG.getGlobalAddress(GASD->getGlobal(), DL, Base.getValueType(), 363251662Sdim HighOffset); 364251662Sdim } else { 365251662Sdim LowAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, Base, 366251662Sdim DAG.getConstant(LowOffset, MVT::i32)); 367251662Sdim HighAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, Base, 368251662Sdim DAG.getConstant(HighOffset, MVT::i32)); 369198090Srdivacky } 370251662Sdim SDValue LowShift = DAG.getConstant((Offset - LowOffset) * 8, MVT::i32); 371251662Sdim SDValue HighShift = DAG.getConstant((HighOffset - Offset) * 8, MVT::i32); 372251662Sdim 373251662Sdim SDValue Low = DAG.getLoad(getPointerTy(), DL, Chain, 374251662Sdim LowAddr, MachinePointerInfo(), 375251662Sdim false, false, false, 0); 376251662Sdim SDValue High = DAG.getLoad(getPointerTy(), DL, Chain, 377251662Sdim HighAddr, MachinePointerInfo(), 378251662Sdim false, false, false, 0); 379251662Sdim SDValue LowShifted = DAG.getNode(ISD::SRL, DL, MVT::i32, Low, LowShift); 380251662Sdim SDValue HighShifted = DAG.getNode(ISD::SHL, DL, MVT::i32, High, HighShift); 381251662Sdim SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, LowShifted, HighShifted); 382251662Sdim Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Low.getValue(1), 383251662Sdim High.getValue(1)); 384251662Sdim SDValue Ops[] = { Result, Chain }; 385251662Sdim return DAG.getMergeValues(Ops, 2, DL); 386198090Srdivacky} 387198090Srdivacky 388251662Sdimstatic bool isWordAligned(SDValue Value, SelectionDAG &DAG) 389251662Sdim{ 390251662Sdim APInt KnownZero, KnownOne; 391251662Sdim DAG.ComputeMaskedBits(Value, KnownZero, KnownOne); 392251662Sdim return KnownZero.countTrailingOnes() >= 2; 393251662Sdim} 394251662Sdim 395193323SedSDValue XCoreTargetLowering:: 396218893SdimLowerLOAD(SDValue Op, SelectionDAG &DAG) const { 397251662Sdim const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 398198090Srdivacky LoadSDNode *LD = cast<LoadSDNode>(Op); 399198090Srdivacky assert(LD->getExtensionType() == ISD::NON_EXTLOAD && 400198090Srdivacky "Unexpected extension type"); 401198090Srdivacky assert(LD->getMemoryVT() == MVT::i32 && "Unexpected load EVT"); 402218893Sdim if (allowsUnalignedMemoryAccesses(LD->getMemoryVT())) 403198090Srdivacky return SDValue(); 404218893Sdim 405243830Sdim unsigned ABIAlignment = getDataLayout()-> 406198090Srdivacky getABITypeAlignment(LD->getMemoryVT().getTypeForEVT(*DAG.getContext())); 407198090Srdivacky // Leave aligned load alone. 408218893Sdim if (LD->getAlignment() >= ABIAlignment) 409198090Srdivacky return SDValue(); 410218893Sdim 411198090Srdivacky SDValue Chain = LD->getChain(); 412198090Srdivacky SDValue BasePtr = LD->getBasePtr(); 413263508Sdim SDLoc DL(Op); 414219077Sdim 415251662Sdim if (!LD->isVolatile()) { 416251662Sdim const GlobalValue *GV; 417251662Sdim int64_t Offset = 0; 418251662Sdim if (DAG.isBaseWithConstantOffset(BasePtr) && 419251662Sdim isWordAligned(BasePtr->getOperand(0), DAG)) { 420251662Sdim SDValue NewBasePtr = BasePtr->getOperand(0); 421251662Sdim Offset = cast<ConstantSDNode>(BasePtr->getOperand(1))->getSExtValue(); 422251662Sdim return lowerLoadWordFromAlignedBasePlusOffset(DL, Chain, NewBasePtr, 423251662Sdim Offset, DAG); 424198090Srdivacky } 425251662Sdim if (TLI.isGAPlusOffset(BasePtr.getNode(), GV, Offset) && 426251662Sdim MinAlign(GV->getAlignment(), 4) == 4) { 427251662Sdim SDValue NewBasePtr = DAG.getGlobalAddress(GV, DL, 428251662Sdim BasePtr->getValueType(0)); 429251662Sdim return lowerLoadWordFromAlignedBasePlusOffset(DL, Chain, NewBasePtr, 430251662Sdim Offset, DAG); 431251662Sdim } 432198090Srdivacky } 433219077Sdim 434198090Srdivacky if (LD->getAlignment() == 2) { 435218893Sdim SDValue Low = DAG.getExtLoad(ISD::ZEXTLOAD, DL, MVT::i32, Chain, 436218893Sdim BasePtr, LD->getPointerInfo(), MVT::i16, 437203954Srdivacky LD->isVolatile(), LD->isNonTemporal(), 2); 438218893Sdim SDValue HighAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, 439198090Srdivacky DAG.getConstant(2, MVT::i32)); 440218893Sdim SDValue High = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain, 441218893Sdim HighAddr, 442218893Sdim LD->getPointerInfo().getWithOffset(2), 443203954Srdivacky MVT::i16, LD->isVolatile(), 444203954Srdivacky LD->isNonTemporal(), 2); 445218893Sdim SDValue HighShifted = DAG.getNode(ISD::SHL, DL, MVT::i32, High, 446198090Srdivacky DAG.getConstant(16, MVT::i32)); 447218893Sdim SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Low, HighShifted); 448218893Sdim Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Low.getValue(1), 449198090Srdivacky High.getValue(1)); 450198090Srdivacky SDValue Ops[] = { Result, Chain }; 451218893Sdim return DAG.getMergeValues(Ops, 2, DL); 452198090Srdivacky } 453219077Sdim 454198090Srdivacky // Lower to a call to __misaligned_load(BasePtr). 455243830Sdim Type *IntPtrTy = getDataLayout()->getIntPtrType(*DAG.getContext()); 456198090Srdivacky TargetLowering::ArgListTy Args; 457198090Srdivacky TargetLowering::ArgListEntry Entry; 458219077Sdim 459198090Srdivacky Entry.Ty = IntPtrTy; 460198090Srdivacky Entry.Node = BasePtr; 461198090Srdivacky Args.push_back(Entry); 462219077Sdim 463239462Sdim TargetLowering::CallLoweringInfo CLI(Chain, IntPtrTy, false, false, 464234353Sdim false, false, 0, CallingConv::C, /*isTailCall=*/false, 465234353Sdim /*doesNotRet=*/false, /*isReturnValueUsed=*/true, 466198090Srdivacky DAG.getExternalSymbol("__misaligned_load", getPointerTy()), 467218893Sdim Args, DAG, DL); 468239462Sdim std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); 469198090Srdivacky 470198090Srdivacky SDValue Ops[] = 471198090Srdivacky { CallResult.first, CallResult.second }; 472198090Srdivacky 473218893Sdim return DAG.getMergeValues(Ops, 2, DL); 474198090Srdivacky} 475198090Srdivacky 476198090SrdivackySDValue XCoreTargetLowering:: 477207618SrdivackyLowerSTORE(SDValue Op, SelectionDAG &DAG) const 478198090Srdivacky{ 479198090Srdivacky StoreSDNode *ST = cast<StoreSDNode>(Op); 480198090Srdivacky assert(!ST->isTruncatingStore() && "Unexpected store type"); 481198090Srdivacky assert(ST->getMemoryVT() == MVT::i32 && "Unexpected store EVT"); 482198090Srdivacky if (allowsUnalignedMemoryAccesses(ST->getMemoryVT())) { 483198090Srdivacky return SDValue(); 484198090Srdivacky } 485243830Sdim unsigned ABIAlignment = getDataLayout()-> 486198090Srdivacky getABITypeAlignment(ST->getMemoryVT().getTypeForEVT(*DAG.getContext())); 487198090Srdivacky // Leave aligned store alone. 488198090Srdivacky if (ST->getAlignment() >= ABIAlignment) { 489198090Srdivacky return SDValue(); 490198090Srdivacky } 491198090Srdivacky SDValue Chain = ST->getChain(); 492198090Srdivacky SDValue BasePtr = ST->getBasePtr(); 493198090Srdivacky SDValue Value = ST->getValue(); 494263508Sdim SDLoc dl(Op); 495219077Sdim 496198090Srdivacky if (ST->getAlignment() == 2) { 497198090Srdivacky SDValue Low = Value; 498198090Srdivacky SDValue High = DAG.getNode(ISD::SRL, dl, MVT::i32, Value, 499198090Srdivacky DAG.getConstant(16, MVT::i32)); 500198090Srdivacky SDValue StoreLow = DAG.getTruncStore(Chain, dl, Low, BasePtr, 501218893Sdim ST->getPointerInfo(), MVT::i16, 502203954Srdivacky ST->isVolatile(), ST->isNonTemporal(), 503203954Srdivacky 2); 504198090Srdivacky SDValue HighAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, BasePtr, 505198090Srdivacky DAG.getConstant(2, MVT::i32)); 506198090Srdivacky SDValue StoreHigh = DAG.getTruncStore(Chain, dl, High, HighAddr, 507218893Sdim ST->getPointerInfo().getWithOffset(2), 508203954Srdivacky MVT::i16, ST->isVolatile(), 509203954Srdivacky ST->isNonTemporal(), 2); 510198090Srdivacky return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, StoreLow, StoreHigh); 511198090Srdivacky } 512219077Sdim 513198090Srdivacky // Lower to a call to __misaligned_store(BasePtr, Value). 514243830Sdim Type *IntPtrTy = getDataLayout()->getIntPtrType(*DAG.getContext()); 515198090Srdivacky TargetLowering::ArgListTy Args; 516198090Srdivacky TargetLowering::ArgListEntry Entry; 517219077Sdim 518198090Srdivacky Entry.Ty = IntPtrTy; 519198090Srdivacky Entry.Node = BasePtr; 520198090Srdivacky Args.push_back(Entry); 521219077Sdim 522198090Srdivacky Entry.Node = Value; 523198090Srdivacky Args.push_back(Entry); 524219077Sdim 525239462Sdim TargetLowering::CallLoweringInfo CLI(Chain, 526239462Sdim Type::getVoidTy(*DAG.getContext()), false, false, 527234353Sdim false, false, 0, CallingConv::C, /*isTailCall=*/false, 528234353Sdim /*doesNotRet=*/false, /*isReturnValueUsed=*/true, 529198090Srdivacky DAG.getExternalSymbol("__misaligned_store", getPointerTy()), 530204642Srdivacky Args, DAG, dl); 531239462Sdim std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); 532198090Srdivacky 533198090Srdivacky return CallResult.second; 534198090Srdivacky} 535198090Srdivacky 536198090SrdivackySDValue XCoreTargetLowering:: 537207618SrdivackyLowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const 538204961Srdivacky{ 539204961Srdivacky assert(Op.getValueType() == MVT::i32 && Op.getOpcode() == ISD::SMUL_LOHI && 540204961Srdivacky "Unexpected operand to lower!"); 541263508Sdim SDLoc dl(Op); 542204961Srdivacky SDValue LHS = Op.getOperand(0); 543204961Srdivacky SDValue RHS = Op.getOperand(1); 544204961Srdivacky SDValue Zero = DAG.getConstant(0, MVT::i32); 545204961Srdivacky SDValue Hi = DAG.getNode(XCoreISD::MACCS, dl, 546204961Srdivacky DAG.getVTList(MVT::i32, MVT::i32), Zero, Zero, 547204961Srdivacky LHS, RHS); 548204961Srdivacky SDValue Lo(Hi.getNode(), 1); 549204961Srdivacky SDValue Ops[] = { Lo, Hi }; 550204961Srdivacky return DAG.getMergeValues(Ops, 2, dl); 551204961Srdivacky} 552204961Srdivacky 553204961SrdivackySDValue XCoreTargetLowering:: 554207618SrdivackyLowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const 555204961Srdivacky{ 556204961Srdivacky assert(Op.getValueType() == MVT::i32 && Op.getOpcode() == ISD::UMUL_LOHI && 557204961Srdivacky "Unexpected operand to lower!"); 558263508Sdim SDLoc dl(Op); 559204961Srdivacky SDValue LHS = Op.getOperand(0); 560204961Srdivacky SDValue RHS = Op.getOperand(1); 561204961Srdivacky SDValue Zero = DAG.getConstant(0, MVT::i32); 562204961Srdivacky SDValue Hi = DAG.getNode(XCoreISD::LMUL, dl, 563204961Srdivacky DAG.getVTList(MVT::i32, MVT::i32), LHS, RHS, 564204961Srdivacky Zero, Zero); 565204961Srdivacky SDValue Lo(Hi.getNode(), 1); 566204961Srdivacky SDValue Ops[] = { Lo, Hi }; 567204961Srdivacky return DAG.getMergeValues(Ops, 2, dl); 568204961Srdivacky} 569204961Srdivacky 570204961Srdivacky/// isADDADDMUL - Return whether Op is in a form that is equivalent to 571204961Srdivacky/// add(add(mul(x,y),a),b). If requireIntermediatesHaveOneUse is true then 572204961Srdivacky/// each intermediate result in the calculation must also have a single use. 573204961Srdivacky/// If the Op is in the correct form the constituent parts are written to Mul0, 574204961Srdivacky/// Mul1, Addend0 and Addend1. 575204961Srdivackystatic bool 576204961SrdivackyisADDADDMUL(SDValue Op, SDValue &Mul0, SDValue &Mul1, SDValue &Addend0, 577204961Srdivacky SDValue &Addend1, bool requireIntermediatesHaveOneUse) 578204961Srdivacky{ 579204961Srdivacky if (Op.getOpcode() != ISD::ADD) 580204961Srdivacky return false; 581204961Srdivacky SDValue N0 = Op.getOperand(0); 582204961Srdivacky SDValue N1 = Op.getOperand(1); 583204961Srdivacky SDValue AddOp; 584204961Srdivacky SDValue OtherOp; 585204961Srdivacky if (N0.getOpcode() == ISD::ADD) { 586204961Srdivacky AddOp = N0; 587204961Srdivacky OtherOp = N1; 588204961Srdivacky } else if (N1.getOpcode() == ISD::ADD) { 589204961Srdivacky AddOp = N1; 590204961Srdivacky OtherOp = N0; 591204961Srdivacky } else { 592204961Srdivacky return false; 593204961Srdivacky } 594204961Srdivacky if (requireIntermediatesHaveOneUse && !AddOp.hasOneUse()) 595204961Srdivacky return false; 596204961Srdivacky if (OtherOp.getOpcode() == ISD::MUL) { 597204961Srdivacky // add(add(a,b),mul(x,y)) 598204961Srdivacky if (requireIntermediatesHaveOneUse && !OtherOp.hasOneUse()) 599204961Srdivacky return false; 600204961Srdivacky Mul0 = OtherOp.getOperand(0); 601204961Srdivacky Mul1 = OtherOp.getOperand(1); 602204961Srdivacky Addend0 = AddOp.getOperand(0); 603204961Srdivacky Addend1 = AddOp.getOperand(1); 604204961Srdivacky return true; 605204961Srdivacky } 606204961Srdivacky if (AddOp.getOperand(0).getOpcode() == ISD::MUL) { 607204961Srdivacky // add(add(mul(x,y),a),b) 608204961Srdivacky if (requireIntermediatesHaveOneUse && !AddOp.getOperand(0).hasOneUse()) 609204961Srdivacky return false; 610204961Srdivacky Mul0 = AddOp.getOperand(0).getOperand(0); 611204961Srdivacky Mul1 = AddOp.getOperand(0).getOperand(1); 612204961Srdivacky Addend0 = AddOp.getOperand(1); 613204961Srdivacky Addend1 = OtherOp; 614204961Srdivacky return true; 615204961Srdivacky } 616204961Srdivacky if (AddOp.getOperand(1).getOpcode() == ISD::MUL) { 617204961Srdivacky // add(add(a,mul(x,y)),b) 618204961Srdivacky if (requireIntermediatesHaveOneUse && !AddOp.getOperand(1).hasOneUse()) 619204961Srdivacky return false; 620204961Srdivacky Mul0 = AddOp.getOperand(1).getOperand(0); 621204961Srdivacky Mul1 = AddOp.getOperand(1).getOperand(1); 622204961Srdivacky Addend0 = AddOp.getOperand(0); 623204961Srdivacky Addend1 = OtherOp; 624204961Srdivacky return true; 625204961Srdivacky } 626204961Srdivacky return false; 627204961Srdivacky} 628204961Srdivacky 629204961SrdivackySDValue XCoreTargetLowering:: 630207618SrdivackyTryExpandADDWithMul(SDNode *N, SelectionDAG &DAG) const 631204961Srdivacky{ 632204961Srdivacky SDValue Mul; 633204961Srdivacky SDValue Other; 634204961Srdivacky if (N->getOperand(0).getOpcode() == ISD::MUL) { 635204961Srdivacky Mul = N->getOperand(0); 636204961Srdivacky Other = N->getOperand(1); 637204961Srdivacky } else if (N->getOperand(1).getOpcode() == ISD::MUL) { 638204961Srdivacky Mul = N->getOperand(1); 639204961Srdivacky Other = N->getOperand(0); 640204961Srdivacky } else { 641204961Srdivacky return SDValue(); 642204961Srdivacky } 643263508Sdim SDLoc dl(N); 644204961Srdivacky SDValue LL, RL, AddendL, AddendH; 645204961Srdivacky LL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 646204961Srdivacky Mul.getOperand(0), DAG.getConstant(0, MVT::i32)); 647204961Srdivacky RL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 648204961Srdivacky Mul.getOperand(1), DAG.getConstant(0, MVT::i32)); 649204961Srdivacky AddendL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 650204961Srdivacky Other, DAG.getConstant(0, MVT::i32)); 651204961Srdivacky AddendH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 652204961Srdivacky Other, DAG.getConstant(1, MVT::i32)); 653204961Srdivacky APInt HighMask = APInt::getHighBitsSet(64, 32); 654204961Srdivacky unsigned LHSSB = DAG.ComputeNumSignBits(Mul.getOperand(0)); 655204961Srdivacky unsigned RHSSB = DAG.ComputeNumSignBits(Mul.getOperand(1)); 656204961Srdivacky if (DAG.MaskedValueIsZero(Mul.getOperand(0), HighMask) && 657204961Srdivacky DAG.MaskedValueIsZero(Mul.getOperand(1), HighMask)) { 658204961Srdivacky // The inputs are both zero-extended. 659204961Srdivacky SDValue Hi = DAG.getNode(XCoreISD::MACCU, dl, 660204961Srdivacky DAG.getVTList(MVT::i32, MVT::i32), AddendH, 661204961Srdivacky AddendL, LL, RL); 662204961Srdivacky SDValue Lo(Hi.getNode(), 1); 663204961Srdivacky return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); 664204961Srdivacky } 665204961Srdivacky if (LHSSB > 32 && RHSSB > 32) { 666204961Srdivacky // The inputs are both sign-extended. 667204961Srdivacky SDValue Hi = DAG.getNode(XCoreISD::MACCS, dl, 668204961Srdivacky DAG.getVTList(MVT::i32, MVT::i32), AddendH, 669204961Srdivacky AddendL, LL, RL); 670204961Srdivacky SDValue Lo(Hi.getNode(), 1); 671204961Srdivacky return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); 672204961Srdivacky } 673204961Srdivacky SDValue LH, RH; 674204961Srdivacky LH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 675204961Srdivacky Mul.getOperand(0), DAG.getConstant(1, MVT::i32)); 676204961Srdivacky RH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 677204961Srdivacky Mul.getOperand(1), DAG.getConstant(1, MVT::i32)); 678204961Srdivacky SDValue Hi = DAG.getNode(XCoreISD::MACCU, dl, 679204961Srdivacky DAG.getVTList(MVT::i32, MVT::i32), AddendH, 680204961Srdivacky AddendL, LL, RL); 681204961Srdivacky SDValue Lo(Hi.getNode(), 1); 682204961Srdivacky RH = DAG.getNode(ISD::MUL, dl, MVT::i32, LL, RH); 683204961Srdivacky LH = DAG.getNode(ISD::MUL, dl, MVT::i32, LH, RL); 684204961Srdivacky Hi = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, RH); 685204961Srdivacky Hi = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, LH); 686204961Srdivacky return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); 687204961Srdivacky} 688204961Srdivacky 689204961SrdivackySDValue XCoreTargetLowering:: 690207618SrdivackyExpandADDSUB(SDNode *N, SelectionDAG &DAG) const 691193323Sed{ 692193323Sed assert(N->getValueType(0) == MVT::i64 && 693193323Sed (N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && 694193323Sed "Unknown operand to lower!"); 695204961Srdivacky 696204961Srdivacky if (N->getOpcode() == ISD::ADD) { 697204961Srdivacky SDValue Result = TryExpandADDWithMul(N, DAG); 698204961Srdivacky if (Result.getNode() != 0) 699204961Srdivacky return Result; 700204961Srdivacky } 701204961Srdivacky 702263508Sdim SDLoc dl(N); 703219077Sdim 704193323Sed // Extract components 705193323Sed SDValue LHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 706193323Sed N->getOperand(0), DAG.getConstant(0, MVT::i32)); 707193323Sed SDValue LHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 708193323Sed N->getOperand(0), DAG.getConstant(1, MVT::i32)); 709193323Sed SDValue RHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 710193323Sed N->getOperand(1), DAG.getConstant(0, MVT::i32)); 711193323Sed SDValue RHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 712193323Sed N->getOperand(1), DAG.getConstant(1, MVT::i32)); 713219077Sdim 714193323Sed // Expand 715193323Sed unsigned Opcode = (N->getOpcode() == ISD::ADD) ? XCoreISD::LADD : 716193323Sed XCoreISD::LSUB; 717193323Sed SDValue Zero = DAG.getConstant(0, MVT::i32); 718249423Sdim SDValue Lo = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32), 719249423Sdim LHSL, RHSL, Zero); 720249423Sdim SDValue Carry(Lo.getNode(), 1); 721219077Sdim 722249423Sdim SDValue Hi = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32), 723249423Sdim LHSH, RHSH, Carry); 724249423Sdim SDValue Ignored(Hi.getNode(), 1); 725193323Sed // Merge the pieces 726193323Sed return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); 727193323Sed} 728193323Sed 729193323SedSDValue XCoreTargetLowering:: 730207618SrdivackyLowerVAARG(SDValue Op, SelectionDAG &DAG) const 731193323Sed{ 732263508Sdim // Whist llvm does not support aggregate varargs we can ignore 733263508Sdim // the possibility of the ValueType being an implicit byVal vararg. 734193323Sed SDNode *Node = Op.getNode(); 735263508Sdim EVT VT = Node->getValueType(0); // not an aggregate 736263508Sdim SDValue InChain = Node->getOperand(0); 737263508Sdim SDValue VAListPtr = Node->getOperand(1); 738263508Sdim EVT PtrVT = VAListPtr.getValueType(); 739263508Sdim const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 740263508Sdim SDLoc dl(Node); 741263508Sdim SDValue VAList = DAG.getLoad(PtrVT, dl, InChain, 742263508Sdim VAListPtr, MachinePointerInfo(SV), 743234353Sdim false, false, false, 0); 744193323Sed // Increment the pointer, VAList, to the next vararg 745263508Sdim SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAList, 746263508Sdim DAG.getIntPtrConstant(VT.getSizeInBits() / 8)); 747193323Sed // Store the incremented VAList to the legalized pointer 748263508Sdim InChain = DAG.getStore(VAList.getValue(1), dl, nextPtr, VAListPtr, 749263508Sdim MachinePointerInfo(SV), false, false, 0); 750193323Sed // Load the actual argument out of the pointer VAList 751263508Sdim return DAG.getLoad(VT, dl, InChain, VAList, MachinePointerInfo(), 752234353Sdim false, false, false, 0); 753193323Sed} 754193323Sed 755193323SedSDValue XCoreTargetLowering:: 756207618SrdivackyLowerVASTART(SDValue Op, SelectionDAG &DAG) const 757193323Sed{ 758263508Sdim SDLoc dl(Op); 759193323Sed // vastart stores the address of the VarArgsFrameIndex slot into the 760193323Sed // memory location argument 761193323Sed MachineFunction &MF = DAG.getMachineFunction(); 762193323Sed XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>(); 763193323Sed SDValue Addr = DAG.getFrameIndex(XFI->getVarArgsFrameIndex(), MVT::i32); 764219077Sdim return DAG.getStore(Op.getOperand(0), dl, Addr, Op.getOperand(1), 765218893Sdim MachinePointerInfo(), false, false, 0); 766193323Sed} 767193323Sed 768207618SrdivackySDValue XCoreTargetLowering::LowerFRAMEADDR(SDValue Op, 769207618Srdivacky SelectionDAG &DAG) const { 770263508Sdim SDLoc dl(Op); 771219077Sdim // Depths > 0 not supported yet! 772193323Sed if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0) 773193323Sed return SDValue(); 774219077Sdim 775193323Sed MachineFunction &MF = DAG.getMachineFunction(); 776193323Sed const TargetRegisterInfo *RegInfo = getTargetMachine().getRegisterInfo(); 777219077Sdim return DAG.getCopyFromReg(DAG.getEntryNode(), dl, 778193323Sed RegInfo->getFrameRegister(MF), MVT::i32); 779193323Sed} 780193323Sed 781218893SdimSDValue XCoreTargetLowering:: 782226633SdimLowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const { 783226633Sdim return Op.getOperand(0); 784226633Sdim} 785226633Sdim 786226633SdimSDValue XCoreTargetLowering:: 787226633SdimLowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const { 788218893Sdim SDValue Chain = Op.getOperand(0); 789218893Sdim SDValue Trmp = Op.getOperand(1); // trampoline 790218893Sdim SDValue FPtr = Op.getOperand(2); // nested function 791218893Sdim SDValue Nest = Op.getOperand(3); // 'nest' parameter value 792218893Sdim 793218893Sdim const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 794218893Sdim 795218893Sdim // .align 4 796218893Sdim // LDAPF_u10 r11, nest 797218893Sdim // LDW_2rus r11, r11[0] 798218893Sdim // STWSP_ru6 r11, sp[0] 799218893Sdim // LDAPF_u10 r11, fptr 800218893Sdim // LDW_2rus r11, r11[0] 801218893Sdim // BAU_1r r11 802218893Sdim // nest: 803218893Sdim // .word nest 804218893Sdim // fptr: 805218893Sdim // .word fptr 806218893Sdim SDValue OutChains[5]; 807218893Sdim 808218893Sdim SDValue Addr = Trmp; 809218893Sdim 810263508Sdim SDLoc dl(Op); 811218893Sdim OutChains[0] = DAG.getStore(Chain, dl, DAG.getConstant(0x0a3cd805, MVT::i32), 812218893Sdim Addr, MachinePointerInfo(TrmpAddr), false, false, 813218893Sdim 0); 814218893Sdim 815218893Sdim Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 816218893Sdim DAG.getConstant(4, MVT::i32)); 817218893Sdim OutChains[1] = DAG.getStore(Chain, dl, DAG.getConstant(0xd80456c0, MVT::i32), 818218893Sdim Addr, MachinePointerInfo(TrmpAddr, 4), false, 819218893Sdim false, 0); 820218893Sdim 821218893Sdim Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 822218893Sdim DAG.getConstant(8, MVT::i32)); 823218893Sdim OutChains[2] = DAG.getStore(Chain, dl, DAG.getConstant(0x27fb0a3c, MVT::i32), 824218893Sdim Addr, MachinePointerInfo(TrmpAddr, 8), false, 825218893Sdim false, 0); 826218893Sdim 827218893Sdim Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 828218893Sdim DAG.getConstant(12, MVT::i32)); 829218893Sdim OutChains[3] = DAG.getStore(Chain, dl, Nest, Addr, 830218893Sdim MachinePointerInfo(TrmpAddr, 12), false, false, 831218893Sdim 0); 832218893Sdim 833218893Sdim Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 834218893Sdim DAG.getConstant(16, MVT::i32)); 835218893Sdim OutChains[4] = DAG.getStore(Chain, dl, FPtr, Addr, 836218893Sdim MachinePointerInfo(TrmpAddr, 16), false, false, 837218893Sdim 0); 838218893Sdim 839226633Sdim return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 5); 840218893Sdim} 841218893Sdim 842249423SdimSDValue XCoreTargetLowering:: 843249423SdimLowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const { 844263508Sdim SDLoc DL(Op); 845249423Sdim unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 846249423Sdim switch (IntNo) { 847249423Sdim case Intrinsic::xcore_crc8: 848249423Sdim EVT VT = Op.getValueType(); 849249423Sdim SDValue Data = 850249423Sdim DAG.getNode(XCoreISD::CRC8, DL, DAG.getVTList(VT, VT), 851249423Sdim Op.getOperand(1), Op.getOperand(2) , Op.getOperand(3)); 852249423Sdim SDValue Crc(Data.getNode(), 1); 853249423Sdim SDValue Results[] = { Crc, Data }; 854249423Sdim return DAG.getMergeValues(Results, 2, DL); 855249423Sdim } 856249423Sdim return SDValue(); 857249423Sdim} 858249423Sdim 859263508SdimSDValue XCoreTargetLowering:: 860263508SdimLowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const { 861263508Sdim SDLoc DL(Op); 862263508Sdim return DAG.getNode(XCoreISD::MEMBARRIER, DL, MVT::Other, Op.getOperand(0)); 863263508Sdim} 864263508Sdim 865193323Sed//===----------------------------------------------------------------------===// 866193323Sed// Calling Convention Implementation 867193323Sed//===----------------------------------------------------------------------===// 868193323Sed 869193323Sed#include "XCoreGenCallingConv.inc" 870193323Sed 871193323Sed//===----------------------------------------------------------------------===// 872198090Srdivacky// Call Calling Convention Implementation 873193323Sed//===----------------------------------------------------------------------===// 874193323Sed 875198090Srdivacky/// XCore call implementation 876198090SrdivackySDValue 877239462SdimXCoreTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 878207618Srdivacky SmallVectorImpl<SDValue> &InVals) const { 879239462Sdim SelectionDAG &DAG = CLI.DAG; 880263508Sdim SDLoc &dl = CLI.DL; 881263508Sdim SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; 882263508Sdim SmallVectorImpl<SDValue> &OutVals = CLI.OutVals; 883263508Sdim SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; 884239462Sdim SDValue Chain = CLI.Chain; 885239462Sdim SDValue Callee = CLI.Callee; 886239462Sdim bool &isTailCall = CLI.IsTailCall; 887239462Sdim CallingConv::ID CallConv = CLI.CallConv; 888239462Sdim bool isVarArg = CLI.IsVarArg; 889239462Sdim 890203954Srdivacky // XCore target does not yet support tail call optimization. 891203954Srdivacky isTailCall = false; 892198090Srdivacky 893193323Sed // For now, only CallingConv::C implemented 894198090Srdivacky switch (CallConv) 895193323Sed { 896193323Sed default: 897198090Srdivacky llvm_unreachable("Unsupported calling convention"); 898193323Sed case CallingConv::Fast: 899193323Sed case CallingConv::C: 900198090Srdivacky return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall, 901210299Sed Outs, OutVals, Ins, dl, DAG, InVals); 902193323Sed } 903193323Sed} 904193323Sed 905193323Sed/// LowerCCCCallTo - functions arguments are copied from virtual 906193323Sed/// regs to (physical regs)/(stack frame), CALLSEQ_START and 907193323Sed/// CALLSEQ_END are emitted. 908193323Sed/// TODO: isTailCall, sret. 909198090SrdivackySDValue 910198090SrdivackyXCoreTargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee, 911198090Srdivacky CallingConv::ID CallConv, bool isVarArg, 912198090Srdivacky bool isTailCall, 913198090Srdivacky const SmallVectorImpl<ISD::OutputArg> &Outs, 914210299Sed const SmallVectorImpl<SDValue> &OutVals, 915198090Srdivacky const SmallVectorImpl<ISD::InputArg> &Ins, 916263508Sdim SDLoc dl, SelectionDAG &DAG, 917207618Srdivacky SmallVectorImpl<SDValue> &InVals) const { 918193323Sed 919193323Sed // Analyze operands of the call, assigning locations to each operand. 920193323Sed SmallVector<CCValAssign, 16> ArgLocs; 921223017Sdim CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 922239462Sdim getTargetMachine(), ArgLocs, *DAG.getContext()); 923193323Sed 924193323Sed // The ABI dictates there should be one stack slot available to the callee 925193323Sed // on function entry (for saving lr). 926193323Sed CCInfo.AllocateStack(4, 4); 927193323Sed 928198090Srdivacky CCInfo.AnalyzeCallOperands(Outs, CC_XCore); 929193323Sed 930193323Sed // Get a count of how many bytes are to be pushed on the stack. 931193323Sed unsigned NumBytes = CCInfo.getNextStackOffset(); 932193323Sed 933219077Sdim Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, 934263508Sdim getPointerTy(), true), dl); 935193323Sed 936193323Sed SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass; 937193323Sed SmallVector<SDValue, 12> MemOpChains; 938193323Sed 939193323Sed // Walk the register/memloc assignments, inserting copies/loads. 940193323Sed for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 941193323Sed CCValAssign &VA = ArgLocs[i]; 942210299Sed SDValue Arg = OutVals[i]; 943193323Sed 944193323Sed // Promote the value if needed. 945193323Sed switch (VA.getLocInfo()) { 946198090Srdivacky default: llvm_unreachable("Unknown loc info!"); 947193323Sed case CCValAssign::Full: break; 948193323Sed case CCValAssign::SExt: 949193323Sed Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 950193323Sed break; 951193323Sed case CCValAssign::ZExt: 952193323Sed Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 953193323Sed break; 954193323Sed case CCValAssign::AExt: 955193323Sed Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 956193323Sed break; 957193323Sed } 958219077Sdim 959219077Sdim // Arguments that can be passed on register must be kept at 960193323Sed // RegsToPass vector 961193323Sed if (VA.isRegLoc()) { 962193323Sed RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 963193323Sed } else { 964193323Sed assert(VA.isMemLoc()); 965193323Sed 966193323Sed int Offset = VA.getLocMemOffset(); 967193323Sed 968219077Sdim MemOpChains.push_back(DAG.getNode(XCoreISD::STWSP, dl, MVT::Other, 969193323Sed Chain, Arg, 970193323Sed DAG.getConstant(Offset/4, MVT::i32))); 971193323Sed } 972193323Sed } 973193323Sed 974193323Sed // Transform all store nodes into one single node because 975193323Sed // all store nodes are independent of each other. 976193323Sed if (!MemOpChains.empty()) 977219077Sdim Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 978193323Sed &MemOpChains[0], MemOpChains.size()); 979193323Sed 980219077Sdim // Build a sequence of copy-to-reg nodes chained together with token 981193323Sed // chain and flag operands which copy the outgoing args into registers. 982221345Sdim // The InFlag in necessary since all emitted instructions must be 983193323Sed // stuck together. 984193323Sed SDValue InFlag; 985193323Sed for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 986219077Sdim Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 987193323Sed RegsToPass[i].second, InFlag); 988193323Sed InFlag = Chain.getValue(1); 989193323Sed } 990193323Sed 991193323Sed // If the callee is a GlobalAddress node (quite common, every direct call is) 992193323Sed // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 993193323Sed // Likewise ExternalSymbol -> TargetExternalSymbol. 994193323Sed if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 995210299Sed Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32); 996193323Sed else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) 997193323Sed Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32); 998193323Sed 999193323Sed // XCoreBranchLink = #chain, #target_address, #opt_in_flags... 1000219077Sdim // = Chain, Callee, Reg#1, Reg#2, ... 1001193323Sed // 1002193323Sed // Returns a chain & a flag for retval copy to use. 1003218893Sdim SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 1004193323Sed SmallVector<SDValue, 8> Ops; 1005193323Sed Ops.push_back(Chain); 1006193323Sed Ops.push_back(Callee); 1007193323Sed 1008219077Sdim // Add argument registers to the end of the list so that they are 1009193323Sed // known live into the call. 1010193323Sed for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 1011193323Sed Ops.push_back(DAG.getRegister(RegsToPass[i].first, 1012193323Sed RegsToPass[i].second.getValueType())); 1013193323Sed 1014193323Sed if (InFlag.getNode()) 1015193323Sed Ops.push_back(InFlag); 1016193323Sed 1017193323Sed Chain = DAG.getNode(XCoreISD::BL, dl, NodeTys, &Ops[0], Ops.size()); 1018193323Sed InFlag = Chain.getValue(1); 1019193323Sed 1020193323Sed // Create the CALLSEQ_END node. 1021193323Sed Chain = DAG.getCALLSEQ_END(Chain, 1022193323Sed DAG.getConstant(NumBytes, getPointerTy(), true), 1023193323Sed DAG.getConstant(0, getPointerTy(), true), 1024263508Sdim InFlag, dl); 1025193323Sed InFlag = Chain.getValue(1); 1026193323Sed 1027193323Sed // Handle result values, copying them out of physregs into vregs that we 1028193323Sed // return. 1029198090Srdivacky return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 1030198090Srdivacky Ins, dl, DAG, InVals); 1031193323Sed} 1032193323Sed 1033198090Srdivacky/// LowerCallResult - Lower the result values of a call into the 1034198090Srdivacky/// appropriate copies out of appropriate physical registers. 1035198090SrdivackySDValue 1036198090SrdivackyXCoreTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 1037198090Srdivacky CallingConv::ID CallConv, bool isVarArg, 1038198090Srdivacky const SmallVectorImpl<ISD::InputArg> &Ins, 1039263508Sdim SDLoc dl, SelectionDAG &DAG, 1040207618Srdivacky SmallVectorImpl<SDValue> &InVals) const { 1041193323Sed 1042193323Sed // Assign locations to each value returned by this call. 1043193323Sed SmallVector<CCValAssign, 16> RVLocs; 1044223017Sdim CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1045239462Sdim getTargetMachine(), RVLocs, *DAG.getContext()); 1046193323Sed 1047198090Srdivacky CCInfo.AnalyzeCallResult(Ins, RetCC_XCore); 1048193323Sed 1049193323Sed // Copy all of the result registers out of their specified physreg. 1050193323Sed for (unsigned i = 0; i != RVLocs.size(); ++i) { 1051193323Sed Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), 1052193323Sed RVLocs[i].getValVT(), InFlag).getValue(1); 1053193323Sed InFlag = Chain.getValue(2); 1054198090Srdivacky InVals.push_back(Chain.getValue(0)); 1055193323Sed } 1056193323Sed 1057198090Srdivacky return Chain; 1058193323Sed} 1059193323Sed 1060193323Sed//===----------------------------------------------------------------------===// 1061198090Srdivacky// Formal Arguments Calling Convention Implementation 1062193323Sed//===----------------------------------------------------------------------===// 1063193323Sed 1064263508Sdimnamespace { 1065263508Sdim struct ArgDataPair { SDValue SDV; ISD::ArgFlagsTy Flags; }; 1066263508Sdim} 1067263508Sdim 1068198090Srdivacky/// XCore formal arguments implementation 1069198090SrdivackySDValue 1070198090SrdivackyXCoreTargetLowering::LowerFormalArguments(SDValue Chain, 1071198090Srdivacky CallingConv::ID CallConv, 1072198090Srdivacky bool isVarArg, 1073198090Srdivacky const SmallVectorImpl<ISD::InputArg> &Ins, 1074263508Sdim SDLoc dl, 1075198090Srdivacky SelectionDAG &DAG, 1076207618Srdivacky SmallVectorImpl<SDValue> &InVals) 1077207618Srdivacky const { 1078198090Srdivacky switch (CallConv) 1079193323Sed { 1080193323Sed default: 1081198090Srdivacky llvm_unreachable("Unsupported calling convention"); 1082193323Sed case CallingConv::C: 1083193323Sed case CallingConv::Fast: 1084198090Srdivacky return LowerCCCArguments(Chain, CallConv, isVarArg, 1085198090Srdivacky Ins, dl, DAG, InVals); 1086193323Sed } 1087193323Sed} 1088193323Sed 1089193323Sed/// LowerCCCArguments - transform physical registers into 1090193323Sed/// virtual registers and generate load operations for 1091193323Sed/// arguments places on the stack. 1092193323Sed/// TODO: sret 1093198090SrdivackySDValue 1094198090SrdivackyXCoreTargetLowering::LowerCCCArguments(SDValue Chain, 1095198090Srdivacky CallingConv::ID CallConv, 1096198090Srdivacky bool isVarArg, 1097198090Srdivacky const SmallVectorImpl<ISD::InputArg> 1098198090Srdivacky &Ins, 1099263508Sdim SDLoc dl, 1100198090Srdivacky SelectionDAG &DAG, 1101207618Srdivacky SmallVectorImpl<SDValue> &InVals) const { 1102193323Sed MachineFunction &MF = DAG.getMachineFunction(); 1103193323Sed MachineFrameInfo *MFI = MF.getFrameInfo(); 1104193323Sed MachineRegisterInfo &RegInfo = MF.getRegInfo(); 1105193323Sed 1106193323Sed // Assign locations to all of the incoming arguments. 1107193323Sed SmallVector<CCValAssign, 16> ArgLocs; 1108223017Sdim CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1109239462Sdim getTargetMachine(), ArgLocs, *DAG.getContext()); 1110193323Sed 1111198090Srdivacky CCInfo.AnalyzeFormalArguments(Ins, CC_XCore); 1112193323Sed 1113218893Sdim unsigned StackSlotSize = XCoreFrameLowering::stackSlotSize(); 1114193323Sed 1115193323Sed unsigned LRSaveSize = StackSlotSize; 1116219077Sdim 1117263508Sdim // All getCopyFromReg ops must precede any getMemcpys to prevent the 1118263508Sdim // scheduler clobbering a register before it has been copied. 1119263508Sdim // The stages are: 1120263508Sdim // 1. CopyFromReg (and load) arg & vararg registers. 1121263508Sdim // 2. Chain CopyFromReg nodes into a TokenFactor. 1122263508Sdim // 3. Memcpy 'byVal' args & push final InVals. 1123263508Sdim // 4. Chain mem ops nodes into a TokenFactor. 1124263508Sdim SmallVector<SDValue, 4> CFRegNode; 1125263508Sdim SmallVector<ArgDataPair, 4> ArgData; 1126263508Sdim SmallVector<SDValue, 4> MemOps; 1127263508Sdim 1128263508Sdim // 1a. CopyFromReg (and load) arg registers. 1129193323Sed for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1130193323Sed 1131193323Sed CCValAssign &VA = ArgLocs[i]; 1132263508Sdim SDValue ArgIn; 1133219077Sdim 1134193323Sed if (VA.isRegLoc()) { 1135193323Sed // Arguments passed in registers 1136198090Srdivacky EVT RegVT = VA.getLocVT(); 1137198090Srdivacky switch (RegVT.getSimpleVT().SimpleTy) { 1138193323Sed default: 1139198090Srdivacky { 1140198090Srdivacky#ifndef NDEBUG 1141198090Srdivacky errs() << "LowerFormalArguments Unhandled argument type: " 1142198090Srdivacky << RegVT.getSimpleVT().SimpleTy << "\n"; 1143198090Srdivacky#endif 1144198090Srdivacky llvm_unreachable(0); 1145198090Srdivacky } 1146193323Sed case MVT::i32: 1147239462Sdim unsigned VReg = RegInfo.createVirtualRegister(&XCore::GRRegsRegClass); 1148193323Sed RegInfo.addLiveIn(VA.getLocReg(), VReg); 1149263508Sdim ArgIn = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); 1150263508Sdim CFRegNode.push_back(ArgIn.getValue(ArgIn->getNumValues() - 1)); 1151193323Sed } 1152193323Sed } else { 1153193323Sed // sanity check 1154193323Sed assert(VA.isMemLoc()); 1155193323Sed // Load the argument to a virtual register 1156193323Sed unsigned ObjSize = VA.getLocVT().getSizeInBits()/8; 1157193323Sed if (ObjSize > StackSlotSize) { 1158198090Srdivacky errs() << "LowerFormalArguments Unhandled argument type: " 1159218893Sdim << EVT(VA.getLocVT()).getEVTString() 1160198090Srdivacky << "\n"; 1161193323Sed } 1162193323Sed // Create the frame index object for this incoming parameter... 1163193323Sed int FI = MFI->CreateFixedObject(ObjSize, 1164199481Srdivacky LRSaveSize + VA.getLocMemOffset(), 1165210299Sed true); 1166193323Sed 1167193323Sed // Create the SelectionDAG nodes corresponding to a load 1168193323Sed //from this parameter 1169193323Sed SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); 1170263508Sdim ArgIn = DAG.getLoad(VA.getLocVT(), dl, Chain, FIN, 1171263508Sdim MachinePointerInfo::getFixedStack(FI), 1172263508Sdim false, false, false, 0); 1173193323Sed } 1174263508Sdim const ArgDataPair ADP = { ArgIn, Ins[i].Flags }; 1175263508Sdim ArgData.push_back(ADP); 1176193323Sed } 1177219077Sdim 1178263508Sdim // 1b. CopyFromReg vararg registers. 1179193323Sed if (isVarArg) { 1180263508Sdim // Argument registers 1181234353Sdim static const uint16_t ArgRegs[] = { 1182193323Sed XCore::R0, XCore::R1, XCore::R2, XCore::R3 1183193323Sed }; 1184193323Sed XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>(); 1185193323Sed unsigned FirstVAReg = CCInfo.getFirstUnallocated(ArgRegs, 1186193323Sed array_lengthof(ArgRegs)); 1187193323Sed if (FirstVAReg < array_lengthof(ArgRegs)) { 1188193323Sed int offset = 0; 1189193323Sed // Save remaining registers, storing higher register numbers at a higher 1190193323Sed // address 1191226633Sdim for (int i = array_lengthof(ArgRegs) - 1; i >= (int)FirstVAReg; --i) { 1192193323Sed // Create a stack slot 1193210299Sed int FI = MFI->CreateFixedObject(4, offset, true); 1194226633Sdim if (i == (int)FirstVAReg) { 1195193323Sed XFI->setVarArgsFrameIndex(FI); 1196193323Sed } 1197193323Sed offset -= StackSlotSize; 1198193323Sed SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); 1199193323Sed // Move argument from phys reg -> virt reg 1200239462Sdim unsigned VReg = RegInfo.createVirtualRegister(&XCore::GRRegsRegClass); 1201193323Sed RegInfo.addLiveIn(ArgRegs[i], VReg); 1202198090Srdivacky SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); 1203263508Sdim CFRegNode.push_back(Val.getValue(Val->getNumValues() - 1)); 1204193323Sed // Move argument from virt reg -> stack 1205218893Sdim SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, 1206218893Sdim MachinePointerInfo(), false, false, 0); 1207193323Sed MemOps.push_back(Store); 1208193323Sed } 1209193323Sed } else { 1210193323Sed // This will point to the next argument passed via stack. 1211193323Sed XFI->setVarArgsFrameIndex( 1212199481Srdivacky MFI->CreateFixedObject(4, LRSaveSize + CCInfo.getNextStackOffset(), 1213210299Sed true)); 1214193323Sed } 1215193323Sed } 1216219077Sdim 1217263508Sdim // 2. chain CopyFromReg nodes into a TokenFactor. 1218263508Sdim if (!CFRegNode.empty()) 1219263508Sdim Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &CFRegNode[0], 1220263508Sdim CFRegNode.size()); 1221263508Sdim 1222263508Sdim // 3. Memcpy 'byVal' args & push final InVals. 1223263508Sdim // Aggregates passed "byVal" need to be copied by the callee. 1224263508Sdim // The callee will use a pointer to this copy, rather than the original 1225263508Sdim // pointer. 1226263508Sdim for (SmallVectorImpl<ArgDataPair>::const_iterator ArgDI = ArgData.begin(), 1227263508Sdim ArgDE = ArgData.end(); 1228263508Sdim ArgDI != ArgDE; ++ArgDI) { 1229263508Sdim if (ArgDI->Flags.isByVal() && ArgDI->Flags.getByValSize()) { 1230263508Sdim unsigned Size = ArgDI->Flags.getByValSize(); 1231263508Sdim unsigned Align = std::max(StackSlotSize, ArgDI->Flags.getByValAlign()); 1232263508Sdim // Create a new object on the stack and copy the pointee into it. 1233263508Sdim int FI = MFI->CreateStackObject(Size, Align, false, false); 1234263508Sdim SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); 1235263508Sdim InVals.push_back(FIN); 1236263508Sdim MemOps.push_back(DAG.getMemcpy(Chain, dl, FIN, ArgDI->SDV, 1237263508Sdim DAG.getConstant(Size, MVT::i32), 1238263508Sdim Align, false, false, 1239263508Sdim MachinePointerInfo(), 1240263508Sdim MachinePointerInfo())); 1241263508Sdim } else { 1242263508Sdim InVals.push_back(ArgDI->SDV); 1243263508Sdim } 1244263508Sdim } 1245263508Sdim 1246263508Sdim // 4, chain mem ops nodes into a TokenFactor. 1247263508Sdim if (!MemOps.empty()) { 1248263508Sdim MemOps.push_back(Chain); 1249263508Sdim Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOps[0], 1250263508Sdim MemOps.size()); 1251263508Sdim } 1252263508Sdim 1253198090Srdivacky return Chain; 1254193323Sed} 1255193323Sed 1256193323Sed//===----------------------------------------------------------------------===// 1257193323Sed// Return Value Calling Convention Implementation 1258193323Sed//===----------------------------------------------------------------------===// 1259193323Sed 1260199481Srdivackybool XCoreTargetLowering:: 1261223017SdimCanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 1262239462Sdim bool isVarArg, 1263210299Sed const SmallVectorImpl<ISD::OutputArg> &Outs, 1264210299Sed LLVMContext &Context) const { 1265199481Srdivacky SmallVector<CCValAssign, 16> RVLocs; 1266223017Sdim CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), RVLocs, Context); 1267210299Sed return CCInfo.CheckReturn(Outs, RetCC_XCore); 1268199481Srdivacky} 1269199481Srdivacky 1270198090SrdivackySDValue 1271198090SrdivackyXCoreTargetLowering::LowerReturn(SDValue Chain, 1272198090Srdivacky CallingConv::ID CallConv, bool isVarArg, 1273198090Srdivacky const SmallVectorImpl<ISD::OutputArg> &Outs, 1274210299Sed const SmallVectorImpl<SDValue> &OutVals, 1275263508Sdim SDLoc dl, SelectionDAG &DAG) const { 1276198090Srdivacky 1277193323Sed // CCValAssign - represent the assignment of 1278193323Sed // the return value to a location 1279193323Sed SmallVector<CCValAssign, 16> RVLocs; 1280193323Sed 1281193323Sed // CCState - Info about the registers and stack slot. 1282223017Sdim CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1283239462Sdim getTargetMachine(), RVLocs, *DAG.getContext()); 1284193323Sed 1285223017Sdim // Analyze return values. 1286198090Srdivacky CCInfo.AnalyzeReturn(Outs, RetCC_XCore); 1287193323Sed 1288193323Sed SDValue Flag; 1289249423Sdim SmallVector<SDValue, 4> RetOps(1, Chain); 1290193323Sed 1291249423Sdim // Return on XCore is always a "retsp 0" 1292249423Sdim RetOps.push_back(DAG.getConstant(0, MVT::i32)); 1293249423Sdim 1294193323Sed // Copy the result values into the output registers. 1295193323Sed for (unsigned i = 0; i != RVLocs.size(); ++i) { 1296193323Sed CCValAssign &VA = RVLocs[i]; 1297193323Sed assert(VA.isRegLoc() && "Can only return in registers!"); 1298193323Sed 1299219077Sdim Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), 1300210299Sed OutVals[i], Flag); 1301193323Sed 1302193323Sed // guarantee that all emitted copies are 1303193323Sed // stuck together, avoiding something bad 1304193323Sed Flag = Chain.getValue(1); 1305249423Sdim RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 1306193323Sed } 1307193323Sed 1308249423Sdim RetOps[0] = Chain; // Update chain. 1309249423Sdim 1310249423Sdim // Add the flag if we have it. 1311193323Sed if (Flag.getNode()) 1312249423Sdim RetOps.push_back(Flag); 1313249423Sdim 1314249423Sdim return DAG.getNode(XCoreISD::RETSP, dl, MVT::Other, 1315249423Sdim &RetOps[0], RetOps.size()); 1316193323Sed} 1317193323Sed 1318193323Sed//===----------------------------------------------------------------------===// 1319193323Sed// Other Lowering Code 1320193323Sed//===----------------------------------------------------------------------===// 1321193323Sed 1322193323SedMachineBasicBlock * 1323193323SedXCoreTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 1324207618Srdivacky MachineBasicBlock *BB) const { 1325193323Sed const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo(); 1326193323Sed DebugLoc dl = MI->getDebugLoc(); 1327193323Sed assert((MI->getOpcode() == XCore::SELECT_CC) && 1328193323Sed "Unexpected instr type to insert"); 1329219077Sdim 1330193323Sed // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 1331193323Sed // control-flow pattern. The incoming instruction knows the destination vreg 1332193323Sed // to set, the condition code register to branch on, the true/false values to 1333193323Sed // select between, and a branch opcode to use. 1334193323Sed const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1335193323Sed MachineFunction::iterator It = BB; 1336193323Sed ++It; 1337219077Sdim 1338193323Sed // thisMBB: 1339193323Sed // ... 1340193323Sed // TrueVal = ... 1341193323Sed // cmpTY ccX, r1, r2 1342193323Sed // bCC copy1MBB 1343193323Sed // fallthrough --> copy0MBB 1344193323Sed MachineBasicBlock *thisMBB = BB; 1345193323Sed MachineFunction *F = BB->getParent(); 1346193323Sed MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 1347193323Sed MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 1348193323Sed F->insert(It, copy0MBB); 1349193323Sed F->insert(It, sinkMBB); 1350210299Sed 1351210299Sed // Transfer the remainder of BB and its successor edges to sinkMBB. 1352210299Sed sinkMBB->splice(sinkMBB->begin(), BB, 1353210299Sed llvm::next(MachineBasicBlock::iterator(MI)), 1354210299Sed BB->end()); 1355210299Sed sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 1356210299Sed 1357193323Sed // Next, add the true and fallthrough blocks as its successors. 1358193323Sed BB->addSuccessor(copy0MBB); 1359193323Sed BB->addSuccessor(sinkMBB); 1360219077Sdim 1361210299Sed BuildMI(BB, dl, TII.get(XCore::BRFT_lru6)) 1362210299Sed .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); 1363210299Sed 1364193323Sed // copy0MBB: 1365193323Sed // %FalseValue = ... 1366193323Sed // # fallthrough to sinkMBB 1367193323Sed BB = copy0MBB; 1368219077Sdim 1369193323Sed // Update machine-CFG edges 1370193323Sed BB->addSuccessor(sinkMBB); 1371219077Sdim 1372193323Sed // sinkMBB: 1373193323Sed // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 1374193323Sed // ... 1375193323Sed BB = sinkMBB; 1376210299Sed BuildMI(*BB, BB->begin(), dl, 1377210299Sed TII.get(XCore::PHI), MI->getOperand(0).getReg()) 1378193323Sed .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB) 1379193323Sed .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 1380219077Sdim 1381210299Sed MI->eraseFromParent(); // The pseudo instruction is gone now. 1382193323Sed return BB; 1383193323Sed} 1384193323Sed 1385193323Sed//===----------------------------------------------------------------------===// 1386198090Srdivacky// Target Optimization Hooks 1387198090Srdivacky//===----------------------------------------------------------------------===// 1388198090Srdivacky 1389198090SrdivackySDValue XCoreTargetLowering::PerformDAGCombine(SDNode *N, 1390198090Srdivacky DAGCombinerInfo &DCI) const { 1391198090Srdivacky SelectionDAG &DAG = DCI.DAG; 1392263508Sdim SDLoc dl(N); 1393198090Srdivacky switch (N->getOpcode()) { 1394198090Srdivacky default: break; 1395204961Srdivacky case XCoreISD::LADD: { 1396204961Srdivacky SDValue N0 = N->getOperand(0); 1397204961Srdivacky SDValue N1 = N->getOperand(1); 1398204961Srdivacky SDValue N2 = N->getOperand(2); 1399204961Srdivacky ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1400204961Srdivacky ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1401204961Srdivacky EVT VT = N0.getValueType(); 1402204961Srdivacky 1403204961Srdivacky // canonicalize constant to RHS 1404204961Srdivacky if (N0C && !N1C) 1405204961Srdivacky return DAG.getNode(XCoreISD::LADD, dl, DAG.getVTList(VT, VT), N1, N0, N2); 1406204961Srdivacky 1407204961Srdivacky // fold (ladd 0, 0, x) -> 0, x & 1 1408204961Srdivacky if (N0C && N0C->isNullValue() && N1C && N1C->isNullValue()) { 1409204961Srdivacky SDValue Carry = DAG.getConstant(0, VT); 1410204961Srdivacky SDValue Result = DAG.getNode(ISD::AND, dl, VT, N2, 1411204961Srdivacky DAG.getConstant(1, VT)); 1412249423Sdim SDValue Ops[] = { Result, Carry }; 1413204961Srdivacky return DAG.getMergeValues(Ops, 2, dl); 1414204961Srdivacky } 1415204961Srdivacky 1416204961Srdivacky // fold (ladd x, 0, y) -> 0, add x, y iff carry is unused and y has only the 1417204961Srdivacky // low bit set 1418249423Sdim if (N1C && N1C->isNullValue() && N->hasNUsesOfValue(0, 1)) { 1419204961Srdivacky APInt KnownZero, KnownOne; 1420204961Srdivacky APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), 1421204961Srdivacky VT.getSizeInBits() - 1); 1422234353Sdim DAG.ComputeMaskedBits(N2, KnownZero, KnownOne); 1423234353Sdim if ((KnownZero & Mask) == Mask) { 1424204961Srdivacky SDValue Carry = DAG.getConstant(0, VT); 1425204961Srdivacky SDValue Result = DAG.getNode(ISD::ADD, dl, VT, N0, N2); 1426249423Sdim SDValue Ops[] = { Result, Carry }; 1427204961Srdivacky return DAG.getMergeValues(Ops, 2, dl); 1428204961Srdivacky } 1429204961Srdivacky } 1430204961Srdivacky } 1431204961Srdivacky break; 1432204961Srdivacky case XCoreISD::LSUB: { 1433204961Srdivacky SDValue N0 = N->getOperand(0); 1434204961Srdivacky SDValue N1 = N->getOperand(1); 1435204961Srdivacky SDValue N2 = N->getOperand(2); 1436204961Srdivacky ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1437204961Srdivacky ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1438204961Srdivacky EVT VT = N0.getValueType(); 1439204961Srdivacky 1440204961Srdivacky // fold (lsub 0, 0, x) -> x, -x iff x has only the low bit set 1441219077Sdim if (N0C && N0C->isNullValue() && N1C && N1C->isNullValue()) { 1442204961Srdivacky APInt KnownZero, KnownOne; 1443204961Srdivacky APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), 1444204961Srdivacky VT.getSizeInBits() - 1); 1445234353Sdim DAG.ComputeMaskedBits(N2, KnownZero, KnownOne); 1446234353Sdim if ((KnownZero & Mask) == Mask) { 1447204961Srdivacky SDValue Borrow = N2; 1448204961Srdivacky SDValue Result = DAG.getNode(ISD::SUB, dl, VT, 1449204961Srdivacky DAG.getConstant(0, VT), N2); 1450249423Sdim SDValue Ops[] = { Result, Borrow }; 1451204961Srdivacky return DAG.getMergeValues(Ops, 2, dl); 1452204961Srdivacky } 1453204961Srdivacky } 1454204961Srdivacky 1455204961Srdivacky // fold (lsub x, 0, y) -> 0, sub x, y iff borrow is unused and y has only the 1456204961Srdivacky // low bit set 1457249423Sdim if (N1C && N1C->isNullValue() && N->hasNUsesOfValue(0, 1)) { 1458204961Srdivacky APInt KnownZero, KnownOne; 1459204961Srdivacky APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), 1460204961Srdivacky VT.getSizeInBits() - 1); 1461234353Sdim DAG.ComputeMaskedBits(N2, KnownZero, KnownOne); 1462234353Sdim if ((KnownZero & Mask) == Mask) { 1463204961Srdivacky SDValue Borrow = DAG.getConstant(0, VT); 1464204961Srdivacky SDValue Result = DAG.getNode(ISD::SUB, dl, VT, N0, N2); 1465249423Sdim SDValue Ops[] = { Result, Borrow }; 1466204961Srdivacky return DAG.getMergeValues(Ops, 2, dl); 1467204961Srdivacky } 1468204961Srdivacky } 1469204961Srdivacky } 1470204961Srdivacky break; 1471205218Srdivacky case XCoreISD::LMUL: { 1472205218Srdivacky SDValue N0 = N->getOperand(0); 1473205218Srdivacky SDValue N1 = N->getOperand(1); 1474205218Srdivacky SDValue N2 = N->getOperand(2); 1475205218Srdivacky SDValue N3 = N->getOperand(3); 1476205218Srdivacky ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1477205218Srdivacky ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1478205218Srdivacky EVT VT = N0.getValueType(); 1479205218Srdivacky // Canonicalize multiplicative constant to RHS. If both multiplicative 1480205218Srdivacky // operands are constant canonicalize smallest to RHS. 1481205218Srdivacky if ((N0C && !N1C) || 1482205218Srdivacky (N0C && N1C && N0C->getZExtValue() < N1C->getZExtValue())) 1483226633Sdim return DAG.getNode(XCoreISD::LMUL, dl, DAG.getVTList(VT, VT), 1484226633Sdim N1, N0, N2, N3); 1485205218Srdivacky 1486205218Srdivacky // lmul(x, 0, a, b) 1487205218Srdivacky if (N1C && N1C->isNullValue()) { 1488205218Srdivacky // If the high result is unused fold to add(a, b) 1489205218Srdivacky if (N->hasNUsesOfValue(0, 0)) { 1490205218Srdivacky SDValue Lo = DAG.getNode(ISD::ADD, dl, VT, N2, N3); 1491249423Sdim SDValue Ops[] = { Lo, Lo }; 1492205218Srdivacky return DAG.getMergeValues(Ops, 2, dl); 1493205218Srdivacky } 1494205218Srdivacky // Otherwise fold to ladd(a, b, 0) 1495249423Sdim SDValue Result = 1496249423Sdim DAG.getNode(XCoreISD::LADD, dl, DAG.getVTList(VT, VT), N2, N3, N1); 1497249423Sdim SDValue Carry(Result.getNode(), 1); 1498249423Sdim SDValue Ops[] = { Carry, Result }; 1499249423Sdim return DAG.getMergeValues(Ops, 2, dl); 1500205218Srdivacky } 1501205218Srdivacky } 1502205218Srdivacky break; 1503204961Srdivacky case ISD::ADD: { 1504205218Srdivacky // Fold 32 bit expressions such as add(add(mul(x,y),a),b) -> 1505205218Srdivacky // lmul(x, y, a, b). The high result of lmul will be ignored. 1506204961Srdivacky // This is only profitable if the intermediate results are unused 1507204961Srdivacky // elsewhere. 1508204961Srdivacky SDValue Mul0, Mul1, Addend0, Addend1; 1509205218Srdivacky if (N->getValueType(0) == MVT::i32 && 1510205218Srdivacky isADDADDMUL(SDValue(N, 0), Mul0, Mul1, Addend0, Addend1, true)) { 1511204961Srdivacky SDValue Ignored = DAG.getNode(XCoreISD::LMUL, dl, 1512204961Srdivacky DAG.getVTList(MVT::i32, MVT::i32), Mul0, 1513204961Srdivacky Mul1, Addend0, Addend1); 1514204961Srdivacky SDValue Result(Ignored.getNode(), 1); 1515204961Srdivacky return Result; 1516204961Srdivacky } 1517205218Srdivacky APInt HighMask = APInt::getHighBitsSet(64, 32); 1518205218Srdivacky // Fold 64 bit expression such as add(add(mul(x,y),a),b) -> 1519205218Srdivacky // lmul(x, y, a, b) if all operands are zero-extended. We do this 1520205218Srdivacky // before type legalization as it is messy to match the operands after 1521205218Srdivacky // that. 1522205218Srdivacky if (N->getValueType(0) == MVT::i64 && 1523205218Srdivacky isADDADDMUL(SDValue(N, 0), Mul0, Mul1, Addend0, Addend1, false) && 1524205218Srdivacky DAG.MaskedValueIsZero(Mul0, HighMask) && 1525205218Srdivacky DAG.MaskedValueIsZero(Mul1, HighMask) && 1526205218Srdivacky DAG.MaskedValueIsZero(Addend0, HighMask) && 1527205218Srdivacky DAG.MaskedValueIsZero(Addend1, HighMask)) { 1528205218Srdivacky SDValue Mul0L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 1529205218Srdivacky Mul0, DAG.getConstant(0, MVT::i32)); 1530205218Srdivacky SDValue Mul1L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 1531205218Srdivacky Mul1, DAG.getConstant(0, MVT::i32)); 1532205218Srdivacky SDValue Addend0L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 1533205218Srdivacky Addend0, DAG.getConstant(0, MVT::i32)); 1534205218Srdivacky SDValue Addend1L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 1535205218Srdivacky Addend1, DAG.getConstant(0, MVT::i32)); 1536205218Srdivacky SDValue Hi = DAG.getNode(XCoreISD::LMUL, dl, 1537205218Srdivacky DAG.getVTList(MVT::i32, MVT::i32), Mul0L, Mul1L, 1538205218Srdivacky Addend0L, Addend1L); 1539205218Srdivacky SDValue Lo(Hi.getNode(), 1); 1540205218Srdivacky return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); 1541205218Srdivacky } 1542204961Srdivacky } 1543204961Srdivacky break; 1544198090Srdivacky case ISD::STORE: { 1545198090Srdivacky // Replace unaligned store of unaligned load with memmove. 1546198090Srdivacky StoreSDNode *ST = cast<StoreSDNode>(N); 1547198090Srdivacky if (!DCI.isBeforeLegalize() || 1548198090Srdivacky allowsUnalignedMemoryAccesses(ST->getMemoryVT()) || 1549198090Srdivacky ST->isVolatile() || ST->isIndexed()) { 1550198090Srdivacky break; 1551198090Srdivacky } 1552198090Srdivacky SDValue Chain = ST->getChain(); 1553198090Srdivacky 1554198090Srdivacky unsigned StoreBits = ST->getMemoryVT().getStoreSizeInBits(); 1555198090Srdivacky if (StoreBits % 8) { 1556198090Srdivacky break; 1557198090Srdivacky } 1558243830Sdim unsigned ABIAlignment = getDataLayout()->getABITypeAlignment( 1559198090Srdivacky ST->getMemoryVT().getTypeForEVT(*DCI.DAG.getContext())); 1560198090Srdivacky unsigned Alignment = ST->getAlignment(); 1561198090Srdivacky if (Alignment >= ABIAlignment) { 1562198090Srdivacky break; 1563198090Srdivacky } 1564198090Srdivacky 1565198090Srdivacky if (LoadSDNode *LD = dyn_cast<LoadSDNode>(ST->getValue())) { 1566198090Srdivacky if (LD->hasNUsesOfValue(1, 0) && ST->getMemoryVT() == LD->getMemoryVT() && 1567198090Srdivacky LD->getAlignment() == Alignment && 1568198090Srdivacky !LD->isVolatile() && !LD->isIndexed() && 1569198090Srdivacky Chain.reachesChainWithoutSideEffects(SDValue(LD, 1))) { 1570198090Srdivacky return DAG.getMemmove(Chain, dl, ST->getBasePtr(), 1571198090Srdivacky LD->getBasePtr(), 1572198090Srdivacky DAG.getConstant(StoreBits/8, MVT::i32), 1573218893Sdim Alignment, false, ST->getPointerInfo(), 1574218893Sdim LD->getPointerInfo()); 1575198090Srdivacky } 1576198090Srdivacky } 1577198090Srdivacky break; 1578198090Srdivacky } 1579198090Srdivacky } 1580198090Srdivacky return SDValue(); 1581198090Srdivacky} 1582198090Srdivacky 1583204961Srdivackyvoid XCoreTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 1584204961Srdivacky APInt &KnownZero, 1585204961Srdivacky APInt &KnownOne, 1586204961Srdivacky const SelectionDAG &DAG, 1587204961Srdivacky unsigned Depth) const { 1588234353Sdim KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0); 1589204961Srdivacky switch (Op.getOpcode()) { 1590204961Srdivacky default: break; 1591204961Srdivacky case XCoreISD::LADD: 1592204961Srdivacky case XCoreISD::LSUB: 1593249423Sdim if (Op.getResNo() == 1) { 1594204961Srdivacky // Top bits of carry / borrow are clear. 1595234353Sdim KnownZero = APInt::getHighBitsSet(KnownZero.getBitWidth(), 1596234353Sdim KnownZero.getBitWidth() - 1); 1597204961Srdivacky } 1598204961Srdivacky break; 1599204961Srdivacky } 1600204961Srdivacky} 1601204961Srdivacky 1602198090Srdivacky//===----------------------------------------------------------------------===// 1603193323Sed// Addressing mode description hooks 1604193323Sed//===----------------------------------------------------------------------===// 1605193323Sed 1606193323Sedstatic inline bool isImmUs(int64_t val) 1607193323Sed{ 1608193323Sed return (val >= 0 && val <= 11); 1609193323Sed} 1610193323Sed 1611193323Sedstatic inline bool isImmUs2(int64_t val) 1612193323Sed{ 1613193323Sed return (val%2 == 0 && isImmUs(val/2)); 1614193323Sed} 1615193323Sed 1616193323Sedstatic inline bool isImmUs4(int64_t val) 1617193323Sed{ 1618193323Sed return (val%4 == 0 && isImmUs(val/4)); 1619193323Sed} 1620193323Sed 1621193323Sed/// isLegalAddressingMode - Return true if the addressing mode represented 1622193323Sed/// by AM is legal for this target, for a load/store of the specified type. 1623193323Sedbool 1624219077SdimXCoreTargetLowering::isLegalAddressingMode(const AddrMode &AM, 1625226633Sdim Type *Ty) const { 1626198090Srdivacky if (Ty->getTypeID() == Type::VoidTyID) 1627204642Srdivacky return AM.Scale == 0 && isImmUs(AM.BaseOffs) && isImmUs4(AM.BaseOffs); 1628198090Srdivacky 1629243830Sdim const DataLayout *TD = TM.getDataLayout(); 1630198090Srdivacky unsigned Size = TD->getTypeAllocSize(Ty); 1631193323Sed if (AM.BaseGV) { 1632198090Srdivacky return Size >= 4 && !AM.HasBaseReg && AM.Scale == 0 && 1633193323Sed AM.BaseOffs%4 == 0; 1634193323Sed } 1635219077Sdim 1636198090Srdivacky switch (Size) { 1637198090Srdivacky case 1: 1638193323Sed // reg + imm 1639193323Sed if (AM.Scale == 0) { 1640193323Sed return isImmUs(AM.BaseOffs); 1641193323Sed } 1642198090Srdivacky // reg + reg 1643193323Sed return AM.Scale == 1 && AM.BaseOffs == 0; 1644198090Srdivacky case 2: 1645198090Srdivacky case 3: 1646193323Sed // reg + imm 1647193323Sed if (AM.Scale == 0) { 1648193323Sed return isImmUs2(AM.BaseOffs); 1649193323Sed } 1650198090Srdivacky // reg + reg<<1 1651193323Sed return AM.Scale == 2 && AM.BaseOffs == 0; 1652198090Srdivacky default: 1653193323Sed // reg + imm 1654193323Sed if (AM.Scale == 0) { 1655193323Sed return isImmUs4(AM.BaseOffs); 1656193323Sed } 1657193323Sed // reg + reg<<2 1658193323Sed return AM.Scale == 4 && AM.BaseOffs == 0; 1659193323Sed } 1660193323Sed} 1661193323Sed 1662193323Sed//===----------------------------------------------------------------------===// 1663193323Sed// XCore Inline Assembly Support 1664193323Sed//===----------------------------------------------------------------------===// 1665193323Sed 1666224145Sdimstd::pair<unsigned, const TargetRegisterClass*> 1667224145SdimXCoreTargetLowering:: 1668224145SdimgetRegForInlineAsmConstraint(const std::string &Constraint, 1669263508Sdim MVT VT) const { 1670224145Sdim if (Constraint.size() == 1) { 1671224145Sdim switch (Constraint[0]) { 1672193323Sed default : break; 1673193323Sed case 'r': 1674239462Sdim return std::make_pair(0U, &XCore::GRRegsRegClass); 1675224145Sdim } 1676193323Sed } 1677224145Sdim // Use the default implementation in TargetLowering to convert the register 1678224145Sdim // constraint into a member of a register class. 1679224145Sdim return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 1680193323Sed} 1681