Searched defs:Incr (Results 1 - 10 of 10) sorted by relevance
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARC/ |
| H A D | ARCOptAddrMode.cpp | 221 int64_t Incr; local
342 canFixPastUses(const ArrayRef<MachineInstr *> &Uses, MachineOperand &Incr, unsigned BaseReg) argument
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsExpandPseudo.cpp | 412 Register Incr = I->getOperand(2).getReg(); local
634 Register Incr = I->getOperand(2).getReg(); local
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| H A D | MipsISelLowering.cpp | 1551 Register Incr = MI.getOperand(2).getReg(); local
1662 Register Incr = MI.getOperand(2).getReg(); local
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/AsmPrinter/ |
| H A D | DwarfUnit.cpp | 521 int Incr = (LittleEndian ? 1 : -1); local
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonVLIWPacketizer.cpp | 530 int Incr; local
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
| H A D | SLPVectorizer.cpp | 1833 int incrementUnscheduledDeps(int Incr) { argument
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 2461 int SubReg = 0, End = NumRegs, Incr = 1; local
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 2846 emitMaskedAtomicRMWIntrinsic( IRBuilder< &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const argument
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| /freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 1730 emitMaskedAtomicRMWIntrinsic(IRBuilder< &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const argument
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | LoopStrengthReduce.cpp | 2143 BinaryOperator *Incr = local
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