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/haiku/headers/private/graphics/intel_extreme/ | ||
H A D | intel_extreme.h | diff efde34c2 Mon Nov 22 04:14:12 MST 2021 Rudolf Cornelissen <rudhaiku@gmail.com> intel_extreme: add haswell/skylake PLL calcs, no functional change yet. diff c7d83a17 Sat May 29 02:36:22 MDT 2021 Rudolf Cornelissen <rudhaiku@gmail.com> Intel_extreme: fixed DPLL pgming (Sandy+), prevent black display by not killing PIPE (Ivy+). Chkd GMA(Q33G/Q45) OK. Added defines. diff 22ec6455 Fri Mar 13 02:47:36 MDT 2020 Adrien Destugues <pulkomandy@pulkomandy.tk> intel_extreme: some minor fixes - Cleanup HEAD_MODE constants. These should be completely removed, now that we have a proper notion of pipes and displays. But the DPMS code still uses them, for now. - Fix the ie_pipe command where width and height were swapped and missing a +1 to show the actual videomode values diff 8fe50548 Sun May 08 14:39:22 MDT 2016 Alexander von Gluck IV <kallisti5@unixzen.com> intel_extreme: Extend DDI port probing to A-E * The Linux code made this a bit hard to figure out via complex define functions, however there can be up to 5 DDI ports (A-E) diff 8d1cb54a Fri Apr 22 21:41:52 MDT 2016 Alexander von Gluck IV <kallisti5@unixzen.com> intel_extreme: Add in some code for the lakes (unused) diff 00e0982f Tue Nov 17 22:28:09 MST 2015 Alexander von Gluck IV <kallisti5@unixzen.com> intel_extreme: First work at programming FDI diff 61fbdb06 Sun Nov 08 22:14:46 MST 2015 Alexander von Gluck IV <kallisti5@unixzen.com> intel_extreme: Set mode and pll via pipe-aware class functions diff fb255821 Wed Nov 04 15:11:22 MST 2015 Alexander von Gluck IV <kallisti5@unixzen.com> intel_extreme: Correct generations based on some Intel help diff e747cbe1 Fri Oct 23 22:59:08 MDT 2015 Alexander von Gluck IV <kallisti5@unixzen.com> intel_extreme: Fix regs, remove PCH for VLV, Expand Type * Fix some incorrect HDMI reg locations * PCH goes away on later Intel chips * Add more mask room for Intel Groups diff 97aa078e Thu Oct 15 22:37:18 MDT 2015 Alexander von Gluck IV <kallisti5@unixzen.com> intel_extreme: Intial work for ValleyView support * No impact to non-ValleyView chipsets * Bump some register locations for VLV * Only have HDMI port to test with on my ValleyView GPU and our driver seems to be missing all HDMI and sideband functionality. * As ValleyView chipsets seem to be UEFI only, we don't have VESA fallback, so this shouldn't cause regressions. (unless we get UEFI framebuffer support) |
/haiku/src/add-ons/kernel/drivers/graphics/intel_extreme/ | ||
H A D | intel_extreme.cpp | diff 69cab3d4 Tue Mar 22 11:21:11 MDT 2022 Jérôme Duval <jerome.duval@gmail.com> intel_extreme: remove gen8 interrupt handler on exit should fix #17535 Change-Id: I09d62090c68bd50494ca168d92d3df7b0c6fd0b4 Reviewed-on: https://review.haiku-os.org/c/haiku/+/5138 Reviewed-by: waddlesplash <waddlesplash@gmail.com> Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org> diff fb255821 Wed Nov 04 15:11:22 MST 2015 Alexander von Gluck IV <kallisti5@unixzen.com> intel_extreme: Correct generations based on some Intel help diff e747cbe1 Fri Oct 23 22:59:08 MDT 2015 Alexander von Gluck IV <kallisti5@unixzen.com> intel_extreme: Fix regs, remove PCH for VLV, Expand Type * Fix some incorrect HDMI reg locations * PCH goes away on later Intel chips * Add more mask room for Intel Groups diff c7af18fd Wed Oct 21 22:46:30 MDT 2015 Alexander von Gluck IV <kallisti5@unixzen.com> drivers/intel_extreme: Fix ValleyView block offsets diff 97aa078e Thu Oct 15 22:37:18 MDT 2015 Alexander von Gluck IV <kallisti5@unixzen.com> intel_extreme: Intial work for ValleyView support * No impact to non-ValleyView chipsets * Bump some register locations for VLV * Only have HDMI port to test with on my ValleyView GPU and our driver seems to be missing all HDMI and sideband functionality. * As ValleyView chipsets seem to be UEFI only, we don't have VESA fallback, so this shouldn't cause regressions. (unless we get UEFI framebuffer support) diff e71af5ae Mon Dec 31 15:35:22 MST 2012 Alexander von Gluck IV <kallisti5@unixzen.com> intel_extreme: Add RC6 downclocking support * Generation 6 (SandyBridge) and later support automatic downclocking of the GPU offering substantial battery use reductions. * As we're playing with fire here, only use on mobile devices SandyBridge or later. * This is testing stable on my SandyBridge laptop, however I need further confirmation of the functionality of this. * Move clock gating into a function in the power.cpp file diff 5af5259c Sat May 13 09:22:20 MDT 2006 Axel Dörfler <axeld@pinc-software.de> Implemented vblank interrupt and support for the retrace semaphore - not yet tested, though. git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@17439 a95241bf-73f2-0310-859d-f6bbb57e9c96 diff 030d964e Thu May 11 09:22:35 MDT 2006 Axel Dörfler <axeld@pinc-software.de> Made the primary ring buffer for the acceleration commands a bit larger (16 KB); this is mostly done because of the fact that I haven't tested how full it usually is, and since I haven't implemented checking for free space yet... git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@17423 a95241bf-73f2-0310-859d-f6bbb57e9c96 diff 22d4db92 Wed Apr 26 11:50:30 MDT 2006 Axel Dörfler <axeld@pinc-software.de> * Added overlay register definitions. * The overlay register update buffer is now created and exported, ready to be used. git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@17244 a95241bf-73f2-0310-859d-f6bbb57e9c96 diff 22d4db92 Wed Apr 26 11:50:30 MDT 2006 Axel Dörfler <axeld@pinc-software.de> * Added overlay register definitions. * The overlay register update buffer is now created and exported, ready to be used. git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@17244 a95241bf-73f2-0310-859d-f6bbb57e9c96 |
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