Searched hist:312399 (Results 1 - 7 of 7) sorted by relevance
| /freebsd-11-stable/sys/dev/ichiic/ | ||
| H A D | ig4_pci.c | diff 312399 Wed Jan 18 23:34:37 MST 2017 marius MFC: r310309, r310340-310341, r311664, r311793-r311794 o sdhci/mmc: Minor whitespace cleanups o Add Braswell PCI IDs for Intel Cherryview o mmc: Accept even lower voltage for Cherryview And HP x2 210, per DragonFlyBSD 240bd9cd58f8259c12c14a8006837e698. o In mmcsd_task(), bio_resid was not being set to 0 on a successful read or write, resulting in random short-read and short-write returns for requests. Fixing this fixes nominal block I/O via mmcsd(4). Obtained from: DragonFlyBSD (fd4b97583be1a1e57234713c25f6e81bc0411cb0) o Add support for Intel Apollo Lake and Bay Trail eMMC PCI controllers. o Flesh out the support for Intel Braswell eMMC controllers further. o In sdhci_init_slot(), use the right capability field for determining the announced bus width based on MMC_CAP_*_BIT_DATA. |
| /freebsd-11-stable/sys/dev/mmc/ | ||
| H A D | mmcreg.h | diff 312399 Wed Jan 18 23:34:37 MST 2017 marius MFC: r310309, r310340-310341, r311664, r311793-r311794 o sdhci/mmc: Minor whitespace cleanups o Add Braswell PCI IDs for Intel Cherryview o mmc: Accept even lower voltage for Cherryview And HP x2 210, per DragonFlyBSD 240bd9cd58f8259c12c14a8006837e698. o In mmcsd_task(), bio_resid was not being set to 0 on a successful read or write, resulting in random short-read and short-write returns for requests. Fixing this fixes nominal block I/O via mmcsd(4). Obtained from: DragonFlyBSD (fd4b97583be1a1e57234713c25f6e81bc0411cb0) o Add support for Intel Apollo Lake and Bay Trail eMMC PCI controllers. o Flesh out the support for Intel Braswell eMMC controllers further. o In sdhci_init_slot(), use the right capability field for determining the announced bus width based on MMC_CAP_*_BIT_DATA. |
| H A D | mmcsd.c | diff 312399 Wed Jan 18 23:34:37 MST 2017 marius MFC: r310309, r310340-310341, r311664, r311793-r311794 o sdhci/mmc: Minor whitespace cleanups o Add Braswell PCI IDs for Intel Cherryview o mmc: Accept even lower voltage for Cherryview And HP x2 210, per DragonFlyBSD 240bd9cd58f8259c12c14a8006837e698. o In mmcsd_task(), bio_resid was not being set to 0 on a successful read or write, resulting in random short-read and short-write returns for requests. Fixing this fixes nominal block I/O via mmcsd(4). Obtained from: DragonFlyBSD (fd4b97583be1a1e57234713c25f6e81bc0411cb0) o Add support for Intel Apollo Lake and Bay Trail eMMC PCI controllers. o Flesh out the support for Intel Braswell eMMC controllers further. o In sdhci_init_slot(), use the right capability field for determining the announced bus width based on MMC_CAP_*_BIT_DATA. |
| H A D | mmc.c | diff 312399 Wed Jan 18 23:34:37 MST 2017 marius MFC: r310309, r310340-310341, r311664, r311793-r311794 o sdhci/mmc: Minor whitespace cleanups o Add Braswell PCI IDs for Intel Cherryview o mmc: Accept even lower voltage for Cherryview And HP x2 210, per DragonFlyBSD 240bd9cd58f8259c12c14a8006837e698. o In mmcsd_task(), bio_resid was not being set to 0 on a successful read or write, resulting in random short-read and short-write returns for requests. Fixing this fixes nominal block I/O via mmcsd(4). Obtained from: DragonFlyBSD (fd4b97583be1a1e57234713c25f6e81bc0411cb0) o Add support for Intel Apollo Lake and Bay Trail eMMC PCI controllers. o Flesh out the support for Intel Braswell eMMC controllers further. o In sdhci_init_slot(), use the right capability field for determining the announced bus width based on MMC_CAP_*_BIT_DATA. |
| /freebsd-11-stable/sys/dev/sdhci/ | ||
| H A D | sdhci.h | diff 312399 Wed Jan 18 23:34:37 MST 2017 marius MFC: r310309, r310340-310341, r311664, r311793-r311794 o sdhci/mmc: Minor whitespace cleanups o Add Braswell PCI IDs for Intel Cherryview o mmc: Accept even lower voltage for Cherryview And HP x2 210, per DragonFlyBSD 240bd9cd58f8259c12c14a8006837e698. o In mmcsd_task(), bio_resid was not being set to 0 on a successful read or write, resulting in random short-read and short-write returns for requests. Fixing this fixes nominal block I/O via mmcsd(4). Obtained from: DragonFlyBSD (fd4b97583be1a1e57234713c25f6e81bc0411cb0) o Add support for Intel Apollo Lake and Bay Trail eMMC PCI controllers. o Flesh out the support for Intel Braswell eMMC controllers further. o In sdhci_init_slot(), use the right capability field for determining the announced bus width based on MMC_CAP_*_BIT_DATA. |
| H A D | sdhci_pci.c | diff 312399 Wed Jan 18 23:34:37 MST 2017 marius MFC: r310309, r310340-310341, r311664, r311793-r311794 o sdhci/mmc: Minor whitespace cleanups o Add Braswell PCI IDs for Intel Cherryview o mmc: Accept even lower voltage for Cherryview And HP x2 210, per DragonFlyBSD 240bd9cd58f8259c12c14a8006837e698. o In mmcsd_task(), bio_resid was not being set to 0 on a successful read or write, resulting in random short-read and short-write returns for requests. Fixing this fixes nominal block I/O via mmcsd(4). Obtained from: DragonFlyBSD (fd4b97583be1a1e57234713c25f6e81bc0411cb0) o Add support for Intel Apollo Lake and Bay Trail eMMC PCI controllers. o Flesh out the support for Intel Braswell eMMC controllers further. o In sdhci_init_slot(), use the right capability field for determining the announced bus width based on MMC_CAP_*_BIT_DATA. |
| H A D | sdhci.c | diff 312399 Wed Jan 18 23:34:37 MST 2017 marius MFC: r310309, r310340-310341, r311664, r311793-r311794 o sdhci/mmc: Minor whitespace cleanups o Add Braswell PCI IDs for Intel Cherryview o mmc: Accept even lower voltage for Cherryview And HP x2 210, per DragonFlyBSD 240bd9cd58f8259c12c14a8006837e698. o In mmcsd_task(), bio_resid was not being set to 0 on a successful read or write, resulting in random short-read and short-write returns for requests. Fixing this fixes nominal block I/O via mmcsd(4). Obtained from: DragonFlyBSD (fd4b97583be1a1e57234713c25f6e81bc0411cb0) o Add support for Intel Apollo Lake and Bay Trail eMMC PCI controllers. o Flesh out the support for Intel Braswell eMMC controllers further. o In sdhci_init_slot(), use the right capability field for determining the announced bus width based on MMC_CAP_*_BIT_DATA. |
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