MFC: r333647, r338275, r338280, r338513

- If present, take advantage of the R/W cache of eMMC revision 1.5 and
later devices. These caches work akin to the ones found in HDDs/SSDs
that ada(4)/da(4) also enable if existent, but likewise increase the
likelihood of data loss in case of a sudden power outage etc. On the
other hand, write performance is up to twice as high for e. g. 1 GiB
files depending on the actual chip and transfer mode employed.
For maximum data integrity, the usage of eMMC caches can be disabled
via the hw.mmcsd.cache tunable.
- Get rid of the NOP mmcsd_open().
- Obtain the bus mode (MMC or SD) from the directly superordinated
bus rather than reaching up to the bridge and use the cached mode
in mmcsd_delete(), too.
- Use le32dec(9) for decoding EXT_CSD values where it makes sense. [1]
- Locally cache some instance variable values in mmc_discover_cards()
in order to improve the code readability a bit.

Obtained from: NetBSD [1]

Revert r330897:

This was intended to be a non-functional change. It wasn't. The commit
message was thus wrong. In addition it broke arm, and merged crypto
related code.

Revert with prejudice.

This revert skips files touched in r316370 since that commit was since
MFCed. This revert also skips files that require $FreeBSD$ property
changes.

Thank you to those who helped me get out of this mess including but not
limited to gonzo, kevans, rgrimes.

Requested by: gjb (re)

Partial merge of the SPDX changes

These changes are incomplete but are making it difficult
to determine what other changes can/should be merged.

No objections from: pfg

MFC: r322209

- If available, use TRIM instead of ERASE for implementing BIO_DELETE.
This also involves adding a quirk table as TRIM is broken for some
Kingston eMMC devices, though. Compared to ERASE (declared "legacy"
in the eMMC specification v5.1), TRIM has the advantage of operating
on write sectors rather than on erase sectors, which typically are
of a much larger size. Thus, employing TRIM, we don't need to fiddle
with coalescing BIO_DELETE requests that are also of (write) sector
units into erase sectors, which might not even add up in all cases.
- For some SanDisk iNAND devices, the CMD38 argument, e. g. ERASE,
TRIM etc., has to be specified via EXT_CSD[113], which now is also
handled via a quirk.
- My initial understanding was that for eMMC partitions, the granularity
should be used as erase sector size, e. g. 128 KB for boot partitions.
However, rereading the relevant parts of the eMMC specification v5.1,
this isn't actually correct. So drop the code which used partition
granularities for delmaxsize and stripesize. For the most part, this
change is a NOP, though, because a) for ERASE, mmcsd_delete() used
the erase sector size unconditionally for all partitions anyway and
b) g_disk_limit() doesn't actually take the stripesize into account.
- Take some more advantage of mmcsd_errmsg() in mmcsd(4) for making
error codes human readable.

MFC: r319350, r321385, r321490, r321588, r321948

o Use SDHCI_CAN_DRIVE_TYPE_{A,C,D} to check for driver type support in
SDHCI_CAPABILITIES2 instead of SDHCI_CTRL2_DRIVER_TYPE_{A,C,D} which
are meant for setting the driver type in SDHCI_HOST_CONTROL2.

o Add support for eMMC HS200 and HS400 bus speed modes at 200 MHz to
sdhci(4), mmc(4) and mmcsd(4).

On the system where the addition of DDR52 support increased the read
throughput to ~80 MB/s (from ~45 MB/s at high speed), HS200 yields
~154 MB/s and HS400 ~187 MB/s, i. e. performance now has more than
quadrupled compared to pre-r315598 (pre-r318494 in stable/11).

However, in fact this isn't a feature-only change; there are boards
based on Intel Bay Trail where DDR52 is problematic and the suggested
workaround is to use HS200 mode instead. So far exact details are
unknown, however, i. e. whether that's due to a defect in these SoCs
or on the boards.

Moreover, due to the above changes requiring to be aware of possible
MMC siblings in the fast path of mmc(4), corresponding information
now is cached in mmc_softc. As a side-effect, mmc_calculate_clock(),
now longer will trigger a panic in low memory situations and all of
mmc(4) operate on the same set of child devices.

o Fix a bug in the failure reporting of mmcsd_delete() that could lead
to a panic.

o Fix 2 bugs on resume, one in mmcsd(4) that could lead to a panic and
another one in mmc(4) that could lead to devices no longer working.

o Fix a memory leak in mmcsd_ioctl() in case copyin(9) fails. [1]

o Fix missing variable initialization in mmc_switch_status(). [2]

o Fix R1_SWITCH_ERROR detection in mmc_switch_status(). [3]

o Handle the case of device_add_child(9) failing, for example due to
a memory shortage, gracefully in mmc(4) and sdhci(4), including not
leaking memory for the instance variables in case of mmc(4), also
fixing [4].

o Correctly use the size of a pointer rather than that of a pointer to
a pointer (this bug was present in head r321385 only, i. e. not in a
stable branch). [5]

o Handle the case of an unknown SD CSD version in mmc_decode_csd_sd()
gracefully instead of calling panic(9).

o Again, check and handle the return values of some additional function
calls in mmc(4) instead of assuming that everything went right or mark
non-fatal errors by casting the return value to void.

o Correct a typo in the Linux IOCTL compatibility; it should have been
MMC_IOC_MULTI_CMD rather than MMC_IOC_CMD_MULTI.

o Now that we are reaching ever faster speeds (more improvement in this
regard is to be expected when adding ADMA support to sdhci(4)), apply
a few micro-optimizations to mmc(4), mmcsd(4) and sdhci(4).

o Correct confusing and error prone mix-ups between "br" or "bridge" in
mmc(4) and mmcsd(4) where - according to the terminology outlined in
comments of bridge.h and mmcbr_if.m around since their addition in
r163516 - the bus is meant and used instead.

o Remove comment lines from bridge.h incorrectly suggesting that there
would be a MMC bridge base class driver.

o Update comments in bridge.h regarding the star topology of SD and SDIO;
since version 3.00 of the SDHCI specification, for eSD and eSDIO bus
topologies are actually possible in form of so called "shared buses"
(in some subcontext later on renamed to "embedded" buses).

Reported by: Coverity
CID: 1372612 [1], 1372624 [2], 1372594 [3], 1007069 [4],
1378432 [5]

MFC: r315598

o Add support for eMMC DDR bus speed mode up to 52 MHz to sdhci(4)
and mmc(4). Given that support for DDR52 is not denoted by SDHCI
capability registers, availability of that timing is indicated by
a new quirk SDHCI_QUIRK_MMC_DDR52 and only enabled for Intel SDHCI
controllers so far.

Compared to 50 MHz at SDR high speed typically yielding ~45 MB/s
read throughput with the eMMC chips tested, read performance goes
up to ~80 MB/s at DDR52.

As a side-effect, this change also fixes communication with some
eMMC devices at SDR high speed mode due to the signaling voltage
and UHS bits in the SDHCI controller no longer being left in an
inappropriate state.

o In sdhci(4), add two tunables hw.sdhci.quirk_clear as well as
hw.sdhci.quirk_set, which (when hooked up in the front-end)
allow to set/clear sdhci(4) quirks for debugging and testing
purposes. However, especially for SDHCI controllers on the
PCI bus which have no specific support code so far and, thus,
are picked up as generic SDHCI controllers, hw.sdhci.quirk_set
allows for setting the necessary quirks (if required).

o In mmc(4), check and handle the return values of some more
function calls instead of assuming that everything went right.
In case failures actually are not problematic, indicate that
by casting the return value to void.

MFC: r312939, r313250, r314811 (partial), r314887 (partial), r315760,
r315845, 315430, r317981, r315466

o Fix some overly long lines, whitespace and other bugs according to
style(9) as well as spelling etc. in mmc(4), mmcsd(4) and sdhci(4).

o In the mmc(4) bridges and sdhci(4) (bus) front-ends:
- Remove redundant assignments of the default bus_generic_print_child
device method,
- use DEVMETHOD_END,
- use NULL instead of 0 for pointers.

o Trim/adjust includes.

o Add and use a MMC_DECLARE_BRIDGE macro for declaring mmc(4) bridges
as kernel drivers and their dependency onto mmc(4).

o Add support for eMMC "partitions". Besides the user data area, i. e.
the default partition, eMMC v4.41 and later devices can additionally
provide up to:
1 enhanced user data area partition
2 boot partitions
1 RPMB (Replay Protected Memory Block) partition
4 general purpose partitions (optionally with a enhanced or extended
attribute)

Besides simply subdividing eMMC devices, some Intel NUCs having UEFI
code in the boot partitions etc., another use case for the partition
support is the activation of pseudo-SLC mode, which manufacturers of
eMMC chips typically associate with the enhanced user data area and/
or the enhanced attribute of general purpose partitions.

CAVEAT EMPTOR: Partitioning eMMC devices is a one-time operation.

o Now that properly issuing CMD6 is crucial (so data isn't written to
the wrong partition for example), make a step into the direction of
correctly handling the timeout for these commands in the MMC layer.
Also, do a SEND_STATUS when CMD6 is invoked with an R1B response as
recommended by relevant specifications.

o Add an IOCTL interface to mmcsd(4); this is sufficiently compatible
with Linux so that the GNU mmc-utils can be ported to and used with
FreeBSD (note that due to the remaining deficiencies outlined above
SANITIZE operations issued by/with `mmc` currently most likely will
fail). These latter have been added to ports as sysutils/mmc-utils.
Among others, the `mmc` tool of mmc-utils allows for partitioning
eMMC devices (tested working).

o For devices following the eMMC specification v4.41 or later, year 0
is 2013 rather than 1997; so correct this for assembling the device
ID string properly.

o Let mmcsd.ko depend on mmc.ko. Additionally, bump MMC_VERSION as at
least for some of the above a matching pair is required.

o In the ACPI front-end of sdhci(4) describe the Intel eMMC and SDXC
controllers as such in order to match the PCI one.
Additionally, in the entry for the 80860F14 SDXC controller remove
the eMMC-only SDHCI_QUIRK_INTEL_POWER_UP_RESET.

MFC: r310309, r310340-310341, r311664, r311793-r311794

o sdhci/mmc: Minor whitespace cleanups

o Add Braswell PCI IDs for Intel Cherryview

o mmc: Accept even lower voltage for Cherryview

And HP x2 210, per DragonFlyBSD 240bd9cd58f8259c12c14a8006837e698.

o In mmcsd_task(), bio_resid was not being set to 0 on a successful read
or write, resulting in random short-read and short-write returns for
requests. Fixing this fixes nominal block I/O via mmcsd(4).

Obtained from: DragonFlyBSD (fd4b97583be1a1e57234713c25f6e81bc0411cb0)

o Add support for Intel Apollo Lake and Bay Trail eMMC PCI controllers.

o Flesh out the support for Intel Braswell eMMC controllers further.

o In sdhci_init_slot(), use the right capability field for determining
the announced bus width based on MMC_CAP_*_BIT_DATA.

Copy head@r302406 to stable/11 as part of the 11.0-RELEASE cycle.
Prune svn:mergeinfo from the new branch, as nothing has been merged
here.

Additional commits post-branch will follow.

Approved by: re (implicit)
Sponsored by: The FreeBSD Foundation

sys/dev: minor spelling fixes.

Most affect comments, very few have user-visible effects.

Use correct response bits for MMC_RSP_R4-R7 types

Fix highest voltage detection

Submitted by: Daisuke Aoyama <aoyama at peach.ne.jp>
Approved by: imp@

o Fixes:
- When switching to 4-bit operation, send a SET_CLR_CARD_DETECT command
to disconnect the card-detect pull-up resistor from the DAT3 line before
sending the SET_BUS_WIDTH command.
- Add the missing "reserved" zero entry to the mantissa table used to
decode various CSD fields. This was causing SD cards to report that they
could run at 30 MHz instead of the maximum 25 MHz mandated in the spec.
o Enhancements:
- At the MMC layer, format various info from the CID into a string that
uniquely identifies the card instance (manufacturer number, serial
number, product name and revision, etc). Export it as an instance
variable.
- At the MMCSD layer, display the formatted card ID string, and also
report the clock speed of the hardware (not the card's max speed), and
the number of bits and number of blocks per transfer. It comes out like
this now:
mmcsd0: 968MB <SD SD01G 8.0 SN 276886905 MFG 08/2008 by 3 SD> at mmc0
22.5MHz/4bit/128-block
o Use DEVMETHOD_END.
o Use NULL instead of 0 for pointers.

PR: 156496
Submitted by: Ian Lepore
MFC after: 1 week

o Define some symbols for a few items that are bare constants in the
code.
o Use NULL in preference to 0 for a few pointers.
o default to bus timing normal, like we default to bus_width_1.

Implement BIO_DELETE command with MMC and SD erase commands.

Erase operation gives card's logic information about unused areas to help it
implement wear-leveling with lower overhead comparing to usual writing.
Erase is much faster then write and does not depends on data bus speed.
Also as result of hitting in-card write logic optimizations I have measured
up to 50% performance boost on writing undersized blocks into preerased areas.

At the same time there are strict limitations on size and allignment of erase
operations. We can erase only blocks aligned to the erase sector size and
with size multiple of it. Different cards has different erase sector size
which usually varies from 64KB to 4MB. SD cards actually allow to erase
smaller blocks, but it is much more expensive as it is implemented via
read-erase-write sequence and so not sutable for the BIO_DELETE purposes.

Reviewed by: imp@

Set of mmc layer improvements:
- add MMC support.
- add SDHC support.
- add 4 and 8 bit bus width support.
- add High Speed bus timing support.

Define and use MMC_SECTOR_SIZE.
Make mmc_get_media_size now return an off_t and remove now useless cast.

Minor style fixes from mav@ (with similar problems fixed where I noticed
them):
#define<tab>
zero memory when we allocate it
Put device name in error message.

Submitted by: mav@

The OCR register defines both acceptable voltage bits, as well as bits
for other things. Mask out the voltage only bits when returning the
Vdd mask for voltage computation.

Submitted by: mav@

A careful reading of the disclaimer that is required to download the
SD Simplified specification, as well as other SD and SDIO
implemenations I've examined, suggest this disclaimer may be required.
It is unclear to me exactly what the license would be for, or why it
might be required. Err on the side of caution and include this
disclaimer so anybody deploying this code can judge for themselves. I
have no further unformation about the details.

Preliminary MMC stack. This stack supports SD 1.0 cards only, but
should be easily adapted to SD 2.0 (aka SDHC), SDIO, MMC and MMCplus
cards. At the present time, there's only one bridge driver for the
ARM9 based Atmel AT91RM9200.