/freebsd-10.0-release/contrib/llvm/tools/lldb/source/Interpreter/ |
H A D | CommandObject.cpp | 342 bool operator() (const std::pair<std::string, lldb::CommandObjectSP> map_element) const argument [all...] |
/freebsd-10.0-release/contrib/llvm/utils/TableGen/ |
H A D | FixedLenDecoderEmitter.cpp | 345 FilterChooser(const std::vector<const CodeGenInstruction*> &Insts, const std::vector<unsigned> &IDs, const std::map<unsigned, std::vector<OperandInfo> > &Ops, unsigned BW, const FixedLenDecoderEmitter *E) argument 358 FilterChooser(const std::vector<const CodeGenInstruction*> &Insts, const std::vector<unsigned> &IDs, const std::map<unsigned, std::vector<OperandInfo> > &Ops, const std::vector<bit_value_t> &ParentFilterBitValues, const FilterChooser &parent) argument [all...] |
H A D | DAGISelMatcher.h | 529 SwitchTypeMatcher(const std::pair<MVT::SimpleValueType, Matcher*> *cases, unsigned numcases) argument [all...] |
/freebsd-10.0-release/sys/contrib/octeon-sdk/ |
H A D | cvmx-eoi-defs.h | 666 uint64_t std : 5; /**< Number of outstanding store data accepted by EOI on member in struct:cvmx_eoi_throttle_ctl::cvmx_eoi_throttle_ctl_s
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/freebsd-10.0-release/sys/dev/bktr/ |
H A D | msp34xx.c | 939 int mode,val,i,std; local [all...] |
/freebsd-10.0-release/contrib/gcclibs/libcpp/include/ |
H A D | cpplib.h | 371 unsigned char std; member in struct:cpp_options
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/freebsd-10.0-release/contrib/llvm/lib/TableGen/ |
H A D | Record.cpp | 1565 get(Init *V, const std::string &VN, const std::vector<std::pair<Init*, std::string> > &args) argument [all...] |
/freebsd-10.0-release/contrib/llvm/tools/clang/lib/Frontend/ |
H A D | CompilerInstance.cpp | 754 operator ()(const std::pair<std::string, bool> &def) const argument [all...] |
/freebsd-10.0-release/sys/dev/drm2/ |
H A D | drm_edid.c | 1168 struct std_timing *std; local
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/freebsd-10.0-release/sys/dev/usb/controller/ |
H A D | ehci.c | 942 _ehci_append_fs_td(ehci_sitd_t *std, ehci_sitd_t *last) argument 968 _ehci_append_hs_td(ehci_itd_t *std, ehci_itd_t *last) argument 1026 _ehci_remove_fs_td(ehci_sitd_t *std, ehci_sitd_t *last) argument 1046 _ehci_remove_hs_td(ehci_itd_t *std, ehci_itd_t *last) argument [all...] |
H A D | ohci.c | 530 ohci_dump_tds(ohci_td_t *std) argument 540 ohci_dump_td(ohci_td_t *std) argument [all...] |
H A D | uhci.c | 897 _uhci_append_td(uhci_td_t *std, uhci_td_t *last) argument 959 _uhci_remove_td(uhci_td_t *std, uhci_td_t *last) argument [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Transforms/ObjCARC/ |
H A D | ObjCARCOpts.cpp | 98 insert(const std::pair<KeyT, ValueT> &InsertPair) { argument [all...] |
/freebsd-10.0-release/contrib/llvm/tools/lldb/source/Core/ |
H A D | ValueObject.cpp | 539 ValueObject::GetChildAtIndexPath (const std::initializer_list< std::pair<size_t, bool> >& idxs, argument 579 ValueObject::GetChildAtIndexPath (const std::vector< std::pair<size_t, bool> > &idxs, argument [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/Mips/ |
H A D | MipsISelLowering.cpp | 2195 getOpndList(SmallVectorImpl<SDValue> &Ops, std::deque< std::pair<unsigned, SDValue> > &RegsToPass, bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const argument 3280 passByValArg(SDValue Chain, DebugLoc DL, std::deque< std::pair<unsigned, SDValue> > &RegsToPass, SmallVector<SDValue, 8> &MemOpChains, SDValue StackPtr, MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, const MipsCC &CC, const ByValArgInfo &ByVal, const ISD::ArgFlagsTy &Flags, bool isLittle) const argument [all...] |
/freebsd-10.0-release/contrib/llvm/tools/clang/lib/Sema/ |
H A D | SemaStmt.cpp | 515 bool operator()(const std::pair<llvm::APSInt, CaseStmt*> &LHS, argument 519 bool operator()(const std::pair<llvm::APSInt, CaseStmt*> &LHS, argument 532 static bool CmpCaseVals(const std::pair<llvm::APSInt, CaseStmt*>& lhs, argument 546 static bool CmpEnumVals(const std::pair<llvm::APSInt, EnumConstantDecl*>& lhs, argument 554 static bool EqEnumVals(const std::pair<llvm::APSInt, EnumConstantDecl*>& lhs, argument 523 operator ()(const llvm::APSInt &LHS, const std::pair<llvm::APSInt, CaseStmt*> &RHS) argument [all...] |
/freebsd-10.0-release/contrib/sendmail/src/ |
H A D | map.c | 1417 struct stat std, stp; local
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/freebsd-10.0-release/contrib/llvm/tools/clang/lib/Serialization/ |
H A D | ASTWriter.cpp | 59 static StringRef data(const std::vector<T, Allocator> &v) { argument [all...] |
H A D | ASTReader.cpp | 722 ReadDeclContextStorage(ModuleFile &M, BitstreamCursor &Cursor, const std::pair<uint64_t, uint64_t> &Offsets, DeclContextInfo &Info) argument [all...] |
/freebsd-10.0-release/contrib/llvm/lib/CodeGen/SelectionDAG/ |
H A D | DAGCombiner.cpp | 7539 ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo, SDValue IVal, StoreSDNode *St, DAGCombiner *DC) argument [all...] |
/freebsd-10.0-release/contrib/llvm/tools/clang/include/clang/AST/ |
H A D | Type.h | [all...] |
/freebsd-10.0-release/sys/contrib/ngatm/netnatm/msg/ |
H A D | unistruct.h | 1024 enum uni_git_std std; /* identifier related standard/application */ member in struct:uni_ie_git
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/freebsd-10.0-release/sys/contrib/v4l/ |
H A D | videodev2.h | 852 v4l2_std_id std; member in struct:v4l2_input 900 v4l2_std_id std; member in struct:v4l2_output
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/freebsd-10.0-release/contrib/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 6407 assert(Idx < 8 && �); if (Idx < 4) { Locs[i] = std::make_pair(0, NumLo); Mask1[NumLo] = Idx; NumLo++; } else { Locs[i] = std::make_pair(1, NumHi); if (2+NumHi < 4) Mask1[2+NumHi] = Idx; NumHi++; } } } if (NumLo <= 2 && NumHi <= 2) { V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); int Mask2[] = { -1, -1, -1, -1 }; for (unsigned i = 0; i != 4; ++i) if (Locs[i].first != -1) { unsigned Idx = (i < 2) ? 0 : 4; Idx += Locs[i].first * 2 + Locs[i].second; Mask2[i] = Idx; } return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]); } if (NumLo == 3 || NumHi == 3) { if (NumHi == 3) { CommuteVectorShuffleMask(PermMask, 4); std::swap(V1, V2); } unsigned HiIndex; for (HiIndex = 0; HiIndex < 3; ++HiIndex) { int Val = PermMask[HiIndex]; if (Val < 0) continue; if (Val >= 4) break; } Mask1[0] = PermMask[HiIndex]; Mask1[1] = -1; Mask1[2] = PermMask[HiIndex^1]; Mask1[3] = -1; V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); if (HiIndex >= 2) { Mask1[0] = PermMask[0]; Mask1[1] = PermMask[1]; Mask1[2] = HiIndex & 1 ? 6 : 4; Mask1[3] = HiIndex & 1 ? 4 : 6; return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); } Mask1[0] = HiIndex & 1 ? 2 : 0; Mask1[1] = HiIndex & 1 ? 0 : 2; Mask1[2] = PermMask[2]; Mask1[3] = PermMask[3]; if (Mask1[2] >= 0) Mask1[2] += 4; if (Mask1[3] >= 0) Mask1[3] += 4; return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]); } int LoMask[] = { -1, -1, -1, -1 }; int HiMask[] = { -1, -1, -1, -1 }; int *MaskPtr = LoMask; unsigned MaskIdx = 0; unsigned LoIdx = 0; unsigned HiIdx = 2; for (unsigned i = 0; i != 4; ++i) { if (i == 2) { MaskPtr = HiMask; MaskIdx = 1; LoIdx = 0; HiIdx = 2; } int Idx = PermMask[i]; if (Idx < 0) { Locs[i] = std::make_pair(-1, -1); } else if (Idx < 4) { Locs[i] = std::make_pair(MaskIdx, LoIdx); MaskPtr[LoIdx] = Idx; LoIdx++; } else { Locs[i] = std::make_pair(MaskIdx, HiIdx); MaskPtr[HiIdx] = Idx; HiIdx++; } } SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]); SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]); int MaskOps[] = { -1, -1, -1, -1 }; for (unsigned i = 0; i != 4; ++i) if (Locs[i].first != -1) MaskOps[i] = Locs[i].first * 4 + Locs[i].second; return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]); } static bool MayFoldVectorLoad(SDValue V) { while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) V = V.getOperand(0); if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR) V = V.getOperand(0); if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR && V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF) V = V.getOperand(0); return MayFoldLoad(V); } static SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) { EVT VT = Op.getValueType(); V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1); return DAG.getNode(ISD::BITCAST, dl, VT, getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64, V1, DAG)); } static SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) { SDValue V1 = Op.getOperand(0); SDValue V2 = Op.getOperand(1); EVT VT = Op.getValueType(); assert(VT != MVT::v2i64 && �); if (HasSSE2 && VT == MVT::v2f64) return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG); return DAG.getNode(ISD::BITCAST, dl, VT, getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32, DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1), DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG)); } static SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) { SDValue V1 = Op.getOperand(0); SDValue V2 = Op.getOperand(1); EVT VT = Op.getValueType(); assert((VT == MVT::v4i32 || VT == MVT::v4f32) && �); if (V2.getOpcode() == ISD::UNDEF) V2 = V1; return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG); } static SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) { SDValue V1 = Op.getOperand(0); SDValue V2 = Op.getOperand(1); EVT VT = Op.getValueType(); unsigned NumElems = VT.getVectorNumElements(); bool CanFoldLoad = false; if (MayFoldVectorLoad(V2)) CanFoldLoad = true; else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op)) CanFoldLoad = true; ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); if (CanFoldLoad) { if (HasSSE2 && NumElems == 2) return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG); if (NumElems == 4) if (SVOp->getMaskElt(1) != -1) return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG); } if (HasSSE2) { if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT)) return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG); } assert(VT != MVT::v4i32 && �); return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1, getShuffleSHUFImmediate(SVOp), DAG); } SDValue X86TargetLowering::LowerVectorIntExtend(SDValue Op, SelectionDAG &DAG) const { if (!Subtarget->hasSSE41()) return SDValue(); EVT VT = Op.getValueType(); if (!Subtarget->hasInt256() && VT.is256BitVector()) return SDValue(); ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); DebugLoc DL = Op.getDebugLoc(); SDValue V1 = Op.getOperand(0); SDValue V2 = Op.getOperand(1); unsigned NumElems = VT.getVectorNumElements(); if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() || VT.getVectorElementType() == MVT::i64) return SDValue(); unsigned Shift = 1; while ((1U << Shift) < NumElems) { if (SVOp->getMaskElt(1U << Shift) == 1) break; Shift += 1; if (Shift > 3) return SDValue(); } unsigned Mask = (1U << Shift) - 1; for (unsigned i = 0; i != NumElems; ++i) { int EltIdx = SVOp->getMaskElt(i); if ((i & Mask) != 0 && EltIdx != -1) return SDValue(); if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift)) return SDValue(); } LLVMContext *Context = DAG.getContext(); unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift; EVT NeVT = EVT::getIntegerVT(*Context, NBits); EVT NVT = EVT::getVectorVT(*Context, NeVT, NumElems >> Shift); if (!isTypeLegal(NVT)) return SDValue(); unsigned SignificantBits = NVT.getSizeInBits() >> Shift; if (V1.getOpcode() == ISD::BITCAST && V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR && V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT && V1.getOperand(0) .getOperand(0).getValueType().getSizeInBits() == SignificantBits) { SDValue V = V1.getOperand(0).getOperand(0).getOperand(0); ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1)); if (CIdx && CIdx->getZExtValue() == 0 && (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) { if (V.getValueSizeInBits() > V1.getValueSizeInBits()) argument [all...] |