Target/X86/X86ISelLowering.cpp

1528 std::pair<const TargetRegisterClass*, uint8_t>
1551   return std::make_pair(RRC, Cost);
2369   SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2417       RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2429           RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2449       RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2488     RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2720 //  Like std call, callee cleans arguments, convention except that ECX is
3239     std::swap(LHS, RHS);
3248     std::swap(LHS, RHS);
5780   std::bitset<4> InputQuads;
5942   std::bitset<8> InOrder;
6396   std::pair<int, int> Locs[4];
6405       Locs[i] = std::make_pair(-1, -1);
6409         Locs[i] = std::make_pair(0, NumLo);
6413         Locs[i] = std::make_pair(1, NumHi);
6451       std::swap(V1, V2);
6506       Locs[i] = std::make_pair(-1, -1);
6508       Locs[i] = std::make_pair(MaskIdx, LoIdx);
6512       Locs[i] = std::make_pair(MaskIdx, HiIdx);
6939     std::swap(V1, V2);
6940     std::swap(V1IsSplat, V2IsSplat);
6976     std::swap(V1, V2);
6977     std::swap(V1IsSplat, V2IsSplat);
8273 std::pair<SDValue,SDValue>
8292     return std::make_pair(SDValue(), SDValue());
8296     return std::make_pair(SDValue(), SDValue());
8351     return std::make_pair(FIST, StackSlot);
8364     return std::make_pair(pair, SDValue());
8581   std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
8599   std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
8841       M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
9152     std::swap(Op0, Op1);
9293       std::swap(Op0, Op1);
9341     std::swap(Op0, Op1);
11834     std::vector<SDValue> Vals(Ratio);
12338   std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
12506     std::pair<SDValue,SDValue> Vals =
15470           std::swap(LHS, RHS);
15485         std::swap(LHS, RHS);
15508           std::swap(LHS, RHS);
15515         std::swap(LHS, RHS);
15535           std::swap(LHS, RHS);
15549         std::swap(LHS, RHS);
15570           std::swap(LHS, RHS);
15577         std::swap(LHS, RHS);
15606           std::swap(TrueC, FalseC);
15798         std::swap(LHS, RHS);
16026         std::swap(TrueC, FalseC);
16027         std::swap(TrueOp, FalseOp);
16137         std::swap(TrueOp, FalseOp);
16193       std::swap(MulAmt1, MulAmt2);
16550       std::swap(N0, N1);
16627     std::swap(N0, N1);
16650     std::swap(Op0, Op1);
16651     std::swap(ShAmt0, ShAmt1);
16788                                 std::min(16U, Alignment));
16985                                 std::min(16U, Alignment));
17241     std::copy(Mask.begin(), Mask.end(), LMask.begin());
17259     std::copy(Mask.begin(), Mask.end(), RMask.begin());
18000   std::string AsmStr = IA->getAsmString();
18035       const std::string &ConstraintsStr = IA->getConstraintString();
18053       const std::string &ConstraintsStr = IA->getConstraintString();
18084 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
18249                                                      std::string &Constraint,
18250                                                      std::vector<SDValue>&Ops,
18381 std::pair<unsigned, const TargetRegisterClass*>
18382 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
18396           return std::make_pair(0U, &X86::GR32RegClass);
18398           return std::make_pair(0U, &X86::GR16RegClass);
18400           return std::make_pair(0U, &X86::GR8RegClass);
18402           return std::make_pair(0U, &X86::GR64RegClass);
18408         return std::make_pair(0U, &X86::GR32_ABCDRegClass);
18410         return std::make_pair(0U, &X86::GR16_ABCDRegClass);
18412         return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
18414         return std::make_pair(0U, &X86::GR64_ABCDRegClass);
18419         return std::make_pair(0U, &X86::GR8RegClass);
18421         return std::make_pair(0U, &X86::GR16RegClass);
18423         return std::make_pair(0U, &X86::GR32RegClass);
18424       return std::make_pair(0U, &X86::GR64RegClass);
18427         return std::make_pair(0U, &X86::GR8_NOREXRegClass);
18429         return std::make_pair(0U, &X86::GR16_NOREXRegClass);
18431         return std::make_pair(0U, &X86::GR32_NOREXRegClass);
18432       return std::make_pair(0U, &X86::GR64_NOREXRegClass);
18437         return std::make_pair(0U, &X86::RFP32RegClass);
18439         return std::make_pair(0U, &X86::RFP64RegClass);
18440       return std::make_pair(0U, &X86::RFP80RegClass);
18443       return std::make_pair(0U, &X86::VR64RegClass);
18455         return std::make_pair(0U, &X86::FR32RegClass);
18458         return std::make_pair(0U, &X86::FR64RegClass);
18466         return std::make_pair(0U, &X86::VR128RegClass);
18474         return std::make_pair(0U, &X86::VR256RegClass);
18482   std::pair<unsigned, const TargetRegisterClass*> Res;