Lines Matching refs:mcr
4289 mcr p15,0,r0,c5,c0,0 /* DFSR */
4290 mcr p15,0,r0,c5,c0,1 /* IFSR */
4291 mcr p15,0,r0,c6,c0,0 /* DFAR */
4292 mcr p15,0,r0,c6,c0,1 /* WFSR */
4300 mcr p15,0,r1,c1,c0,0
4302 mcr p15,0,r0,c8,c7,0 /* Invalidate TLB */
4303 mcr p15,0,r0,c7,c5,0 /* Invalidate icache */
4304 mcr p15,0,r0,c7,c5,6 /* Invalidate BTAC */
4305 mcr p15,0,r0,c7,c10,4 /* DSB */
4306 mcr p15,0,r0,c7,c5,4 /* ISB */
4329 mcr p15,0,r0,c7,c10,4
4336 mcr p15,0,r1,c1,c0,0
4343 mcr p15,0,r0,c7,c10,4 /* DSB */
4346 mcr p15,0,r1,c1,c0,0
4347 mcr p15,0,r0,c7,c5,4 /* ISB */
4350 mcr p15,0,r0,c8,c7,0
4371 mcr p15,0,r0,c2,c0,2
4373 mcr p15,0,r1,c2,c0,0
4376 mcr p15,0,r1,c3,c0,0
4380 mcr p15,0,r1,c1,c0,0
4381 mcr p15,0,r0,c7,c5,4 /* ISB */
4425 mcr p15,0,r0,c7,c10,4 /* DSB */
4426 mcr p15,0,r0,c7,c5,4 /* ISB */
4601 mcr p15,0,r1,c9,c12,0 /* Set enable bit in PMNC */
4603 mcr p15,0,r1,c9,c12,1
4796 mcr p15,0,r1,c9,c12,0 /* Set enable bit in PMNC */
4798 mcr p15,0,r1,c9,c12,1
5256 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
5257 mcr p15, 0, r10, c7, c5, 4 @ flush prefetch buffer,
5273 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
5284 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
5285 mcr p15, 0, r10, c7, c5, 4 @ flush prefetch buffer,
5294 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
5312 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
5313 mcr p15, 0, r10, c7, c5, 4 @ flush prefetch buffer,
5329 mcr p15, 0, r11, c7, c6, 2 @ invalidate by set/way
5340 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
5341 mcr p15, 0, r10, c7, c5, 4 @ flush prefetch buffer,
5350 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
5449 mcr p15, 0, r0, c7, c10, 1 @ clean D / U line
5454 mcr p15, 0, r10, c7, c5, 4 @ flush prefetch buffer,
5512 mcr p15,0,r0,c1,c0,0