drivers/ssb/driver_chipcommon_pmu.c

22 static u32 ssb_chipco_pll_read(struct ssb_chipcommon *cc, u32 offset)
24 	chipco_write32(cc, SSB_CHIPCO_PLLCTL_ADDR, offset);
25 	return chipco_read32(cc, SSB_CHIPCO_PLLCTL_DATA);
28 static void ssb_chipco_pll_write(struct ssb_chipcommon *cc,
31 	chipco_write32(cc, SSB_CHIPCO_PLLCTL_ADDR, offset);
32 	chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, value);
35 static void ssb_chipco_regctl_maskset(struct ssb_chipcommon *cc,
40 	chipco_read32(cc, SSB_CHIPCO_REGCTL_ADDR);
41 	chipco_write32(cc, SSB_CHIPCO_REGCTL_ADDR, offset);
42 	chipco_read32(cc, SSB_CHIPCO_REGCTL_ADDR);
43 	value = chipco_read32(cc, SSB_CHIPCO_REGCTL_DATA);
46 	chipco_write32(cc, SSB_CHIPCO_REGCTL_DATA, value);
47 	chipco_read32(cc, SSB_CHIPCO_REGCTL_DATA);
90 static void ssb_pmu0_pllinit_r0(struct ssb_chipcommon *cc,
93 	struct ssb_bus *bus = cc->dev->bus;
104 	cc->pmu.crystalfreq = e->freq;
107 	pmuctl = chipco_read32(cc, SSB_CHIPCO_PMU_CTL);
113 	dev_info(cc->dev->dev, "Programming PLL to %u.%03u MHz\n",
119 		chipco_mask32(cc, SSB_CHIPCO_PMU_MINRES_MSK,
121 		chipco_mask32(cc, SSB_CHIPCO_PMU_MAXRES_MSK,
125 		chipco_mask32(cc, SSB_CHIPCO_PMU_MINRES_MSK,
127 		chipco_mask32(cc, SSB_CHIPCO_PMU_MAXRES_MSK,
134 		tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST);
139 	tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST);
141 		dev_emerg(cc->dev->dev, "Failed to turn the PLL off!\n");
144 	pllctl = ssb_chipco_pll_read(cc, SSB_PMU0_PLLCTL0);
149 	ssb_chipco_pll_write(cc, SSB_PMU0_PLLCTL0, pllctl);
152 	pllctl = ssb_chipco_pll_read(cc, SSB_PMU0_PLLCTL1);
159 	ssb_chipco_pll_write(cc, SSB_PMU0_PLLCTL1, pllctl);
162 	pllctl = ssb_chipco_pll_read(cc, SSB_PMU0_PLLCTL2);
165 	ssb_chipco_pll_write(cc, SSB_PMU0_PLLCTL2, pllctl);
168 	pmuctl = chipco_read32(cc, SSB_CHIPCO_PMU_CTL);
174 	chipco_write32(cc, SSB_CHIPCO_PMU_CTL, pmuctl);
221 static void ssb_pmu1_pllinit_r0(struct ssb_chipcommon *cc,
224 	struct ssb_bus *bus = cc->dev->bus;
233 		cc->pmu.crystalfreq = 20000;
243 	cc->pmu.crystalfreq = e->freq;
246 	pmuctl = chipco_read32(cc, SSB_CHIPCO_PMU_CTL);
252 	dev_info(cc->dev->dev, "Programming PLL to %u.%03u MHz\n",
258 		chipco_mask32(cc, SSB_CHIPCO_PMU_MINRES_MSK,
261 		chipco_mask32(cc, SSB_CHIPCO_PMU_MAXRES_MSK,
271 		tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST);
276 	tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST);
278 		dev_emerg(cc->dev->dev, "Failed to turn the PLL off!\n");
281 	pllctl = ssb_chipco_pll_read(cc, SSB_PMU1_PLLCTL0);
285 	ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, pllctl);
288 	pllctl = ssb_chipco_pll_read(cc, SSB_PMU1_PLLCTL2);
292 	ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, pllctl);
295 	pllctl = ssb_chipco_pll_read(cc, SSB_PMU1_PLLCTL3);
298 	ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL3, pllctl);
302 		pllctl = ssb_chipco_pll_read(cc, SSB_PMU1_PLLCTL5);
305 		ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, pllctl);
309 	pmuctl = chipco_read32(cc, SSB_CHIPCO_PMU_CTL);
314 	chipco_write32(cc, SSB_CHIPCO_PMU_CTL, pmuctl);
317 static void ssb_pmu_pll_init(struct ssb_chipcommon *cc)
319 	struct ssb_bus *bus = cc->dev->bus;
333 		ssb_pmu1_pllinit_r0(cc, crystalfreq);
336 		ssb_pmu0_pllinit_r0(cc, crystalfreq);
341 		ssb_pmu0_pllinit_r0(cc, crystalfreq);
344 		if (cc->pmu.rev == 2) {
345 			chipco_write32(cc, SSB_CHIPCO_PLLCTL_ADDR, 0x0000000A);
346 			chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, 0x380005C0);
352 		dev_err(cc->dev->dev, "ERROR: PLL init unknown for device %04X\n",
423 static void ssb_pmu_resources_init(struct ssb_chipcommon *cc)
425 	struct ssb_bus *bus = cc->dev->bus;
448 		if (chipco_read32(cc, SSB_CHIPCO_CHIPSTAT) &
474 		dev_err(cc->dev->dev, "ERROR: PMU resource config unknown for device %04X\n",
480 			chipco_write32(cc, SSB_CHIPCO_PMU_RES_TABSEL,
482 			chipco_write32(cc, SSB_CHIPCO_PMU_RES_UPDNTM,
488 			chipco_write32(cc, SSB_CHIPCO_PMU_RES_TABSEL,
492 				chipco_write32(cc, SSB_CHIPCO_PMU_RES_DEPMSK,
496 				chipco_set32(cc, SSB_CHIPCO_PMU_RES_DEPMSK,
500 				chipco_mask32(cc, SSB_CHIPCO_PMU_RES_DEPMSK,
511 		chipco_write32(cc, SSB_CHIPCO_PMU_MINRES_MSK, min_msk);
513 		chipco_write32(cc, SSB_CHIPCO_PMU_MAXRES_MSK, max_msk);
517 void ssb_pmu_init(struct ssb_chipcommon *cc)
521 	if (!(cc->capabilities & SSB_CHIPCO_CAP_PMU))
524 	pmucap = chipco_read32(cc, SSB_CHIPCO_PMU_CAP);
525 	cc->pmu.rev = (pmucap & SSB_CHIPCO_PMU_CAP_REVISION);
527 	dev_dbg(cc->dev->dev, "Found rev %u PMU (capabilities 0x%08X)\n",
528 		cc->pmu.rev, pmucap);
530 	if (cc->pmu.rev == 1)
531 		chipco_mask32(cc, SSB_CHIPCO_PMU_CTL,
534 		chipco_set32(cc, SSB_CHIPCO_PMU_CTL,
536 	ssb_pmu_pll_init(cc);
537 	ssb_pmu_resources_init(cc);
540 void ssb_pmu_set_ldo_voltage(struct ssb_chipcommon *cc,
543 	struct ssb_bus *bus = cc->dev->bus;
586 	ssb_chipco_regctl_maskset(cc, addr, ~(mask << shift),
590 void ssb_pmu_set_ldo_paref(struct ssb_chipcommon *cc, bool on)
592 	struct ssb_bus *bus = cc->dev->bus;
610 		chipco_set32(cc, SSB_CHIPCO_PMU_MINRES_MSK, 1 << ldo);
612 		chipco_mask32(cc, SSB_CHIPCO_PMU_MINRES_MSK, ~(1 << ldo));
613 	chipco_read32(cc, SSB_CHIPCO_PMU_MINRES_MSK); //SPEC FIXME found via mmiotrace - dummy read?
619 static u32 ssb_pmu_get_alp_clock_clk0(struct ssb_chipcommon *cc)
624 	crystalfreq = (chipco_read32(cc, SSB_CHIPCO_PMU_CTL) &
631 u32 ssb_pmu_get_alp_clock(struct ssb_chipcommon *cc)
633 	struct ssb_bus *bus = cc->dev->bus;
637 		return ssb_pmu_get_alp_clock_clk0(cc);
639 		dev_err(cc->dev->dev, "ERROR: PMU alp clock unknown for device %04X\n",
645 u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc)
647 	struct ssb_bus *bus = cc->dev->bus;
654 		dev_err(cc->dev->dev, "ERROR: PMU cpu clock unknown for device %04X\n",
660 u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc)
662 	struct ssb_bus *bus = cc->dev->bus;
668 		dev_err(cc->dev->dev, "ERROR: PMU controlclock unknown for device %04X\n",
674 void ssb_pmu_spuravoid_pllupdate(struct ssb_chipcommon *cc, int spuravoid)
678 	switch (cc->dev->bus->chip_id) {
680 		ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, 0x11100070);
681 		ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL1, 0x1014140a);
682 		ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, 0x88888854);
684 			ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x05201828);
686 			ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x05001828);
691 			ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, 0x11500008);
692 			ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL1, 0x0C000C06);
693 			ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x0F600a08);
694 			ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL3, 0x00000000);
695 			ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL4, 0x2001E920);
696 			ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, 0x88888815);
698 			ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, 0x11100008);
699 			ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL1, 0x0c000c06);
700 			ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x03000a08);
701 			ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL3, 0x00000000);
702 			ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL4, 0x200005c0);
703 			ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, 0x88888855);
708 		dev_err(cc->dev->dev,
710 			cc->dev->bus->chip_id);
714 	chipco_set32(cc, SSB_CHIPCO_PMU_CTL, pmu_ctl);