net/phy/motorcomm.c

90 /* If these bits are set to 3, the PHY attempts five times ( 3(set value) +
381  * @set: bit mask of bits to set
384  * modified as new register value = (old register value & ~mask) | set.
390 			    u16 set)
398 	return __phy_modify(phydev, YTPHY_PAGE_DATA, mask, set);
406  * @set: bit mask of bits to set
409  * modified as new register value = (old register value & ~mask) | set.
414 				      u16 mask, u16 set)
419 	ret = ytphy_modify_ext(phydev, regnum, mask, set);
605 	/* set rgmii delay mode */
632 	/* set clock mode to 125mhz */
690 	int set;
693 		set = YT8521_RSSR_FIBER_SPACE;
695 		set = YT8521_RSSR_UTP_SPACE;
697 	return ytphy_modify_ext(phydev, YT8521_REG_SPACE_SELECT_REG, mask, set);
711 	/* for tx delay / rx delay with YT8521_CCR_RXC_DLY_EN is not set. */
729 	/* only for rx delay with YT8521_CCR_RXC_DLY_EN is set. */
783 	 * so YT8521_CCR_RXC_DLY_EN should not be set.
908 	/* set rgmii rx clk driver strength */
925 	/* set rgmii rx data driver strength */
952  * yt8521_probe() - read chip config then set suitable polling_mode
1000 	/* set default reg space */
1273 	 * priority. reg space should be properly set before read
1424  * @set: bit mask of bits to set
1427  * modified as new register value = (old register value & ~mask) | set.
1435 				    u16 mask, u16 set)
1445 	ret = __phy_modify(phydev, MII_BMCR, mask, set);
1450 	if (set == BMCR_RESET) {
1470  * @set: bit mask of bits to set
1473  * modified as new register value = (old register value & ~mask) | set.
1480 					u16 set)
1487 					       set);
1492 					       mask, set);
1497 					       mask, set);
1582 	/* set rgmii delay mode */
1926 	 * 1000Mbits/sec capable PHYs shall have the BMSR_ESTATEN bit set to a