intel/igc/igc_phy.c

35 	s32 ret_val = 0;
38 	ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
39 	if (ret_val)
44 	ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
45 	if (ret_val)
52 	return ret_val;
68 	s32 ret_val = 0;
75 		ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
76 		if (ret_val && usec_interval > 0) {
86 		ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
87 		if (ret_val)
99 	return ret_val;
164 	s32  ret_val;
167 	ret_val = igc_check_reset_block(hw);
168 	if (ret_val) {
169 		ret_val = 0;
173 	ret_val = phy->ops.acquire(hw);
174 	if (ret_val)
204 	return ret_val;
222 	s32 ret_val;
227 	ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
228 	if (ret_val)
229 		return ret_val;
233 		ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
235 		if (ret_val)
236 			return ret_val;
241 		ret_val = phy->ops.read_reg(hw, (STANDARD_AN_REG_MASK <<
246 		if (ret_val)
247 			return ret_val;
369 	ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
370 	if (ret_val)
371 		return ret_val;
376 		ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL,
380 		ret_val = phy->ops.write_reg(hw,
386 	return ret_val;
399 	s32 ret_val = 0;
403 		ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
404 		if (ret_val)
406 		ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
407 		if (ret_val)
417 	return ret_val;
433 	s32 ret_val;
447 	ret_val = igc_phy_setup_autoneg(hw);
448 	if (ret_val) {
457 	ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
458 	if (ret_val)
462 	ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
463 	if (ret_val)
470 		ret_val = igc_wait_autoneg(hw);
471 		if (ret_val) {
480 	return ret_val;
494 	s32 ret_val = 0;
501 		ret_val = igc_copper_link_autoneg(hw);
502 		if (ret_val)
509 		ret_val = hw->phy.ops.force_speed_duplex(hw);
510 		if (ret_val) {
519 	ret_val = igc_phy_has_link(hw, COPPER_LINK_UP_LIMIT, 10, &link);
520 	if (ret_val)
526 		ret_val = igc_config_fc_after_link_up(hw);
532 	return ret_val;
548 	s32 ret_val = 0;
552 		ret_val = -IGC_ERR_PARAM;
578 		ret_val = -IGC_ERR_PHY;
583 		ret_val = -IGC_ERR_PHY;
589 	return ret_val;
604 	s32 ret_val = 0;
608 		ret_val = -IGC_ERR_PARAM;
635 		ret_val = -IGC_ERR_PHY;
640 		ret_val = -IGC_ERR_PHY;
645 	return ret_val;
659 	s32 ret_val;
661 	ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, dev_addr);
662 	if (ret_val)
663 		return ret_val;
665 	ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD, address);
666 	if (ret_val)
667 		return ret_val;
669 	ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, IGC_MMDAC_FUNC_DATA |
671 	if (ret_val)
672 		return ret_val;
675 		ret_val = hw->phy.ops.read_reg(hw, IGC_MMDAAD, data);
677 		ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD, *data);
678 	if (ret_val)
679 		return ret_val;
682 	ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, 0);
683 	if (ret_val)
684 		return ret_val;
686 	return ret_val;
727 	s32 ret_val;
732 		ret_val = hw->phy.ops.acquire(hw);
733 		if (ret_val)
734 			return ret_val;
735 		ret_val = igc_write_phy_reg_mdic(hw, offset, data);
738 		ret_val = igc_write_xmdio_reg(hw, (u16)offset, dev_addr,
742 	return ret_val;
758 	s32 ret_val;
763 		ret_val = hw->phy.ops.acquire(hw);
764 		if (ret_val)
765 			return ret_val;
766 		ret_val = igc_read_phy_reg_mdic(hw, offset, data);
769 		ret_val = igc_read_xmdio_reg(hw, (u16)offset, dev_addr,
773 	return ret_val;
784 	u16 ret_val;
787 	ret_val = phy->ops.read_reg(hw, IGC_GPHY_VERSION, &gphy_version);
788 	if (ret_val)