Lines Matching defs:table
422 pr_err("vdd_dep_on_sclk table is NULL\n");
586 "The CAC Leakage table does not exist!", return -EINVAL);
789 pr_warn("Index from SCLK/VDDC Dependency Table exceeds the CAC Leakage Table index, using maximum index from CAC table.\n");
805 pr_warn("Index from SCLK/VDDC Dependency Table exceeds the CAC Leakage Table index in second look up, using maximum index from CAC table.");
842 SMU7_Discrete_DpmTable *table)
848 table->VddcLevelCount = data->vddc_voltage_table.count;
849 for (count = 0; count < table->VddcLevelCount; count++) {
852 &(table->VddcLevel[count]));
853 PP_ASSERT_WITH_CODE(0 == result, "do not populate SMC VDDC voltage table", return -EINVAL);
857 table->VddcLevel[count].Smio = (uint8_t) count;
858 table->Smio[count] |= data->vddc_voltage_table.entries[count].smio_low;
859 table->SmioMaskVddcVid |= data->vddc_voltage_table.entries[count].smio_low;
861 table->VddcLevel[count].Smio = 0;
865 CONVERT_FROM_HOST_TO_SMC_UL(table->VddcLevelCount);
871 SMU7_Discrete_DpmTable *table)
877 table->VddciLevelCount = data->vddci_voltage_table.count;
879 for (count = 0; count < table->VddciLevelCount; count++) {
882 &(table->VddciLevel[count]));
883 PP_ASSERT_WITH_CODE(result == 0, "do not populate SMC VDDCI voltage table", return -EINVAL);
885 table->VddciLevel[count].Smio = (uint8_t) count;
886 table->Smio[count] |= data->vddci_voltage_table.entries[count].smio_low;
887 table->SmioMaskVddciVid |= data->vddci_voltage_table.entries[count].smio_low;
889 table->VddciLevel[count].Smio = 0;
893 CONVERT_FROM_HOST_TO_SMC_UL(table->VddciLevelCount);
899 SMU7_Discrete_DpmTable *table)
905 table->MvddLevelCount = data->mvdd_voltage_table.count;
907 for (count = 0; count < table->MvddLevelCount; count++) {
910 &table->MvddLevel[count]);
911 PP_ASSERT_WITH_CODE(result == 0, "do not populate SMC mvdd voltage table", return -EINVAL);
913 table->MvddLevel[count].Smio = (uint8_t) count;
914 table->Smio[count] |= data->mvdd_voltage_table.entries[count].smio_low;
915 table->SmioMaskMvddVid |= data->mvdd_voltage_table.entries[count].smio_low;
917 table->MvddLevel[count].Smio = 0;
921 CONVERT_FROM_HOST_TO_SMC_UL(table->MvddLevelCount);
928 SMU7_Discrete_DpmTable *table)
932 result = ci_populate_smc_vddc_table(hwmgr, table);
934 "can not populate VDDC voltage table to SMC", return -EINVAL);
936 result = ci_populate_smc_vdd_ci_table(hwmgr, table);
938 "can not populate VDDCI voltage table to SMC", return -EINVAL);
940 result = ci_populate_smc_mvdd_table(hwmgr, table);
942 "can not populate MVDD voltage table to SMC", return -EINVAL);
997 static int ci_populate_smc_link_level(struct pp_hwmgr *hwmgr, SMU7_Discrete_DpmTable *table)
1006 table->LinkLevel[i].PcieGenSpeed =
1008 table->LinkLevel[i].PcieLaneCount =
1010 table->LinkLevel[i].EnabledForActivity = 1;
1011 table->LinkLevel[i].DownT = PP_HOST_TO_SMC_UL(5);
1012 table->LinkLevel[i].UpT = PP_HOST_TO_SMC_UL(30);
1191 "can not find MinVddc voltage value from memory VDDC voltage dependency table", return result);
1200 "can not find MinVddci voltage value from memory VDDCI voltage dependency table", return result);
1209 "can not find MinVddci voltage value from memory MVDD voltage dependency table", return result);
1378 SMU7_Discrete_DpmTable *table)
1392 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
1395 table->ACPILevel.MinVddc = PP_HOST_TO_SMC_UL(data->acpi_vddc * VOLTAGE_SCALE);
1397 table->ACPILevel.MinVddc = PP_HOST_TO_SMC_UL(data->min_vddc_in_pptable * VOLTAGE_SCALE);
1399 table->ACPILevel.MinVddcPhases = data->vddc_phase_shed_control ? 0 : 1;
1401 table->ACPILevel.SclkFrequency = atomctrl_get_reference_clock(hwmgr);
1405 table->ACPILevel.SclkFrequency, ÷rs);
1411 table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;
1412 table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1413 table->ACPILevel.DeepSleepDivId = 0;
1422 table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
1423 table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
1424 table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
1425 table->ACPILevel.CgSpllFuncCntl4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
1426 table->ACPILevel.SpllSpreadSpectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
1427 table->ACPILevel.SpllSpreadSpectrum2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
1428 table->ACPILevel.CcPwrDynRm = 0;
1429 table->ACPILevel.CcPwrDynRm1 = 0;
1432 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
1434 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkFrequency);
1435 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl);
1436 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl2);
1437 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl3);
1438 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl4);
1439 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum);
1440 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum2);
1441 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
1442 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
1445 /* table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;*/
1446 table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc;
1447 table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;
1450 table->MemoryACPILevel.MinVddci = table->MemoryACPILevel.MinVddc;
1453 table->MemoryACPILevel.MinVddci = PP_HOST_TO_SMC_UL(data->acpi_vddci * VOLTAGE_SCALE);
1455 table->MemoryACPILevel.MinVddci = PP_HOST_TO_SMC_UL(data->min_vddci_in_pptable * VOLTAGE_SCALE);
1459 table->MemoryACPILevel.MinMvdd =
1462 table->MemoryACPILevel.MinMvdd = 0;
1482 table->MemoryACPILevel.DllCntl =
1484 table->MemoryACPILevel.MclkPwrmgtCntl =
1486 table->MemoryACPILevel.MpllAdFuncCntl =
1488 table->MemoryACPILevel.MpllDqFuncCntl =
1490 table->MemoryACPILevel.MpllFuncCntl =
1492 table->MemoryACPILevel.MpllFuncCntl_1 =
1494 table->MemoryACPILevel.MpllFuncCntl_2 =
1496 table->MemoryACPILevel.MpllSs1 =
1498 table->MemoryACPILevel.MpllSs2 =
1501 table->MemoryACPILevel.EnabledForThrottle = 0;
1502 table->MemoryACPILevel.EnabledForActivity = 0;
1503 table->MemoryACPILevel.UpH = 0;
1504 table->MemoryACPILevel.DownH = 100;
1505 table->MemoryACPILevel.VoltageDownH = 0;
1507 table->MemoryACPILevel.ActivityLevel = PP_HOST_TO_SMC_US(data->current_profile_setting.mclk_activity);
1509 table->MemoryACPILevel.StutterEnable = 0;
1510 table->MemoryACPILevel.StrobeEnable = 0;
1511 table->MemoryACPILevel.EdcReadEnable = 0;
1512 table->MemoryACPILevel.EdcWriteEnable = 0;
1513 table->MemoryACPILevel.RttEnable = 0;
1519 SMU7_Discrete_DpmTable *table)
1527 table->UvdLevelCount = (uint8_t)(uvd_table->count);
1529 for (count = 0; count < table->UvdLevelCount; count++) {
1530 table->UvdLevel[count].VclkFrequency =
1532 table->UvdLevel[count].DclkFrequency =
1534 table->UvdLevel[count].MinVddc =
1536 table->UvdLevel[count].MinVddcPhases = 1;
1539 table->UvdLevel[count].VclkFrequency, ÷rs);
1543 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
1546 table->UvdLevel[count].DclkFrequency, ÷rs);
1550 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
1551 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
1552 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
1553 CONVERT_FROM_HOST_TO_SMC_US(table->UvdLevel[count].MinVddc);
1560 SMU7_Discrete_DpmTable *table)
1568 table->VceLevelCount = (uint8_t)(vce_table->count);
1569 table->VceBootLevel = 0;
1571 for (count = 0; count < table->VceLevelCount; count++) {
1572 table->VceLevel[count].Frequency = vce_table->entries[count].evclk;
1573 table->VceLevel[count].MinVoltage =
1575 table->VceLevel[count].MinPhases = 1;
1578 table->VceLevel[count].Frequency, ÷rs);
1583 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1585 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
1586 CONVERT_FROM_HOST_TO_SMC_US(table->VceLevel[count].MinVoltage);
1592 SMU7_Discrete_DpmTable *table)
1600 table->AcpLevelCount = (uint8_t)(acp_table->count);
1601 table->AcpBootLevel = 0;
1603 for (count = 0; count < table->AcpLevelCount; count++) {
1604 table->AcpLevel[count].Frequency = acp_table->entries[count].acpclk;
1605 table->AcpLevel[count].MinVoltage = acp_table->entries[count].v;
1606 table->AcpLevel[count].MinPhases = 1;
1609 table->AcpLevel[count].Frequency, ÷rs);
1613 table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1615 CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].Frequency);
1616 CONVERT_FROM_HOST_TO_SMC_US(table->AcpLevel[count].MinVoltage);
1686 SMU7_Discrete_DpmTable *table)
1692 table->GraphicsBootLevel = 0;
1693 table->MemoryBootLevel = 0;
1695 /* find boot level from dpm table*/
1702 pr_err("VBIOS did not find boot engine clock value in dependency table. Using Graphics DPM level 0!\n");
1712 pr_err("VBIOS did not find boot engine clock value in dependency table. Using Memory DPM level 0!\n");
1716 table->BootVddc = data->vbios_boot_state.vddc_bootup_value;
1717 table->BootVddci = data->vbios_boot_state.vddci_bootup_value;
1718 table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value;
1884 SMU7_Discrete_DpmTable *table)
1889 table->SVI2Enable = 1;
1891 table->SVI2Enable = 0;
1911 static int ci_populate_vr_config(struct pp_hwmgr *hwmgr, SMU7_Discrete_DpmTable *table)
1917 table->VRConfig |= (config<<VRCONF_VDDGFX_SHIFT);
1921 table->VRConfig |= config;
1928 table->VRConfig |= (config<<VRCONF_VDDCI_SHIFT);
1931 table->VRConfig |= (config<<VRCONF_VDDCI_SHIFT);
1936 table->VRConfig |= (config<<VRCONF_MVDD_SHIFT);
1947 SMU7_Discrete_DpmTable *table = &(smu_data->smc_state_table);
1955 ci_populate_smc_voltage_tables(hwmgr, table);
1959 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
1964 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
1967 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
1970 result = ci_populate_ulv_state(hwmgr, &(table->Ulv));
1986 result = ci_populate_smc_link_level(hwmgr, table);
1990 result = ci_populate_smc_acpi_level(hwmgr, table);
1994 result = ci_populate_smc_vce_level(hwmgr, table);
1998 result = ci_populate_smc_acp_level(hwmgr, table);
2008 result = ci_populate_smc_uvd_level(hwmgr, table);
2012 table->UvdBootLevel = 0;
2013 table->VceBootLevel = 0;
2014 table->AcpBootLevel = 0;
2015 table->SamuBootLevel = 0;
2017 table->GraphicsBootLevel = 0;
2018 table->MemoryBootLevel = 0;
2020 result = ci_populate_smc_boot_level(hwmgr, table);
2030 table->UVDInterval = 1;
2031 table->VCEInterval = 1;
2032 table->ACPInterval = 1;
2033 table->SAMUInterval = 1;
2034 table->GraphicsVoltageChangeEnable = 1;
2035 table->GraphicsThermThrottleEnable = 1;
2036 table->GraphicsInterval = 1;
2037 table->VoltageInterval = 1;
2038 table->ThermalInterval = 1;
2040 table->TemperatureLimitHigh =
2043 table->TemperatureLimitLow =
2047 table->MemoryVoltageChangeEnable = 1;
2048 table->MemoryInterval = 1;
2049 table->VoltageResponseTime = 0;
2050 table->VddcVddciDelta = 4000;
2051 table->PhaseResponseTime = 0;
2052 table->MemoryThermThrottleEnable = 1;
2058 table->PCIeBootLinkLevel = (uint8_t)data->dpm_table.pcie_speed_table.count;
2059 table->PCIeGenInterval = 1;
2061 result = ci_populate_vr_config(hwmgr, table);
2064 data->vr_config = table->VRConfig;
2066 ci_populate_smc_svi2_config(hwmgr, table);
2069 CONVERT_FROM_HOST_TO_SMC_UL(table->Smio[i]);
2071 table->ThermGpio = 17;
2072 table->SclkStepSize = 0x4000;
2074 table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;
2078 table->VRHotGpio = SMU7_UNUSED_GPIO_PIN;
2083 table->AcDcGpio = SMU7_UNUSED_GPIO_PIN;
2085 CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
2086 CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
2087 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddcVid);
2088 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddcPhase);
2089 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddciVid);
2090 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskMvddVid);
2091 CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
2092 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
2093 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
2094 table->VddcVddciDelta = PP_HOST_TO_SMC_US(table->VddcVddciDelta);
2095 CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
2096 CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
2098 table->BootVddc = PP_HOST_TO_SMC_US(table->BootVddc * VOLTAGE_SCALE);
2099 table->BootVddci = PP_HOST_TO_SMC_US(table->BootVddci * VOLTAGE_SCALE);
2100 table->BootMVdd = PP_HOST_TO_SMC_US(table->BootMVdd * VOLTAGE_SCALE);
2105 (uint8_t *)&(table->SystemFlags),
2114 "Failed to populate initialize MC Reg table!", return result);
2239 PP_ASSERT_WITH_CODE((0 == result), "Failed to upload MC reg table!", return result);
2541 static int ci_set_s0_mc_reg_index(struct ci_mc_reg_table *table)
2546 for (i = 0; i < table->last; i++) {
2547 table->mc_reg_address[i].s0 =
2548 ci_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address)
2549 ? address : table->mc_reg_address[i].s1;
2554 static int ci_copy_vbios_smc_reg_table(const pp_atomctrl_mc_reg_table *table,
2559 PP_ASSERT_WITH_CODE((table->last <= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE),
2560 "Invalid VramInfo table.", return -EINVAL);
2561 PP_ASSERT_WITH_CODE((table->num_entries <= MAX_AC_TIMING_ENTRIES),
2562 "Invalid VramInfo table.", return -EINVAL);
2564 for (i = 0; i < table->last; i++)
2565 ni_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
2567 ni_table->last = table->last;
2569 for (i = 0; i < table->num_entries; i++) {
2571 table->mc_reg_table_entry[i].mclk_max;
2572 for (j = 0; j < table->last; j++) {
2574 table->mc_reg_table_entry[i].mc_data[j];
2578 ni_table->num_entries = table->num_entries;
2584 struct ci_mc_reg_table *table)
2590 for (i = 0, j = table->last; i < table->last; i++) {
2592 "Invalid VramInfo table.", return -EINVAL);
2594 switch (table->mc_reg_address[i].s1) {
2598 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS;
2599 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP;
2600 for (k = 0; k < table->num_entries; k++) {
2601 table->mc_reg_table_entry[k].mc_data[j] =
2603 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
2608 "Invalid VramInfo table.", return -EINVAL);
2610 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS;
2611 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP;
2612 for (k = 0; k < table->num_entries; k++) {
2613 table->mc_reg_table_entry[k].mc_data[j] =
2615 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
2618 table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
2624 "Invalid VramInfo table.", return -EINVAL);
2625 table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD;
2626 table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD;
2627 for (k = 0; k < table->num_entries; k++) {
2628 table->mc_reg_table_entry[k].mc_data[j] =
2629 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
2638 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS1;
2639 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS1_LP;
2640 for (k = 0; k < table->num_entries; k++) {
2641 table->mc_reg_table_entry[k].mc_data[j] =
2643 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
2654 table->last = j;
2659 static int ci_set_valid_flag(struct ci_mc_reg_table *table)
2663 for (i = 0; i < table->last; i++) {
2664 for (j = 1; j < table->num_entries; j++) {
2665 if (table->mc_reg_table_entry[j-1].mc_data[i] !=
2666 table->mc_reg_table_entry[j].mc_data[i]) {
2667 table->validflag |= (1 << i);
2680 pp_atomctrl_mc_reg_table *table;
2684 table = kzalloc(sizeof(pp_atomctrl_mc_reg_table), GFP_KERNEL);
2686 if (NULL == table)
2711 result = atomctrl_initialize_mc_reg_table(hwmgr, module_index, table);
2714 result = ci_copy_vbios_smc_reg_table(table, ni_table);
2724 kfree(table);