Lines Matching refs:clk_table
259 .clk_table = {
366 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
369 bw_params->clk_table.entries[i].dcfclk_mhz;
505 bw_params->clk_table.num_entries = j + 1;
516 for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) {
519 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].FClk;
520 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].MemClk;
521 bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[j].Voltage;
524 bw_params->clk_table.entries[i].wck_ratio = 2;
527 bw_params->clk_table.entries[i].wck_ratio = 4;
530 bw_params->clk_table.entries[i].wck_ratio = 1;
534 bw_params->clk_table.entries[i].dcfclk_mhz = temp;
537 bw_params->clk_table.entries[i].socclk_mhz = temp;
538 bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk;
539 bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk;
549 if (i >= bw_params->clk_table.num_entries) {