#
f69d3d6d |
|
26-Sep-2023 |
Simon Glass <sjg@chromium.org> |
pci: serial: Support reading PCI-register size with base The PCI helpers read only the base address for a PCI region. In some cases the size is needed as well, e.g. to pass along to a driver which needs to know the size of its register area. Update the functions to allow the size to be returned. For serial, record the information and provided it with the serial_info() call. A limitation still exists in that the size is not available when OF_LIVE is enabled, so take account of that in the tests. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
7f5ff034 |
|
26-Sep-2023 |
Simon Glass <sjg@chromium.org> |
serial: Drop ns16550 serial_getinfo() in SPL This is typically not needed in SPL/TPL and increases the code size. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
6e7df1d1 |
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10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
global: Finish CONFIG -> CFG migration At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
91092132 |
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16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_NS16550_* to CFG_SYS_NS16550_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NS16550 namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
57c3afbc |
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16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
powerpc: Rename CONFIG_NS16550_MIN_FUNCTIONS This symbol is specific to the PowerPC SPL implementation, so rename this to reflect that it's in SPL and used / tested there, so that we can then safely migrate it to Kconfig. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
29caf930 |
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02-Sep-2022 |
Stefan Roese <sr@denx.de> |
cyclic: Use schedule() instead of WATCHDOG_RESET() Globally replace all occurances of WATCHDOG_RESET() with schedule(), which handles the HW_WATCHDOG functionality and the cyclic infrastructure. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Tom Rini <trini@konsulko.com> [am335x_evm, mx6cuboxi, rpi_3,dra7xx_evm, pine64_plus, am65x_evm, j721e_evm] |
#
5e998b4d |
|
23-Jun-2022 |
Pali Rohár <pali@kernel.org> |
serial: ns16550: Wait in debug_uart_init until tx buffer is empty Commit d293759d55cc ("serial: ns16550: Add support for SPL_DEBUG_UART_BASE") fixed support for setting correct early debug UART base address in SPL. But after this commit, output from Marvell A385 BootROM is truncated or lost and not fully present on serial console. Debugging this issue showed that BootROM just put bytes into UART HW output buffer and does not wait until UART HW transmit all characters. U-Boot ns16550 early debug is initialized very early and during its initialization is resetting UART HW and flushing remaining transmit buffer (which still contains BootROM output). Fix this issue by waiting in init function prior resetting UART HW until TxEmpty bit in UART Line Status Register is set. TxEmpty is set when all remaining bytes from HW buffer are transmitted. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> [trini: Add comment, move ';' to new line per checkpatch.pl] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
d293759d |
|
06-May-2022 |
Pali Rohár <pali@kernel.org> |
serial: ns16550: Add support for SPL_DEBUG_UART_BASE Use CONFIG_VAL(DEBUG_UART_BASE) instead of CONFIG_DEBUG_UART_BASE, so proper config value (CONFIG_DEBUG_UART_BASE or CONFIG_SPL_DEBUG_UART_BASE) is used based on building target. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
04ee76c9 |
|
09-Apr-2022 |
Johan Jonker <jbx6244@gmail.com> |
rockchip: serial: move driver alias to serial_rockchip.c The Rockchip uart DT nodes have "snps,dw-apb-uart" as fall back string. The driver ns16550.c has CONFIG_IS_ENABLED(OF_REAL) as condition to of_match and does not copy dtplat data. For TPL/SPL the driver serial_rockchip.c is used. Move driver alias to correct driver. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
f899cc14 |
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12-Sep-2021 |
Tom Rini <trini@konsulko.com> |
ti: keystone: Move away from CONFIG_SOC_KEYSTONE We have individual SOC symbols for each keystone 2 platform. Use the existing CONFIG_ARCH_KEYSTONE rather than CONFIG_SOC_KEYSTONE to encompass all of the keystone families. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
414cc151 |
|
07-Aug-2021 |
Simon Glass <sjg@chromium.org> |
treewide: Simply conditions with the new OF_REAL Use this new Kconfig to simplify the compilation conditions where appropriate. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
384b62c0 |
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03-Feb-2021 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Handle zero <clock-frequency> value A working device tree node of ns16550 should never be populated with value zero for the <clock-frequency> property. Unfortunately this is the case for the QEMU ppce500 target. Let's try to assign plat->clock to CONFIG_SYS_NS16550_CLK as the last resort to handle such case. This commit should be reverted when: - The following QEMU patch [1] is merged, and - U-Boot CI has upgraded its QEMU version that contains the fix [1] http://patchwork.ozlabs.org/project/qemu-devel/patch/1612362288-22216-2-git-send-email-bmeng.cn@gmail.com/ Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
09bd0840 |
|
03-Feb-2021 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Correct the base address type Currently ns16550_serial_assign_base() treats the argument 'base' with type `ulong`. This is incorrect because the base address was obtained from device tree with type `fdt_addr_t` that can represent a physical address larger than 32-bit in a 32-bit system. Fixes: 9e6ce62190b7 ("serial: ns16550: Fix ordering of getting base address") Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
401d1c4f |
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30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
bdf8fd76 |
|
28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
0fd3d911 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com> |
#
2d6bf754 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
#
d30c7209 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo |
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de> |
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> |
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se> |
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> |
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com |
#
9ad3b049 |
|
02-Nov-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: add setconfig support Add possibility to update the serial parity used. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com> |
#
46879196 |
|
24-Oct-2018 |
Bin Meng <bmeng.cn@gmail.com> |
serial: Remove DM_FLAG_PRE_RELOC flag in various drivers When a driver declares DM_FLAG_PRE_RELOC flag, it wishes to be bound before relocation. However due to a bug in the DM core, the flag only takes effect when devices are statically declared via U_BOOT_DEVICE(). This bug has been fixed recently by commit "dm: core: Respect drivers with the DM_FLAG_PRE_RELOC flag in lists_bind_fdt()", but with the fix, it has a side effect that all existing drivers that declared DM_FLAG_PRE_RELOC flag will be bound before relocation now. This may expose potential boot failure on some boards due to insufficient memory during the pre-relocation stage. To mitigate this potential impact, the following changes are implemented: - Remove DM_FLAG_PRE_RELOC flag in the driver, if the driver only supports configuration from device tree (OF_CONTROL) - Keep DM_FLAG_PRE_RELOC flag in the driver only if the device is statically declared via U_BOOT_DEVICE() - Surround DM_FLAG_PRE_RELOC flag with OF_CONTROL check, for drivers that support both statically declared devices and configuration from device tree Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
6f57c344 |
|
09-Aug-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), let's rather ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
5d754197 |
|
27-Aug-2018 |
Lokesh Vutla <lokeshvutla@ti.com> |
serial: omap: Introduce DM specific omap serial Add driver model support for OMAP_SERIAL while reusing the functions in ns16550.c Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Tested-by: Derald D. Woods <woods.technical@gmail.com> |
#
b051eecb |
|
14-Jun-2018 |
Ley Foon Tan <ley.foon.tan@intel.com> |
serial: ns16550: Add reset ctrl to driver Add code to reset all reset signals as in serial DT node. A reset property is an optional feature, so do not fail if a reset property is not present. If a reset property is discovered, then use it to deassert, thus bringing the IP out of reset. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
78b7d37b |
|
15-Feb-2018 |
Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> |
ns16550: Fix mem mapped endian check Do a explicit check for CONFIG_SYS_BIG_ENDIAN and CONFIG_SYS_LITTLE_ENDIAN to avoid errors on platforms where both are undefined (x86). Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> Reviewed-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com> |
#
4dbf9bed |
|
15-Jan-2018 |
Mario Six <mario.six@gdsys.cc> |
serial: ns16550: Fix style violation Clarify the computation precedence in two ternary operator constructions. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc> |
#
7fded0ce |
|
16-Aug-2017 |
Stefan Roese <sr@denx.de> |
Revert "serial: ns16550: Add RX interrupt buffer support" This reverts commit 6822cf3ec7c8768b8727573b8f4b2cb3d870b881. As Bin Meng has tested and pointed out, we don't need the RX interrupt for the RX buffer support at all. Just reading all available characters into a buffer is sufficient to solve the problem with the dropped characters upon long lines pasted into the U-Boot prompt. Since this RX buffer support can be implemented in a generic way, without any device specifica (e.g. for the ns16550), I'll post a new patch with a new serial RX buffer support for DM, which all DM based serial drivers can use. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
6822cf3e |
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14-Jul-2017 |
Stefan Roese <sr@denx.de> |
serial: ns16550: Add RX interrupt buffer support Pasting longer lines into the U-Boot console prompt sometimes leads to characters missing. One problem here is the small 16-byte FIFO of the legacy NS16550 UART, e.g. on x86 platforms. This patch now introduces a Kconfig option to enable RX interrupt buffer support for NS16550 style UARTs. With this option enabled, I was able paste really long lines into the U-Boot console, without any characters missing. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> [trini: Guard ns16550_serial_remove with CONFIG_IS_ENABLED(SERIAL_PRESENT) to match struct assignment] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
8d3a2568 |
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11-Jul-2017 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-dm
|
#
db9f8f6a |
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12-Jun-2017 |
Simon Glass <sjg@chromium.org> |
dm: serial: ns16550: Convert to livetree Update this driver to support a live device tree. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Tested-on: Beaver, Jetson-TK1 |
#
3d40479f |
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07-Jun-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
rockchip: ns16550: dm: convert fdt_get to dev_read With the new dev_read functions available, we can convert the rockchip architecture-specific drivers and common drivers used by these devices over to the dev_read family of calls. This covers the serial driver (ns16550 and compatible) used for the Rockchip devices. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
a821c4af |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: Rename dev_addr..() functions These support the flat device tree. We want to use the dev_read_..() prefix for functions that support both flat tree and live tree. So rename the existing functions to avoid confusion. In the end we will have: 1. dev_read_addr...() - works on devices, supports flat/live tree 2. devfdt_get_addr...() - current functions, flat tree only 3. of_get_address() etc. - new functions, live tree only All drivers will be written to use 1. That function will in turn call either 2 or 3 depending on whether the flat or live tree is in use. Note this involves changing some dead code - the imx_lpi2c.c file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
89024ddc |
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12-May-2017 |
Tom Rini <trini@konsulko.com> |
TI: Drop 'CONFIG_OMAP' In the two cases in the code where we use CONFIG_OMAP as a useful test currently we can make use of CONFIG_ARCH_OMAP2PLUS instead. With that changed we can drop all defines of CONFIG_OMAP. While in here, CONFIG_OMAP3430 is only defined and then never used, so drop. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
a52cf086 |
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22-Apr-2017 |
Lokesh Vutla <lokeshvutla@ti.com> |
serial: omap: Support debug UART Add debug UART functions to permit omap specific ns16550 to provide an early debug UART. This is mostly in common with DEBUG_UART_NS16550 except for Mode definition register which is required for selecting UART mode(16x auto-baud or 13x mode). Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
6f8c351e |
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27-Mar-2017 |
Alexandru Gagniuc <alex.g@adaptrum.com> |
serial: ns16550: Link in the DM driver when when using platdata Do not condition the compilation of the U_BOOT_DRIVER by !OF_PLATDATA. This is inconsistent with the majority of other drivers. This also blocks OF_PLATDATA boards with an 16550-compatible serial from using serial in SPL. Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com> Reviewed-by: Simon Glass <sjg@chromium.org> Added tweak for rock to avoid a TPL build failure: Signed-off-by: Simon Glass <sjg@chromium.org> |
#
e160f7d4 |
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17-Jan-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
17fa0326 |
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18-Jan-2017 |
Heiko Schocher <hs@denx.de> |
serial, ns16550: bugfix: ns16550 fifo not enabled commit: 65f83802b7a5b "serial: 16550: Add getfcr accessor" breaks u-boot commandline working with long commands sending to the board. Since the above patch, you have to setup the fcr register. For board/archs which enable OF_PLATDATA, the new field fcr in struct ns16550_platdata is not filled with a default value ... This leads in not setting up the uarts fifo, which ends in problems, when you send long commands to u-boots commandline. Detected this issue with automated tbot tests on am335x based shc board. The error does not popup, if you type commands. You need to copy&paste a long command to u-boots commandshell (or send a long command with tbot) Possible boards/plattforms with problems: ./arch/arm/cpu/arm926ejs/lpc32xx/devices.c ./arch/arm/mach-tegra/board.c ./board/overo/overo.c ./board/quipos/cairo/cairo.c ./board/logicpd/omap3som/omap3logic.c ./board/logicpd/zoom1/zoom1.c ./board/timll/devkit8000/devkit8000.c ./board/lg/sniper/sniper.c ./board/ti/beagle/beagle.c ./drivers/serial/serial_rockchip.c Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Tested-by: Adam Ford <aford173@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
0b060eef |
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30-Nov-2016 |
Marek Vasut <marex@denx.de> |
serial: 16550: Add Ingenic JZ4780 support Add compatibility string for the Ingenic JZ4780 SoC, the necessary UART enable bit into FCR and register shift. Neither are encoded in the DTS coming from Linux, so we need to support it this way. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
79fd9281 |
|
30-Nov-2016 |
Marek Vasut <marex@denx.de> |
serial: 16550: Add port type as driver data Add driver data to each compatible string to identify the type of the port. Since all the ports in the driver are entirely compatible with 16550 for now, all are marked with PORT_NS16550. But, there are ports which have specific quirks, like the JZ4780 UART, which do not have any DT property to denote the quirks. Instead, Linux uses the compatible string to discern such ports and enable the necessary quirks. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> |
#
65f83802 |
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30-Nov-2016 |
Marek Vasut <marex@denx.de> |
serial: 16550: Add getfcr accessor Add function which allows fetching the default FCR register setting from platform data for DM , while retaining old behavior for non-DM by returning UART_FCRVAL. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
021abf69 |
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26-Sep-2016 |
Masahiro Yamada <masahiroy@kernel.org> |
Revert "ns16650: Make sure we have CONFIG_CLK set before using infrastructure" This reverts commit 82f5279b0cd99a9163d34cfe926d0316d9dc0d37. The build failure of k2*evm boards was fixed in a different way by the previous commit. It is nasty to patch generic drivers around with #ifdef CONFIG_CLK just for the KeyStone's matter. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
ab895d6a |
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30-Sep-2016 |
Alexandre Courbot <acourbot@nvidia.com> |
serial: ns16550: Handle -ENOENT when requesting clock When calling clk_get_by_index(), fall back to the legacy method of getting the clock if -ENOENT is returned. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> |
#
82f5279b |
|
22-Sep-2016 |
Tom Rini <trini@konsulko.com> |
ns16650: Make sure we have CONFIG_CLK set before using infrastructure We cannot call on the CONFIG_CLK based clk_get_rate function unless CONFIG_CLK is set. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
50fce1d5 |
|
08-Sep-2016 |
Paul Burton <paul.burton@mips.com> |
serial: ns16550: Support clocks via phandle Previously ns16550 compatible UARTs probed via device tree have needed their device tree nodes to contain a clock-frequency property. An alternative to this commonly used with Linux is to reference a clock via a phandle. This patch allows U-Boot to support that, retrieving the clock frequency by probing the appropriate clock device. For example, a system might choose to provide the UART base clock as a reference to a clock common to multiple devices: sys_clk: clock { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <10000000>; }; uart0: uart@10000000 { compatible = "ns16550a"; reg = <0x10000000 0x1000>; clocks = <&sys_clk>; }; uart1: uart@10000000 { compatible = "ns16550a"; reg = <0x10001000 0x1000>; clocks = <&sys_clk>; }; This removes the need for the frequency information to be duplicated in multiple nodes and allows the device tree to be more descriptive of the system. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
b2927fba |
|
04-Jul-2016 |
Simon Glass <sjg@chromium.org> |
dm: serial: ns16550: Update to support of-platdata With of-platdata this driver cannot know the format of the of-platdata struct, so we cannot use generic code for accessing the of-platdata. Each SoC that uses this driver will need to set up ns16550's platdata for it. So don't compile in the generic code. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
03c6f176 |
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24-May-2016 |
Marek Vasut <marex@denx.de> |
serial: 16550: Drop OMAP1510 support The CONFIG_OMAP1510 is no longer defined, so remove this dead code. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Nishanth Menon <nm@ti.com> |
#
fa4ce723 |
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24-May-2016 |
Marek Vasut <marex@denx.de> |
serial: 16550: Make serial_io/out_shift available to debug mode The ns16550 driver needs serial_in_shift() and serial_out_shift() when compiled in debug UART mode, so shift the DM_SERIAL check a little to make these functions available. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
df8ec55d |
|
17-May-2016 |
Paul Burton <paul.burton@mips.com> |
dm: ns16550: Don't map_physmem for I/O ports If the UART is to be accessed using I/O port accessors (inb & outb) then using map_physmem doesn't make sense, since it operates in a different memory space. Remove the call to map_physmem when CONFIG_SYS_NS16550_PORT_MAPPED is defined, allowing I/O port addresses to not be mangled by the incorrect mapping. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> |
#
59b35ddd |
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16-Feb-2016 |
Michal Simek <michal.simek@amd.com> |
dm: ns16550: Add support for reg-offset property reg-offset is the part of standard 8250 binding in the kernel. It is shifting start of address space by reg-offset. On Xilinx platform this offset is typically 0x1000. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Moved the new field to the end of the struct to avoid problems: Signed-off-by: Simon Glass <sjg@chromium.org> |
#
e5e88c65 |
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29-Feb-2016 |
Tom Rini <trini@konsulko.com> |
Revert "dm: ns16550: Add support for reg-offset property" This reverts commit d9a3bec682f9756621615f4306718a356a3230e3. While this is a correct change to do long term it unfortunately breaks a number of platforms that are using pdata and not named struct members so they are getting all of their data after 'base' incorrect. Acked-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
d9a3bec6 |
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16-Feb-2016 |
Michal Simek <michal.simek@amd.com> |
dm: ns16550: Add support for reg-offset property reg-offset is the part of standard 8250 binding in the kernel. It is shifting start of address space by reg-offset. On Xilinx platform this offset is typically 0x1000. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
cc4228f9 |
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14-Dec-2015 |
Thomas Chou <thomas@wytron.com.tw> |
ns16550: zap the rockchip serial compatible string Zap the rockchip serial compatible string, because rockchip serial has "snps,dw-apb-uart" compatible string in the dts. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org> |
#
b7e29834 |
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13-Dec-2015 |
Simon Glass <sjg@chromium.org> |
dm: ns16550: Allow the driver to be omitted if requested Allow the ns16550 debug UART to be used without the full driver. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Thomas Chou <thomas@wytron.com.tw> |
#
fcc0a877 |
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29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: serial: Convert ns16550 driver to use driver model PCI API Use the driver model version of the function to find the BAR. This updates the fdtdec function, of which ns16550 is the only user. The fdtdec_get_pci_bdf() function is dropped for several reasons: - with driver model we should use 'struct udevice *' rather than passing the device tree offset explicitly - there are no other users in the tree - the function parses for information which is already available in the PCI device structure (specifically struct pci_child_platdata which is available at dev_get_parent_platdata(dev) Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> |
#
b7e5a643 |
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04-Dec-2015 |
Simon Glass <sjg@chromium.org> |
dm: serial: ns16550: Add pre-reloc flag to the driver For platforms that don't use device tree in SPL the only way to mark this driver as 'required by relocation' is with the DM_FLAG_PRE_RELOC flag. Add this to ensure that the driver is bound. Fixes: fde7e18938d8 ("dm: tegra: pci: Move CONFIG_PCI_TEGRA to Kconfig") Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Stephen Warren <swarren@nvidia.com> Acked-by: Thomas Chou <thomas@wytron.com.tw> |
#
80e06146 |
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28-Nov-2015 |
Thomas Chou <thomas@wytron.com.tw> |
ns16550: change reg-shift property default to zero Change reg-shift property default to zero. When the integer property is missing, it should be taken as zero. This is consistent to Linux drivers/tty/serial/of_serial.c. The x86 and most powerpc use reg-shift of 0. Most others use reg-shift of 2. While reg-shift of 1 is rarely used. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
a51dbebf |
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16-Nov-2015 |
huang lin <hl@rock-chips.com> |
rockchip: serial driver support rk3036 Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
4fb60552 |
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19-Nov-2015 |
Thomas Chou <thomas@wytron.com.tw> |
ns16550: zap CONFIG_NS16550_SERIAL Zap CONFIG_NS16550_SERIAL, as the unification of ns16550 drivers is completed. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
8e62d32e |
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19-Nov-2015 |
Thomas Chou <thomas@wytron.com.tw> |
ns16550: add generic binding to unify the drivers Add generic binding to unify ns16550 drivers. There are several drivers using almost the same code, such as serial_dw, serial_keystone, serial_omap, serial_ppc, serial_rockchip, serial_tegra.c, and serial_x86. But each is platform specific. The key difference between these drivers is the way to get input clock frequency. With this unified approach, fixed clock frequency should be extracted from "clock-frequency" property of device tree blob. If this property is not available, the macro CONFIG_SYS_NS16550_CLK will be used. It can be a constant or a function to get clock, eg, get_serial_clock(). Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de> Acked-by: Simon Glass <sjg@chromium.org> |
#
77d7b5cd |
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19-Nov-2015 |
Thomas Chou <thomas@wytron.com.tw> |
ns16550: change map_sysmem to map_physmem Change map_sysmem() to map_physmem(,,MAP_NOCACHE). Though map_sysmem() can be used to map system memory, it might be wrong to use it for I/O ports. The map_physmem() serves the same purpose to translate physical address to virtual address with the additional flag to take care of cache property. Most drivers use map_physmem() since I/O ports access should be uncached. As ns16550 is a driver, it should use map_physmem() rather than map_sysmem(). Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org> |
#
97b05973 |
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18-Oct-2015 |
Simon Glass <sjg@chromium.org> |
debug_uart: Adjust the declaration of debug_uart_init() We want to be able to add other common code to this function. So change the driver's version to have an underscore before it, just like _debug_uart_putc(). Define debug_uart_init() to call this version. Update all drivers to this new method. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
4e9838c1 |
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11-Aug-2015 |
Simon Glass <sjg@chromium.org> |
dm: Use dev_get_addr() where possible This is a convenient way for a driver to get the hardware address of a device, when regmap or syscon are not being used. Change existing callers to use it as an example to others. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> |
#
0f925822 |
|
11-Aug-2015 |
Masahiro Yamada <masahiroy@kernel.org> |
of: clean up OF_CONTROL ifdef conditionals We have flipped CONFIG_SPL_DISABLE_OF_CONTROL. We have cleansing devices, $(SPL_) and CONFIG_IS_ENABLED(), so we are ready to clear away the ugly logic in include/fdtdec.h: #ifdef CONFIG_OF_CONTROL # if defined(CONFIG_SPL_BUILD) && !defined(SPL_OF_CONTROL) # define OF_CONTROL 0 # else # define OF_CONTROL 1 # endif #else # define OF_CONTROL 0 #endif Now CONFIG_IS_ENABLED(OF_CONTROL) is the substitute. It refers to CONFIG_OF_CONTROL for U-boot proper and CONFIG_SPL_OF_CONTROL for SPL. Also, we no longer have to cancel CONFIG_OF_CONTROL in include/config_uncmd_spl.h and scripts/Makefile.spl. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> |
#
6e780c7a |
|
23-Jun-2015 |
Simon Glass <sjg@chromium.org> |
ns16550: Improve debug UART so it can work with 32-bit access Since Rockchip requires 32-bit serial access, add this to the driver. Refactor a little to make this easier. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
90914008 |
|
12-May-2015 |
Simon Glass <sjg@chromium.org> |
dm: ns16550: Support CONFIG_SYS_NS16550_MEM32 with driver model This option is used by some boards, so support it with driver model. This is really ugly - we should rewrite this driver once all users are moved to driver model. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4f60166c |
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24-Apr-2015 |
Axel Lin <axel.lin@ingics.com> |
serial: ns16550: Remove hard-coded baud_divisor setting This was accidentally added by commit dd0b0122bacc "serial: ns16550: Add an option to specify the debug UART register shift". Remove it. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
ab9fd2e8 |
|
27-Feb-2015 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Remove unnecessary init on UART setup It is not necessary to write a zero baud rate to the device, and for some chips this will cause problems. Drop this code. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
363e6da1 |
|
27-Feb-2015 |
Simon Glass <sjg@chromium.org> |
dm: ns16550: Support non-byte register spacing with driver model Allow this driver to support boards where the register shift is not 0. This fixes some compiler warnings which appear in that case. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
dd0b0122 |
|
27-Feb-2015 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Add an option to specify the debug UART register shift This UART permits different register spacing. To support the debug UART on devices which have a spacing other than 1 byte, allow the shift value to be specified. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
0eb25b61 |
|
22-Mar-2015 |
Joe Hershberger <joe.hershberger@ni.com> |
common: Make sure arch-specific map_sysmem() is defined In the case where the arch defines a custom map_sysmem(), make sure that including just mapmem.h is sufficient to have these functions as they are when the arch does not override it. Also split the non-arch specific functions out of common.h Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
20379c11 |
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28-Feb-2015 |
Axel Lin <axel.lin@ingics.com> |
serial: ns16550: Fix build error due to a typo Fix trivial typo. Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Axel Lin <axel.lin@ingics.com> |
#
21d00436 |
|
26-Jan-2015 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support debug UART Add debug UART functions to permit ns16550 to provide an early debug UART. Try to avoid using the stack so that this can be called from assembler before a stack is set up (at least on ARM and PowerPC). Signed-off-by: Simon Glass <sjg@chromium.org> |
#
76571674 |
|
26-Jan-2015 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Add access functions that don't need platdata For the debug UART we need to be able to provide any parameters before driver model is set up. Add parameters to the low-level access functions to make this possible. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
3db886a5 |
|
31-Dec-2014 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Support ns16550 compatible pci uart devices There are many pci uart devices which are ns16550 compatible. We can describe them in the board dts file and use it as the U-Boot serial console as specified in the chosen node 'stdout-path' property. Those pci uart devices can have their register be memory-mapped, or i/o-mapped. The driver will try to use the memory-mapped register if the reg property in the node has an entry to describe the memory-mapped register, otherwise i/o-mapped register will be used. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
956a8bae |
|
10-Nov-2014 |
Gregoire Gentil <gregoire@gentil.com> |
ns16550.c: Fix for ns16550 driver hanging on OMAP4 The same problem that is seen on some OMAP3 is also seen on some OMAP4 so include them in the test in order to prevent some hangs during SPL. [trini: Re-word commit message, make apply cleanly] Signed-off-by: Tom Rini <trini@ti.com> |
#
1f77690e |
|
10-Oct-2014 |
Simon Glass <sjg@chromium.org> |
dm: serial: ns16550: Add a cast to the I/O operations This generates a warning when driver model is enabled, so fix it by adding a cast. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
11c1a878 |
|
22-Oct-2014 |
Simon Glass <sjg@chromium.org> |
dm: ns16550: Correct the probe logic for platform data The probe logic sets up the pointer to the platform data in the device tree decode method. It should be done in the probe() method, and anyway the device tree decode method can't be used when CONFIG_OF_CONTROL is not enabled. Fix these two problems. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@ti.com> |
#
167efe01 |
|
22-Oct-2014 |
Simon Glass <sjg@chromium.org> |
dm: ns16550: Use an address instead of a pointer for the uart base It is inconvenient to have to use casts when specifying platform data. Also it is not strictly correct, since we should use map_sysmem() to convert an address to a pointer. Adjust the platform data to use an address. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@ti.com> |
#
aea2be20 |
|
22-Oct-2014 |
Simon Glass <sjg@chromium.org> |
dm: serial: ns16550: Correct logic for checking for character There is a bug in the logic which checks for an available character. This can cause invalid characters to be received - this was noticed on beaglebone. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@ti.com> |
#
12e431b2 |
|
04-Sep-2014 |
Simon Glass <sjg@chromium.org> |
dm: serial: Add driver model support for ns16550 Add driver model support so that ns16550 can support operation both with and without driver model. The driver needs a clock frequency so cannot stand alone unfortunately. The clock frequency must be provided by a separate driver. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8bbe33c8 |
|
04-Sep-2014 |
Simon Glass <sjg@chromium.org> |
dm: serial: Collect common baud rate code in ns16550 The same sequence is used in several places, so move it into a function. Note that UART_LCR_BKSE is an alias for UART_LCR_DLAB. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
fa54eb12 |
|
04-Sep-2014 |
Simon Glass <sjg@chromium.org> |
dm: serial: Move baud rate calculation to ns16550.c Move the function that calculates the baud rate divisor into ns16550.c so it can be used by that file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8ac22a60 |
|
30-Jul-2014 |
Masahiro Yamada <masahiroy@kernel.org> |
omap: clean-up dead configs The following configs are not defined at all. - CONFIG_OMAP1510 - CONFIG_OMAP_1510P1 - CONFIG_OMAP_SX1 - CONFIG_OMAP3_DMA - CONFIG_OMAP3_ZOOM2 - CONFIG_OMAP_INNOVATOR Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Tom Rini <trini@ti.com> |
#
7c387646 |
|
15-Jul-2014 |
Khoronzhuk, Ivan <ivan.khoronzhuk@ti.com> |
keystone2: use CONFIG_SOC_KEYSTONE in common places Use CONFIG_SOC_KEYSTONE in common places instead of defining a lot of "if def .. || if def " for different Keystone2 SoC types. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> |
#
d57dee57 |
|
09-Apr-2014 |
Karicheri, Muralidharan <m-karicheri2@ti.com> |
serial: nsl16550: add hw flow control support keystone serial hw support hw flow control. This patch enables hw flow control for keystone EVMs as an optional feature based on CONFIG_SERIAL_HW_FLOW_CONTROL. Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> |
#
ef509b90 |
|
04-Apr-2014 |
Vitaly Andrianov <vitalya@ti.com> |
k2hk: add support for k2hk SOC and EVM k2hk EVM is based on Texas Instruments Keystone2 Hawking/Kepler SoC. Keystone2 SoC has ARM v7 Cortex-A15 MPCore processor. Please refer the ti/k2hk_evm/README for details on the board, build and other information. This patch add support for keystone architecture and k2hk evm. Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: WingMan Kwok <w-kwok2@ti.com> Signed-off-by: Sandeep Nair <sandeep_n@ti.com> |
#
456ccfdf |
|
20-Dec-2013 |
Tom Rini <trini@konsulko.com> |
TI:omap3: Drop omap3_zoom2 The omap3_zoom2 board has not been updated for a correct CONFIG_SYS_HZ and Tom Rix's email has long been bouncing. Signed-off-by: Tom Rini <trini@ti.com> |
#
9ed6e412 |
|
01-Jul-2013 |
TENART Antoine <atenart@adeneo-embedded.com> |
Prepare for TI816X : reuse existing code from TI814X Rename some CONFIG_TI814X to a more generic CONFIG_TI81XX Signed-off-by: Antoine Tenart <atenart@adeneo-embedded.com> [trini: Adapt for CONFIG_OMAP_COMMON changes, AM43XX] Signed-off-by: Tom Rini <trini@ti.com> |
#
57180408 |
|
30-Jul-2013 |
Lokesh Vutla <lokeshvutla@ti.com> |
ARM: AM43xx: Add build support Add AM43xx support in the required places Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> |
#
7f5eef93 |
|
03-Jun-2013 |
Tom Rini <trini@konsulko.com> |
arm: Remove OMAP2420H4 and all omap24xx support The omap2420H4 was the only mainline omap24xx board. Prior to being fixed by Jon Hunter in time for v2013.04 it had been functionally broken for a very long time. Remove this board as there's not been interest in it in U-Boot for quite a long time. Signed-off-by: Tom Rini <trini@ti.com> |
#
fd2aeac5 |
|
28-Mar-2013 |
Manfred Huber <man.huber@arcor.de> |
omap3_beagle: Flush UART3 xmit on enable if TEMT is broken Flush UART3 xmit on enable if TEMT is broken On some OMAP3 devices when UART3 is configured for boot mode before SPL starts only THRE bit is set. We have to empty the transmitter before initialization starts. This patch avoids the use of CONFIG_SYS_NS16550_BROKEN_TEMT. Signed-off-by: Manfred Huber <man.huber@arcor.de> Tested-by: Javier Martinez Canillas <javier@dowhile0.org> Tested-by: Andreas Bießmann <andreas.devel@googlemail.com> |
#
6213a68f |
|
15-Mar-2013 |
Matt Porter <mporter@ti.com> |
ns16550: enable quirks for ti814x TI814X requires the same quirks as AM33XX to be enabled. Signed-off-by: Matt Porter <mporter@ti.com> Reviewed-by: Tom Rini <trini@ti.com> |
#
69e06832 |
|
05-Mar-2013 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Remove unwanted cast This cast does not seem correct, since we should be writing to a pointer, not a ulong. This fixes the following warning on nds32: -ns16550.c:49: warning: passing argument 2 of 'writeb' makes pointer from integer without a cast Signed-off-by: Simon Glass <sjg@chromium.org> |
#
7de0fe1a |
|
06-Jan-2013 |
Javier Martinez Canillas <javier@dowhile0.org> |
serial/ns16550: add an option to avoid hanging on broken platforms Some platforms (e.g. IGEPv2 board) has a broken ns16550 UART that does not set the TEMT bit when the transmitter is empty in SPL. This makes U-Boot to hang while waiting for TEMT to be set. Add a new option to avoid this: CONFIG_SYS_NS16550_BROKEN_TEMT 16550 UART set the Transmitter Empty (TEMT) Bit when all output has finished and the transmitter is totally empty. U-Boot waits for this bit to be set to initialize the serial console. On some broken platforms this bit is not set in SPL making U-Boot to hang while waiting for TEMT. Define this option to avoid it. Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> |
#
cb55b332 |
|
18-Sep-2012 |
Scott Wood <scottwood@freescale.com> |
serial/ns16550: wait for TEMT before initializing TEMT is set when the transmitter is totally empty and all output has finished. This prevents output problems (including a loss of synchronization observed on p2020 that persisted for quite a while) if SPL has output still on its way out. Signed-off-by: Scott Wood <scottwood@freescale.com> -- v2: fixed typo in subject, and explained what the bit does in the changelog |
#
f2041388 |
|
15-Sep-2012 |
Marek Vasut <marex@denx.de> |
serial: ns16550: Call usbtty_poll only in non-SPL build Having both USBTTY and CONFIG_SERIAL_MULTI enabled in SPL, the usbtty.c file is protected in Makefile to not be compiled into the SPL. Yet, the ns16550 serial driver does not contain such protection. Add it to avoid missing symbol error. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Marek Vasut <marek.vasut@gmail.com> Cc: Tom Rini <trini@ti.com> |
#
99b603e7 |
|
09-Jul-2012 |
Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com> |
serial/ns16550: ns16550 has a different register layout on SOC_DA8XX also fix NS16550_init() as we need 16x divider Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com> Acked-by: Christian Riesch <christian.riesch@omicron.at> Tested-by: Christian Riesch <christian.riesch@omicron.at> Acked-by: Sughosh Ganu <urwithsughosh@gmail.com> Tested-by: Sughosh Ganu <urwithsughosh@gmail.com> |
#
5289e83a |
|
13-Oct-2011 |
Chandan Nath <chandan.nath@ti.com> |
ARM:AM33XX: Add support for TI AM335X EVM This patch adds basic support for booting the board. This patch adds support for the UART necessary to get to the u-boot prompt. Signed-off-by: Chandan Nath <chandan.nath@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> |
#
f8df9d0d |
|
15-Oct-2011 |
Simon Glass <sjg@chromium.org> |
NS16550: trivial code clean for checkpatch This removes most checkpatch warnings from the ns16550 driver and its header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
79df1208 |
|
01-Sep-2011 |
Dave Aldridge <fovsoft@gmail.com> |
ns16550: change to allow 32 bit access to registers If CONFIG_SYS_NS16550_MEM32 is defined then 32 bit memory mapped access will be used to read/write the uart registers. This is especially useful for SoC devices that implement 16550 compatible uarts but that have peripheral access width constraints. Signed-off-by: Dave Aldridge <fovsoft@gmail.com> |
#
a160ea0b |
|
27-Oct-2010 |
Prafulla Wadaskar <prafulla@marvell.com> |
Serial: ns16550: Add support for CONFIG_SYS_NS16550_IER macro On some processors this ier register configuration is different for ex. Marvell Armada100 This patch introduce CONFIG_SYS_NS16550_IER macro support to unconditionally initialize this register. Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com> |
#
1a2d9b30 |
|
12-Oct-2010 |
Stefan Roese <sr@denx.de> |
ns16550: Add WATCHDOG_RESET to putc for short watchdog timeout boards Call watchdog_reset() upon newline. This is done here in putc since the environment code uses a single puts() to print the complete envrironment upon "printenv". So we can't put this watchdog call in puts(). This is needed for boards with a very short watchdog timeout, like the lwmon5 with a 100ms timeout. Without this patch this board resets in the commands with long outputs, like "printenv" or "fdt print". Note that the image size is not increased with this patch when CONFIG_HW_WATCHDOG or CONFIG_WATCHDOG are not defined since the compiler optimizes this additional code away. Signed-off-by: Stefan Roese <sr@denx.de> Fix typo in comment. Signed-off-by: Wolfgang Denk <wd@denx.de> |
#
167cdad1 |
|
23-Apr-2010 |
Graeme Russ <graeme.russ@gmail.com> |
SERIAL: Enable port-mapped access The x86 architecture exclusively uses Port-Mapped I/O (inb/outb) to access the 16550 UARTs. This patch mimics how Linux selects between Memory-Mapped and Port-Mapped I/O. This allows x86 boards to use CONFIG_SERIAL_MUTLI and drop the custom serial port driver Signed-off-by: Graeme Russ <graeme.russ@gmail.com> |
#
a47a12be |
|
15-Apr-2010 |
Stefan Roese <sr@denx.de> |
Move arch/ppc to arch/powerpc As discussed on the list, move "arch/ppc" to "arch/powerpc" to better match the Linux directory structure. Please note that this patch also changes the "ppc" target in MAKEALL to "powerpc" to match this new infrastructure. But "ppc" is kept as an alias for now, to not break compatibility with scripts using this name. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Wolfgang Denk <wd@denx.de> Acked-by: Detlev Zundel <dzu@denx.de> Acked-by: Kim Phillips <kim.phillips@freescale.com> Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Anatolij Gustschin <agust@denx.de> |
#
a1b322a9 |
|
01-Feb-2010 |
Ladislav Michl <ladis@linux-mips.org> |
ns16550: kick watchdog while waiting for a character ns16550 busyloops waiting for incoming byte causing watchdog to reboot while waiting for a key press. A call to WATCHDOG_RESET in NS16550_getc loop fixes it. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> |
#
660888b7 |
|
30-May-2009 |
Tom Rix <Tom.Rix@windriver.com> |
ZOOM2 Add serial support. Zoom2 serial is in general supplied by one of the 4 UARTS on the debug board. The default serial is from the USB connector on left side of the debug board. The USB connector will produce 2 of the 4 UARTS. On your host pick the first enumeration. The details of the setting of the serial gpmc setup are not available. The values were provided by another party. The serial port set up is the same with Zoom1. Baud rate 115200, 8 bit data, no parity, 1 stop bit, no flow. The kernel bootargs are console=ttyS3,115200n8 Signed-off-by: Tom Rix <Tom.Rix@windriver.com> |
#
200779e3 |
|
03-Apr-2009 |
Detlev Zundel <dzu@denx.de> |
Rename common ns16550 constants with UART_ prefix to prevent conflicts Fix problems introduced in commit 7b5611cdd12ca0cc33f994f0d4a4454788fc3124 [inka4x0: Add hardware diagnosis functions for inka4x0] which redefined MSR_RI which is already used on PowerPC systems. Also eliminate redundant definitions in ps2mult.h. More cleanup will be needed for other redundant occurrences though. Signed-off-by: Detlev Zundel <dzu@denx.de> |
#
b4746d8b |
|
11-Feb-2009 |
Mike Frysinger <vapier@gentoo.org> |
drivers/serial/ns16550: move ifdef into Makefile COBJS-$(...) Signed-off-by: Mike Frysinger <vapier@gentoo.org> |
#
f5675aa5 |
|
18-Feb-2009 |
Ron Madrid <ron_madrid@sbcglobal.net> |
Create configuration option for restricted ns16550 functions This patch will create a configuration option for a minimum configuration for the ns16550 serial driver at drivers/serial/ns16550.c and will apply this new configuration option to the SIMPC8313.h config file in order to fix the NAND bootstrap build error. This option will exclude all functions with exception of NS16550_putc and NS16550_init. This will be used primarily to save space and remove unused code from builds in which space is limited. Signed-off-by: Ron Madrid <ron_madrid@sbcglobal.net> |
#
6d0f6bcf |
|
16-Oct-2008 |
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
rename CFG_ macros to CONFIG_SYS Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
#
7ec8bb15 |
|
27-Dec-2007 |
Wolfgang Denk <wd@denx.de> |
OMAP5912: fix FIFO handling in UART driver According to the OMAP5912 Serial Interfaces Reference Guide (see http://focus.ti.com/lit/ug/spru760c/spru760c.pdf, page 150), the FIFO_EN enable bit in the FIFO Control Register (FCR) can only be changed when the baud clock is not running, i. e. when both DLL and DLH are set to 0. Thus make sure that DLL and DLH are 0 when writing the FCR. Signed-off-by: Wolfgang Denk <wd@denx.de> |
#
1378df79 |
|
24-Nov-2007 |
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
drivers/serial : move serial drivers to drivers/serial Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
#
6e7df1d1 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
global: Finish CONFIG -> CFG migration At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
91092132 |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_NS16550_* to CFG_SYS_NS16550_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NS16550 namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
57c3afbc |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
powerpc: Rename CONFIG_NS16550_MIN_FUNCTIONS This symbol is specific to the PowerPC SPL implementation, so rename this to reflect that it's in SPL and used / tested there, so that we can then safely migrate it to Kconfig. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
29caf930 |
|
02-Sep-2022 |
Stefan Roese <sr@denx.de> |
cyclic: Use schedule() instead of WATCHDOG_RESET() Globally replace all occurances of WATCHDOG_RESET() with schedule(), which handles the HW_WATCHDOG functionality and the cyclic infrastructure. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Tom Rini <trini@konsulko.com> [am335x_evm, mx6cuboxi, rpi_3,dra7xx_evm, pine64_plus, am65x_evm, j721e_evm] |
#
5e998b4d |
|
23-Jun-2022 |
Pali Rohár <pali@kernel.org> |
serial: ns16550: Wait in debug_uart_init until tx buffer is empty Commit d293759d55cc ("serial: ns16550: Add support for SPL_DEBUG_UART_BASE") fixed support for setting correct early debug UART base address in SPL. But after this commit, output from Marvell A385 BootROM is truncated or lost and not fully present on serial console. Debugging this issue showed that BootROM just put bytes into UART HW output buffer and does not wait until UART HW transmit all characters. U-Boot ns16550 early debug is initialized very early and during its initialization is resetting UART HW and flushing remaining transmit buffer (which still contains BootROM output). Fix this issue by waiting in init function prior resetting UART HW until TxEmpty bit in UART Line Status Register is set. TxEmpty is set when all remaining bytes from HW buffer are transmitted. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> [trini: Add comment, move ';' to new line per checkpatch.pl] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
d293759d |
|
06-May-2022 |
Pali Rohár <pali@kernel.org> |
serial: ns16550: Add support for SPL_DEBUG_UART_BASE Use CONFIG_VAL(DEBUG_UART_BASE) instead of CONFIG_DEBUG_UART_BASE, so proper config value (CONFIG_DEBUG_UART_BASE or CONFIG_SPL_DEBUG_UART_BASE) is used based on building target. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
04ee76c9 |
|
09-Apr-2022 |
Johan Jonker <jbx6244@gmail.com> |
rockchip: serial: move driver alias to serial_rockchip.c The Rockchip uart DT nodes have "snps,dw-apb-uart" as fall back string. The driver ns16550.c has CONFIG_IS_ENABLED(OF_REAL) as condition to of_match and does not copy dtplat data. For TPL/SPL the driver serial_rockchip.c is used. Move driver alias to correct driver. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
f899cc14 |
|
12-Sep-2021 |
Tom Rini <trini@konsulko.com> |
ti: keystone: Move away from CONFIG_SOC_KEYSTONE We have individual SOC symbols for each keystone 2 platform. Use the existing CONFIG_ARCH_KEYSTONE rather than CONFIG_SOC_KEYSTONE to encompass all of the keystone families. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
414cc151 |
|
07-Aug-2021 |
Simon Glass <sjg@chromium.org> |
treewide: Simply conditions with the new OF_REAL Use this new Kconfig to simplify the compilation conditions where appropriate. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
384b62c0 |
|
03-Feb-2021 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Handle zero <clock-frequency> value A working device tree node of ns16550 should never be populated with value zero for the <clock-frequency> property. Unfortunately this is the case for the QEMU ppce500 target. Let's try to assign plat->clock to CONFIG_SYS_NS16550_CLK as the last resort to handle such case. This commit should be reverted when: - The following QEMU patch [1] is merged, and - U-Boot CI has upgraded its QEMU version that contains the fix [1] http://patchwork.ozlabs.org/project/qemu-devel/patch/1612362288-22216-2-git-send-email-bmeng.cn@gmail.com/ Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
09bd0840 |
|
03-Feb-2021 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Correct the base address type Currently ns16550_serial_assign_base() treats the argument 'base' with type `ulong`. This is incorrect because the base address was obtained from device tree with type `fdt_addr_t` that can represent a physical address larger than 32-bit in a 32-bit system. Fixes: 9e6ce62190b7 ("serial: ns16550: Fix ordering of getting base address") Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
401d1c4f |
|
30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
bdf8fd76 |
|
28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
0fd3d911 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com> |
#
2d6bf754 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
#
d30c7209 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo |
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de> |
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> |
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se> |
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> |
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com |
#
9ad3b049 |
|
02-Nov-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: add setconfig support Add possibility to update the serial parity used. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com> |
#
46879196 |
|
24-Oct-2018 |
Bin Meng <bmeng.cn@gmail.com> |
serial: Remove DM_FLAG_PRE_RELOC flag in various drivers When a driver declares DM_FLAG_PRE_RELOC flag, it wishes to be bound before relocation. However due to a bug in the DM core, the flag only takes effect when devices are statically declared via U_BOOT_DEVICE(). This bug has been fixed recently by commit "dm: core: Respect drivers with the DM_FLAG_PRE_RELOC flag in lists_bind_fdt()", but with the fix, it has a side effect that all existing drivers that declared DM_FLAG_PRE_RELOC flag will be bound before relocation now. This may expose potential boot failure on some boards due to insufficient memory during the pre-relocation stage. To mitigate this potential impact, the following changes are implemented: - Remove DM_FLAG_PRE_RELOC flag in the driver, if the driver only supports configuration from device tree (OF_CONTROL) - Keep DM_FLAG_PRE_RELOC flag in the driver only if the device is statically declared via U_BOOT_DEVICE() - Surround DM_FLAG_PRE_RELOC flag with OF_CONTROL check, for drivers that support both statically declared devices and configuration from device tree Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
6f57c344 |
|
09-Aug-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), let's rather ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
5d754197 |
|
27-Aug-2018 |
Lokesh Vutla <lokeshvutla@ti.com> |
serial: omap: Introduce DM specific omap serial Add driver model support for OMAP_SERIAL while reusing the functions in ns16550.c Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Tested-by: Derald D. Woods <woods.technical@gmail.com> |
#
b051eecb |
|
14-Jun-2018 |
Ley Foon Tan <ley.foon.tan@intel.com> |
serial: ns16550: Add reset ctrl to driver Add code to reset all reset signals as in serial DT node. A reset property is an optional feature, so do not fail if a reset property is not present. If a reset property is discovered, then use it to deassert, thus bringing the IP out of reset. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
78b7d37b |
|
15-Feb-2018 |
Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> |
ns16550: Fix mem mapped endian check Do a explicit check for CONFIG_SYS_BIG_ENDIAN and CONFIG_SYS_LITTLE_ENDIAN to avoid errors on platforms where both are undefined (x86). Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> Reviewed-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com> |
#
4dbf9bed |
|
15-Jan-2018 |
Mario Six <mario.six@gdsys.cc> |
serial: ns16550: Fix style violation Clarify the computation precedence in two ternary operator constructions. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc> |
#
7fded0ce |
|
16-Aug-2017 |
Stefan Roese <sr@denx.de> |
Revert "serial: ns16550: Add RX interrupt buffer support" This reverts commit 6822cf3ec7c8768b8727573b8f4b2cb3d870b881. As Bin Meng has tested and pointed out, we don't need the RX interrupt for the RX buffer support at all. Just reading all available characters into a buffer is sufficient to solve the problem with the dropped characters upon long lines pasted into the U-Boot prompt. Since this RX buffer support can be implemented in a generic way, without any device specifica (e.g. for the ns16550), I'll post a new patch with a new serial RX buffer support for DM, which all DM based serial drivers can use. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
6822cf3e |
|
14-Jul-2017 |
Stefan Roese <sr@denx.de> |
serial: ns16550: Add RX interrupt buffer support Pasting longer lines into the U-Boot console prompt sometimes leads to characters missing. One problem here is the small 16-byte FIFO of the legacy NS16550 UART, e.g. on x86 platforms. This patch now introduces a Kconfig option to enable RX interrupt buffer support for NS16550 style UARTs. With this option enabled, I was able paste really long lines into the U-Boot console, without any characters missing. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> [trini: Guard ns16550_serial_remove with CONFIG_IS_ENABLED(SERIAL_PRESENT) to match struct assignment] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
8d3a2568 |
|
11-Jul-2017 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-dm
|
#
db9f8f6a |
|
12-Jun-2017 |
Simon Glass <sjg@chromium.org> |
dm: serial: ns16550: Convert to livetree Update this driver to support a live device tree. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Tested-on: Beaver, Jetson-TK1 |
#
3d40479f |
|
07-Jun-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
rockchip: ns16550: dm: convert fdt_get to dev_read With the new dev_read functions available, we can convert the rockchip architecture-specific drivers and common drivers used by these devices over to the dev_read family of calls. This covers the serial driver (ns16550 and compatible) used for the Rockchip devices. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
a821c4af |
|
17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: Rename dev_addr..() functions These support the flat device tree. We want to use the dev_read_..() prefix for functions that support both flat tree and live tree. So rename the existing functions to avoid confusion. In the end we will have: 1. dev_read_addr...() - works on devices, supports flat/live tree 2. devfdt_get_addr...() - current functions, flat tree only 3. of_get_address() etc. - new functions, live tree only All drivers will be written to use 1. That function will in turn call either 2 or 3 depending on whether the flat or live tree is in use. Note this involves changing some dead code - the imx_lpi2c.c file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
89024ddc |
|
12-May-2017 |
Tom Rini <trini@konsulko.com> |
TI: Drop 'CONFIG_OMAP' In the two cases in the code where we use CONFIG_OMAP as a useful test currently we can make use of CONFIG_ARCH_OMAP2PLUS instead. With that changed we can drop all defines of CONFIG_OMAP. While in here, CONFIG_OMAP3430 is only defined and then never used, so drop. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
a52cf086 |
|
22-Apr-2017 |
Lokesh Vutla <lokeshvutla@ti.com> |
serial: omap: Support debug UART Add debug UART functions to permit omap specific ns16550 to provide an early debug UART. This is mostly in common with DEBUG_UART_NS16550 except for Mode definition register which is required for selecting UART mode(16x auto-baud or 13x mode). Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
6f8c351e |
|
27-Mar-2017 |
Alexandru Gagniuc <alex.g@adaptrum.com> |
serial: ns16550: Link in the DM driver when when using platdata Do not condition the compilation of the U_BOOT_DRIVER by !OF_PLATDATA. This is inconsistent with the majority of other drivers. This also blocks OF_PLATDATA boards with an 16550-compatible serial from using serial in SPL. Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com> Reviewed-by: Simon Glass <sjg@chromium.org> Added tweak for rock to avoid a TPL build failure: Signed-off-by: Simon Glass <sjg@chromium.org> |
#
e160f7d4 |
|
17-Jan-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
17fa0326 |
|
18-Jan-2017 |
Heiko Schocher <hs@denx.de> |
serial, ns16550: bugfix: ns16550 fifo not enabled commit: 65f83802b7a5b "serial: 16550: Add getfcr accessor" breaks u-boot commandline working with long commands sending to the board. Since the above patch, you have to setup the fcr register. For board/archs which enable OF_PLATDATA, the new field fcr in struct ns16550_platdata is not filled with a default value ... This leads in not setting up the uarts fifo, which ends in problems, when you send long commands to u-boots commandline. Detected this issue with automated tbot tests on am335x based shc board. The error does not popup, if you type commands. You need to copy&paste a long command to u-boots commandshell (or send a long command with tbot) Possible boards/plattforms with problems: ./arch/arm/cpu/arm926ejs/lpc32xx/devices.c ./arch/arm/mach-tegra/board.c ./board/overo/overo.c ./board/quipos/cairo/cairo.c ./board/logicpd/omap3som/omap3logic.c ./board/logicpd/zoom1/zoom1.c ./board/timll/devkit8000/devkit8000.c ./board/lg/sniper/sniper.c ./board/ti/beagle/beagle.c ./drivers/serial/serial_rockchip.c Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Tested-by: Adam Ford <aford173@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
0b060eef |
|
30-Nov-2016 |
Marek Vasut <marex@denx.de> |
serial: 16550: Add Ingenic JZ4780 support Add compatibility string for the Ingenic JZ4780 SoC, the necessary UART enable bit into FCR and register shift. Neither are encoded in the DTS coming from Linux, so we need to support it this way. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
79fd9281 |
|
30-Nov-2016 |
Marek Vasut <marex@denx.de> |
serial: 16550: Add port type as driver data Add driver data to each compatible string to identify the type of the port. Since all the ports in the driver are entirely compatible with 16550 for now, all are marked with PORT_NS16550. But, there are ports which have specific quirks, like the JZ4780 UART, which do not have any DT property to denote the quirks. Instead, Linux uses the compatible string to discern such ports and enable the necessary quirks. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> |
#
65f83802 |
|
30-Nov-2016 |
Marek Vasut <marex@denx.de> |
serial: 16550: Add getfcr accessor Add function which allows fetching the default FCR register setting from platform data for DM , while retaining old behavior for non-DM by returning UART_FCRVAL. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
021abf69 |
|
26-Sep-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
Revert "ns16650: Make sure we have CONFIG_CLK set before using infrastructure" This reverts commit 82f5279b0cd99a9163d34cfe926d0316d9dc0d37. The build failure of k2*evm boards was fixed in a different way by the previous commit. It is nasty to patch generic drivers around with #ifdef CONFIG_CLK just for the KeyStone's matter. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
ab895d6a |
|
30-Sep-2016 |
Alexandre Courbot <acourbot@nvidia.com> |
serial: ns16550: Handle -ENOENT when requesting clock When calling clk_get_by_index(), fall back to the legacy method of getting the clock if -ENOENT is returned. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> |
#
82f5279b |
|
22-Sep-2016 |
Tom Rini <trini@konsulko.com> |
ns16650: Make sure we have CONFIG_CLK set before using infrastructure We cannot call on the CONFIG_CLK based clk_get_rate function unless CONFIG_CLK is set. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
50fce1d5 |
|
08-Sep-2016 |
Paul Burton <paul.burton@mips.com> |
serial: ns16550: Support clocks via phandle Previously ns16550 compatible UARTs probed via device tree have needed their device tree nodes to contain a clock-frequency property. An alternative to this commonly used with Linux is to reference a clock via a phandle. This patch allows U-Boot to support that, retrieving the clock frequency by probing the appropriate clock device. For example, a system might choose to provide the UART base clock as a reference to a clock common to multiple devices: sys_clk: clock { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <10000000>; }; uart0: uart@10000000 { compatible = "ns16550a"; reg = <0x10000000 0x1000>; clocks = <&sys_clk>; }; uart1: uart@10000000 { compatible = "ns16550a"; reg = <0x10001000 0x1000>; clocks = <&sys_clk>; }; This removes the need for the frequency information to be duplicated in multiple nodes and allows the device tree to be more descriptive of the system. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
b2927fba |
|
04-Jul-2016 |
Simon Glass <sjg@chromium.org> |
dm: serial: ns16550: Update to support of-platdata With of-platdata this driver cannot know the format of the of-platdata struct, so we cannot use generic code for accessing the of-platdata. Each SoC that uses this driver will need to set up ns16550's platdata for it. So don't compile in the generic code. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
03c6f176 |
|
24-May-2016 |
Marek Vasut <marex@denx.de> |
serial: 16550: Drop OMAP1510 support The CONFIG_OMAP1510 is no longer defined, so remove this dead code. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Nishanth Menon <nm@ti.com> |
#
fa4ce723 |
|
24-May-2016 |
Marek Vasut <marex@denx.de> |
serial: 16550: Make serial_io/out_shift available to debug mode The ns16550 driver needs serial_in_shift() and serial_out_shift() when compiled in debug UART mode, so shift the DM_SERIAL check a little to make these functions available. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
df8ec55d |
|
17-May-2016 |
Paul Burton <paul.burton@mips.com> |
dm: ns16550: Don't map_physmem for I/O ports If the UART is to be accessed using I/O port accessors (inb & outb) then using map_physmem doesn't make sense, since it operates in a different memory space. Remove the call to map_physmem when CONFIG_SYS_NS16550_PORT_MAPPED is defined, allowing I/O port addresses to not be mangled by the incorrect mapping. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> |
#
59b35ddd |
|
16-Feb-2016 |
Michal Simek <michal.simek@amd.com> |
dm: ns16550: Add support for reg-offset property reg-offset is the part of standard 8250 binding in the kernel. It is shifting start of address space by reg-offset. On Xilinx platform this offset is typically 0x1000. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Moved the new field to the end of the struct to avoid problems: Signed-off-by: Simon Glass <sjg@chromium.org> |
#
e5e88c65 |
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29-Feb-2016 |
Tom Rini <trini@konsulko.com> |
Revert "dm: ns16550: Add support for reg-offset property" This reverts commit d9a3bec682f9756621615f4306718a356a3230e3. While this is a correct change to do long term it unfortunately breaks a number of platforms that are using pdata and not named struct members so they are getting all of their data after 'base' incorrect. Acked-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
d9a3bec6 |
|
16-Feb-2016 |
Michal Simek <michal.simek@amd.com> |
dm: ns16550: Add support for reg-offset property reg-offset is the part of standard 8250 binding in the kernel. It is shifting start of address space by reg-offset. On Xilinx platform this offset is typically 0x1000. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
cc4228f9 |
|
14-Dec-2015 |
Thomas Chou <thomas@wytron.com.tw> |
ns16550: zap the rockchip serial compatible string Zap the rockchip serial compatible string, because rockchip serial has "snps,dw-apb-uart" compatible string in the dts. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org> |
#
b7e29834 |
|
13-Dec-2015 |
Simon Glass <sjg@chromium.org> |
dm: ns16550: Allow the driver to be omitted if requested Allow the ns16550 debug UART to be used without the full driver. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Thomas Chou <thomas@wytron.com.tw> |
#
fcc0a877 |
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29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: serial: Convert ns16550 driver to use driver model PCI API Use the driver model version of the function to find the BAR. This updates the fdtdec function, of which ns16550 is the only user. The fdtdec_get_pci_bdf() function is dropped for several reasons: - with driver model we should use 'struct udevice *' rather than passing the device tree offset explicitly - there are no other users in the tree - the function parses for information which is already available in the PCI device structure (specifically struct pci_child_platdata which is available at dev_get_parent_platdata(dev) Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> |
#
b7e5a643 |
|
04-Dec-2015 |
Simon Glass <sjg@chromium.org> |
dm: serial: ns16550: Add pre-reloc flag to the driver For platforms that don't use device tree in SPL the only way to mark this driver as 'required by relocation' is with the DM_FLAG_PRE_RELOC flag. Add this to ensure that the driver is bound. Fixes: fde7e18938d8 ("dm: tegra: pci: Move CONFIG_PCI_TEGRA to Kconfig") Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Stephen Warren <swarren@nvidia.com> Acked-by: Thomas Chou <thomas@wytron.com.tw> |
#
80e06146 |
|
28-Nov-2015 |
Thomas Chou <thomas@wytron.com.tw> |
ns16550: change reg-shift property default to zero Change reg-shift property default to zero. When the integer property is missing, it should be taken as zero. This is consistent to Linux drivers/tty/serial/of_serial.c. The x86 and most powerpc use reg-shift of 0. Most others use reg-shift of 2. While reg-shift of 1 is rarely used. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
a51dbebf |
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16-Nov-2015 |
huang lin <hl@rock-chips.com> |
rockchip: serial driver support rk3036 Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
4fb60552 |
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19-Nov-2015 |
Thomas Chou <thomas@wytron.com.tw> |
ns16550: zap CONFIG_NS16550_SERIAL Zap CONFIG_NS16550_SERIAL, as the unification of ns16550 drivers is completed. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
8e62d32e |
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19-Nov-2015 |
Thomas Chou <thomas@wytron.com.tw> |
ns16550: add generic binding to unify the drivers Add generic binding to unify ns16550 drivers. There are several drivers using almost the same code, such as serial_dw, serial_keystone, serial_omap, serial_ppc, serial_rockchip, serial_tegra.c, and serial_x86. But each is platform specific. The key difference between these drivers is the way to get input clock frequency. With this unified approach, fixed clock frequency should be extracted from "clock-frequency" property of device tree blob. If this property is not available, the macro CONFIG_SYS_NS16550_CLK will be used. It can be a constant or a function to get clock, eg, get_serial_clock(). Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de> Acked-by: Simon Glass <sjg@chromium.org> |
#
77d7b5cd |
|
19-Nov-2015 |
Thomas Chou <thomas@wytron.com.tw> |
ns16550: change map_sysmem to map_physmem Change map_sysmem() to map_physmem(,,MAP_NOCACHE). Though map_sysmem() can be used to map system memory, it might be wrong to use it for I/O ports. The map_physmem() serves the same purpose to translate physical address to virtual address with the additional flag to take care of cache property. Most drivers use map_physmem() since I/O ports access should be uncached. As ns16550 is a driver, it should use map_physmem() rather than map_sysmem(). Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org> |
#
97b05973 |
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18-Oct-2015 |
Simon Glass <sjg@chromium.org> |
debug_uart: Adjust the declaration of debug_uart_init() We want to be able to add other common code to this function. So change the driver's version to have an underscore before it, just like _debug_uart_putc(). Define debug_uart_init() to call this version. Update all drivers to this new method. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
4e9838c1 |
|
11-Aug-2015 |
Simon Glass <sjg@chromium.org> |
dm: Use dev_get_addr() where possible This is a convenient way for a driver to get the hardware address of a device, when regmap or syscon are not being used. Change existing callers to use it as an example to others. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> |
#
0f925822 |
|
11-Aug-2015 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
of: clean up OF_CONTROL ifdef conditionals We have flipped CONFIG_SPL_DISABLE_OF_CONTROL. We have cleansing devices, $(SPL_) and CONFIG_IS_ENABLED(), so we are ready to clear away the ugly logic in include/fdtdec.h: #ifdef CONFIG_OF_CONTROL # if defined(CONFIG_SPL_BUILD) && !defined(SPL_OF_CONTROL) # define OF_CONTROL 0 # else # define OF_CONTROL 1 # endif #else # define OF_CONTROL 0 #endif Now CONFIG_IS_ENABLED(OF_CONTROL) is the substitute. It refers to CONFIG_OF_CONTROL for U-boot proper and CONFIG_SPL_OF_CONTROL for SPL. Also, we no longer have to cancel CONFIG_OF_CONTROL in include/config_uncmd_spl.h and scripts/Makefile.spl. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> |
#
6e780c7a |
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23-Jun-2015 |
Simon Glass <sjg@chromium.org> |
ns16550: Improve debug UART so it can work with 32-bit access Since Rockchip requires 32-bit serial access, add this to the driver. Refactor a little to make this easier. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
90914008 |
|
12-May-2015 |
Simon Glass <sjg@chromium.org> |
dm: ns16550: Support CONFIG_SYS_NS16550_MEM32 with driver model This option is used by some boards, so support it with driver model. This is really ugly - we should rewrite this driver once all users are moved to driver model. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4f60166c |
|
24-Apr-2015 |
Axel Lin <axel.lin@ingics.com> |
serial: ns16550: Remove hard-coded baud_divisor setting This was accidentally added by commit dd0b0122bacc "serial: ns16550: Add an option to specify the debug UART register shift". Remove it. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
ab9fd2e8 |
|
27-Feb-2015 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Remove unnecessary init on UART setup It is not necessary to write a zero baud rate to the device, and for some chips this will cause problems. Drop this code. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
363e6da1 |
|
27-Feb-2015 |
Simon Glass <sjg@chromium.org> |
dm: ns16550: Support non-byte register spacing with driver model Allow this driver to support boards where the register shift is not 0. This fixes some compiler warnings which appear in that case. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
dd0b0122 |
|
27-Feb-2015 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Add an option to specify the debug UART register shift This UART permits different register spacing. To support the debug UART on devices which have a spacing other than 1 byte, allow the shift value to be specified. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
0eb25b61 |
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22-Mar-2015 |
Joe Hershberger <joe.hershberger@ni.com> |
common: Make sure arch-specific map_sysmem() is defined In the case where the arch defines a custom map_sysmem(), make sure that including just mapmem.h is sufficient to have these functions as they are when the arch does not override it. Also split the non-arch specific functions out of common.h Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
20379c11 |
|
28-Feb-2015 |
Axel Lin <axel.lin@ingics.com> |
serial: ns16550: Fix build error due to a typo Fix trivial typo. Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Axel Lin <axel.lin@ingics.com> |
#
21d00436 |
|
26-Jan-2015 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support debug UART Add debug UART functions to permit ns16550 to provide an early debug UART. Try to avoid using the stack so that this can be called from assembler before a stack is set up (at least on ARM and PowerPC). Signed-off-by: Simon Glass <sjg@chromium.org> |
#
76571674 |
|
26-Jan-2015 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Add access functions that don't need platdata For the debug UART we need to be able to provide any parameters before driver model is set up. Add parameters to the low-level access functions to make this possible. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
3db886a5 |
|
31-Dec-2014 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Support ns16550 compatible pci uart devices There are many pci uart devices which are ns16550 compatible. We can describe them in the board dts file and use it as the U-Boot serial console as specified in the chosen node 'stdout-path' property. Those pci uart devices can have their register be memory-mapped, or i/o-mapped. The driver will try to use the memory-mapped register if the reg property in the node has an entry to describe the memory-mapped register, otherwise i/o-mapped register will be used. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
956a8bae |
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10-Nov-2014 |
Gregoire Gentil <gregoire@gentil.com> |
ns16550.c: Fix for ns16550 driver hanging on OMAP4 The same problem that is seen on some OMAP3 is also seen on some OMAP4 so include them in the test in order to prevent some hangs during SPL. [trini: Re-word commit message, make apply cleanly] Signed-off-by: Tom Rini <trini@ti.com> |
#
1f77690e |
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10-Oct-2014 |
Simon Glass <sjg@chromium.org> |
dm: serial: ns16550: Add a cast to the I/O operations This generates a warning when driver model is enabled, so fix it by adding a cast. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
11c1a878 |
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22-Oct-2014 |
Simon Glass <sjg@chromium.org> |
dm: ns16550: Correct the probe logic for platform data The probe logic sets up the pointer to the platform data in the device tree decode method. It should be done in the probe() method, and anyway the device tree decode method can't be used when CONFIG_OF_CONTROL is not enabled. Fix these two problems. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@ti.com> |
#
167efe01 |
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22-Oct-2014 |
Simon Glass <sjg@chromium.org> |
dm: ns16550: Use an address instead of a pointer for the uart base It is inconvenient to have to use casts when specifying platform data. Also it is not strictly correct, since we should use map_sysmem() to convert an address to a pointer. Adjust the platform data to use an address. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@ti.com> |
#
aea2be20 |
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22-Oct-2014 |
Simon Glass <sjg@chromium.org> |
dm: serial: ns16550: Correct logic for checking for character There is a bug in the logic which checks for an available character. This can cause invalid characters to be received - this was noticed on beaglebone. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@ti.com> |
#
12e431b2 |
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04-Sep-2014 |
Simon Glass <sjg@chromium.org> |
dm: serial: Add driver model support for ns16550 Add driver model support so that ns16550 can support operation both with and without driver model. The driver needs a clock frequency so cannot stand alone unfortunately. The clock frequency must be provided by a separate driver. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8bbe33c8 |
|
04-Sep-2014 |
Simon Glass <sjg@chromium.org> |
dm: serial: Collect common baud rate code in ns16550 The same sequence is used in several places, so move it into a function. Note that UART_LCR_BKSE is an alias for UART_LCR_DLAB. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
fa54eb12 |
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04-Sep-2014 |
Simon Glass <sjg@chromium.org> |
dm: serial: Move baud rate calculation to ns16550.c Move the function that calculates the baud rate divisor into ns16550.c so it can be used by that file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8ac22a60 |
|
30-Jul-2014 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
omap: clean-up dead configs The following configs are not defined at all. - CONFIG_OMAP1510 - CONFIG_OMAP_1510P1 - CONFIG_OMAP_SX1 - CONFIG_OMAP3_DMA - CONFIG_OMAP3_ZOOM2 - CONFIG_OMAP_INNOVATOR Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Tom Rini <trini@ti.com> |
#
7c387646 |
|
15-Jul-2014 |
Khoronzhuk, Ivan <ivan.khoronzhuk@ti.com> |
keystone2: use CONFIG_SOC_KEYSTONE in common places Use CONFIG_SOC_KEYSTONE in common places instead of defining a lot of "if def .. || if def " for different Keystone2 SoC types. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> |
#
d57dee57 |
|
09-Apr-2014 |
Karicheri, Muralidharan <m-karicheri2@ti.com> |
serial: nsl16550: add hw flow control support keystone serial hw support hw flow control. This patch enables hw flow control for keystone EVMs as an optional feature based on CONFIG_SERIAL_HW_FLOW_CONTROL. Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> |
#
ef509b90 |
|
04-Apr-2014 |
Vitaly Andrianov <vitalya@ti.com> |
k2hk: add support for k2hk SOC and EVM k2hk EVM is based on Texas Instruments Keystone2 Hawking/Kepler SoC. Keystone2 SoC has ARM v7 Cortex-A15 MPCore processor. Please refer the ti/k2hk_evm/README for details on the board, build and other information. This patch add support for keystone architecture and k2hk evm. Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: WingMan Kwok <w-kwok2@ti.com> Signed-off-by: Sandeep Nair <sandeep_n@ti.com> |
#
456ccfdf |
|
20-Dec-2013 |
Tom Rini <trini@konsulko.com> |
TI:omap3: Drop omap3_zoom2 The omap3_zoom2 board has not been updated for a correct CONFIG_SYS_HZ and Tom Rix's email has long been bouncing. Signed-off-by: Tom Rini <trini@ti.com> |
#
9ed6e412 |
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01-Jul-2013 |
TENART Antoine <atenart@adeneo-embedded.com> |
Prepare for TI816X : reuse existing code from TI814X Rename some CONFIG_TI814X to a more generic CONFIG_TI81XX Signed-off-by: Antoine Tenart <atenart@adeneo-embedded.com> [trini: Adapt for CONFIG_OMAP_COMMON changes, AM43XX] Signed-off-by: Tom Rini <trini@ti.com> |
#
57180408 |
|
30-Jul-2013 |
Lokesh Vutla <lokeshvutla@ti.com> |
ARM: AM43xx: Add build support Add AM43xx support in the required places Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> |
#
7f5eef93 |
|
03-Jun-2013 |
Tom Rini <trini@konsulko.com> |
arm: Remove OMAP2420H4 and all omap24xx support The omap2420H4 was the only mainline omap24xx board. Prior to being fixed by Jon Hunter in time for v2013.04 it had been functionally broken for a very long time. Remove this board as there's not been interest in it in U-Boot for quite a long time. Signed-off-by: Tom Rini <trini@ti.com> |
#
fd2aeac5 |
|
28-Mar-2013 |
Manfred Huber <man.huber@arcor.de> |
omap3_beagle: Flush UART3 xmit on enable if TEMT is broken Flush UART3 xmit on enable if TEMT is broken On some OMAP3 devices when UART3 is configured for boot mode before SPL starts only THRE bit is set. We have to empty the transmitter before initialization starts. This patch avoids the use of CONFIG_SYS_NS16550_BROKEN_TEMT. Signed-off-by: Manfred Huber <man.huber@arcor.de> Tested-by: Javier Martinez Canillas <javier@dowhile0.org> Tested-by: Andreas Bießmann <andreas.devel@googlemail.com> |
#
6213a68f |
|
15-Mar-2013 |
Matt Porter <mporter@ti.com> |
ns16550: enable quirks for ti814x TI814X requires the same quirks as AM33XX to be enabled. Signed-off-by: Matt Porter <mporter@ti.com> Reviewed-by: Tom Rini <trini@ti.com> |
#
69e06832 |
|
05-Mar-2013 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Remove unwanted cast This cast does not seem correct, since we should be writing to a pointer, not a ulong. This fixes the following warning on nds32: -ns16550.c:49: warning: passing argument 2 of 'writeb' makes pointer from integer without a cast Signed-off-by: Simon Glass <sjg@chromium.org> |
#
7de0fe1a |
|
06-Jan-2013 |
Javier Martinez Canillas <javier@dowhile0.org> |
serial/ns16550: add an option to avoid hanging on broken platforms Some platforms (e.g. IGEPv2 board) has a broken ns16550 UART that does not set the TEMT bit when the transmitter is empty in SPL. This makes U-Boot to hang while waiting for TEMT to be set. Add a new option to avoid this: CONFIG_SYS_NS16550_BROKEN_TEMT 16550 UART set the Transmitter Empty (TEMT) Bit when all output has finished and the transmitter is totally empty. U-Boot waits for this bit to be set to initialize the serial console. On some broken platforms this bit is not set in SPL making U-Boot to hang while waiting for TEMT. Define this option to avoid it. Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> |
#
cb55b332 |
|
18-Sep-2012 |
Scott Wood <scottwood@freescale.com> |
serial/ns16550: wait for TEMT before initializing TEMT is set when the transmitter is totally empty and all output has finished. This prevents output problems (including a loss of synchronization observed on p2020 that persisted for quite a while) if SPL has output still on its way out. Signed-off-by: Scott Wood <scottwood@freescale.com> -- v2: fixed typo in subject, and explained what the bit does in the changelog |
#
f2041388 |
|
15-Sep-2012 |
Marek Vasut <marex@denx.de> |
serial: ns16550: Call usbtty_poll only in non-SPL build Having both USBTTY and CONFIG_SERIAL_MULTI enabled in SPL, the usbtty.c file is protected in Makefile to not be compiled into the SPL. Yet, the ns16550 serial driver does not contain such protection. Add it to avoid missing symbol error. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Marek Vasut <marek.vasut@gmail.com> Cc: Tom Rini <trini@ti.com> |
#
99b603e7 |
|
09-Jul-2012 |
Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com> |
serial/ns16550: ns16550 has a different register layout on SOC_DA8XX also fix NS16550_init() as we need 16x divider Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com> Acked-by: Christian Riesch <christian.riesch@omicron.at> Tested-by: Christian Riesch <christian.riesch@omicron.at> Acked-by: Sughosh Ganu <urwithsughosh@gmail.com> Tested-by: Sughosh Ganu <urwithsughosh@gmail.com> |
#
5289e83a |
|
13-Oct-2011 |
Chandan Nath <chandan.nath@ti.com> |
ARM:AM33XX: Add support for TI AM335X EVM This patch adds basic support for booting the board. This patch adds support for the UART necessary to get to the u-boot prompt. Signed-off-by: Chandan Nath <chandan.nath@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> |
#
f8df9d0d |
|
15-Oct-2011 |
Simon Glass <sjg@chromium.org> |
NS16550: trivial code clean for checkpatch This removes most checkpatch warnings from the ns16550 driver and its header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
79df1208 |
|
01-Sep-2011 |
Dave Aldridge <fovsoft@gmail.com> |
ns16550: change to allow 32 bit access to registers If CONFIG_SYS_NS16550_MEM32 is defined then 32 bit memory mapped access will be used to read/write the uart registers. This is especially useful for SoC devices that implement 16550 compatible uarts but that have peripheral access width constraints. Signed-off-by: Dave Aldridge <fovsoft@gmail.com> |
#
a160ea0b |
|
27-Oct-2010 |
Prafulla Wadaskar <prafulla@marvell.com> |
Serial: ns16550: Add support for CONFIG_SYS_NS16550_IER macro On some processors this ier register configuration is different for ex. Marvell Armada100 This patch introduce CONFIG_SYS_NS16550_IER macro support to unconditionally initialize this register. Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com> |
#
1a2d9b30 |
|
12-Oct-2010 |
Stefan Roese <sr@denx.de> |
ns16550: Add WATCHDOG_RESET to putc for short watchdog timeout boards Call watchdog_reset() upon newline. This is done here in putc since the environment code uses a single puts() to print the complete envrironment upon "printenv". So we can't put this watchdog call in puts(). This is needed for boards with a very short watchdog timeout, like the lwmon5 with a 100ms timeout. Without this patch this board resets in the commands with long outputs, like "printenv" or "fdt print". Note that the image size is not increased with this patch when CONFIG_HW_WATCHDOG or CONFIG_WATCHDOG are not defined since the compiler optimizes this additional code away. Signed-off-by: Stefan Roese <sr@denx.de> Fix typo in comment. Signed-off-by: Wolfgang Denk <wd@denx.de> |
#
167cdad1 |
|
23-Apr-2010 |
Graeme Russ <graeme.russ@gmail.com> |
SERIAL: Enable port-mapped access The x86 architecture exclusively uses Port-Mapped I/O (inb/outb) to access the 16550 UARTs. This patch mimics how Linux selects between Memory-Mapped and Port-Mapped I/O. This allows x86 boards to use CONFIG_SERIAL_MUTLI and drop the custom serial port driver Signed-off-by: Graeme Russ <graeme.russ@gmail.com> |
#
a47a12be |
|
15-Apr-2010 |
Stefan Roese <sr@denx.de> |
Move arch/ppc to arch/powerpc As discussed on the list, move "arch/ppc" to "arch/powerpc" to better match the Linux directory structure. Please note that this patch also changes the "ppc" target in MAKEALL to "powerpc" to match this new infrastructure. But "ppc" is kept as an alias for now, to not break compatibility with scripts using this name. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Wolfgang Denk <wd@denx.de> Acked-by: Detlev Zundel <dzu@denx.de> Acked-by: Kim Phillips <kim.phillips@freescale.com> Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Anatolij Gustschin <agust@denx.de> |
#
a1b322a9 |
|
01-Feb-2010 |
Ladislav Michl <ladis@linux-mips.org> |
ns16550: kick watchdog while waiting for a character ns16550 busyloops waiting for incoming byte causing watchdog to reboot while waiting for a key press. A call to WATCHDOG_RESET in NS16550_getc loop fixes it. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> |
#
660888b7 |
|
30-May-2009 |
Tom Rix <Tom.Rix@windriver.com> |
ZOOM2 Add serial support. Zoom2 serial is in general supplied by one of the 4 UARTS on the debug board. The default serial is from the USB connector on left side of the debug board. The USB connector will produce 2 of the 4 UARTS. On your host pick the first enumeration. The details of the setting of the serial gpmc setup are not available. The values were provided by another party. The serial port set up is the same with Zoom1. Baud rate 115200, 8 bit data, no parity, 1 stop bit, no flow. The kernel bootargs are console=ttyS3,115200n8 Signed-off-by: Tom Rix <Tom.Rix@windriver.com> |
#
200779e3 |
|
03-Apr-2009 |
Detlev Zundel <dzu@denx.de> |
Rename common ns16550 constants with UART_ prefix to prevent conflicts Fix problems introduced in commit 7b5611cdd12ca0cc33f994f0d4a4454788fc3124 [inka4x0: Add hardware diagnosis functions for inka4x0] which redefined MSR_RI which is already used on PowerPC systems. Also eliminate redundant definitions in ps2mult.h. More cleanup will be needed for other redundant occurrences though. Signed-off-by: Detlev Zundel <dzu@denx.de> |
#
b4746d8b |
|
11-Feb-2009 |
Mike Frysinger <vapier@gentoo.org> |
drivers/serial/ns16550: move ifdef into Makefile COBJS-$(...) Signed-off-by: Mike Frysinger <vapier@gentoo.org> |
#
f5675aa5 |
|
18-Feb-2009 |
Ron Madrid <ron_madrid@sbcglobal.net> |
Create configuration option for restricted ns16550 functions This patch will create a configuration option for a minimum configuration for the ns16550 serial driver at drivers/serial/ns16550.c and will apply this new configuration option to the SIMPC8313.h config file in order to fix the NAND bootstrap build error. This option will exclude all functions with exception of NS16550_putc and NS16550_init. This will be used primarily to save space and remove unused code from builds in which space is limited. Signed-off-by: Ron Madrid <ron_madrid@sbcglobal.net> |
#
6d0f6bcf |
|
16-Oct-2008 |
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
rename CFG_ macros to CONFIG_SYS Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
#
7ec8bb15 |
|
27-Dec-2007 |
Wolfgang Denk <wd@denx.de> |
OMAP5912: fix FIFO handling in UART driver According to the OMAP5912 Serial Interfaces Reference Guide (see http://focus.ti.com/lit/ug/spru760c/spru760c.pdf, page 150), the FIFO_EN enable bit in the FIFO Control Register (FCR) can only be changed when the baud clock is not running, i. e. when both DLL and DLH are set to 0. Thus make sure that DLL and DLH are 0 when writing the FCR. Signed-off-by: Wolfgang Denk <wd@denx.de> |
#
1378df79 |
|
24-Nov-2007 |
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
drivers/serial : move serial drivers to drivers/serial Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
#
91092132 |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_NS16550_* to CFG_SYS_NS16550_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NS16550 namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
57c3afbc |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
powerpc: Rename CONFIG_NS16550_MIN_FUNCTIONS This symbol is specific to the PowerPC SPL implementation, so rename this to reflect that it's in SPL and used / tested there, so that we can then safely migrate it to Kconfig. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
29caf930 |
|
02-Sep-2022 |
Stefan Roese <sr@denx.de> |
cyclic: Use schedule() instead of WATCHDOG_RESET() Globally replace all occurances of WATCHDOG_RESET() with schedule(), which handles the HW_WATCHDOG functionality and the cyclic infrastructure. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Tom Rini <trini@konsulko.com> [am335x_evm, mx6cuboxi, rpi_3,dra7xx_evm, pine64_plus, am65x_evm, j721e_evm] |
#
5e998b4d |
|
23-Jun-2022 |
Pali Rohár <pali@kernel.org> |
serial: ns16550: Wait in debug_uart_init until tx buffer is empty Commit d293759d55cc ("serial: ns16550: Add support for SPL_DEBUG_UART_BASE") fixed support for setting correct early debug UART base address in SPL. But after this commit, output from Marvell A385 BootROM is truncated or lost and not fully present on serial console. Debugging this issue showed that BootROM just put bytes into UART HW output buffer and does not wait until UART HW transmit all characters. U-Boot ns16550 early debug is initialized very early and during its initialization is resetting UART HW and flushing remaining transmit buffer (which still contains BootROM output). Fix this issue by waiting in init function prior resetting UART HW until TxEmpty bit in UART Line Status Register is set. TxEmpty is set when all remaining bytes from HW buffer are transmitted. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> [trini: Add comment, move ';' to new line per checkpatch.pl] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
d293759d |
|
06-May-2022 |
Pali Rohár <pali@kernel.org> |
serial: ns16550: Add support for SPL_DEBUG_UART_BASE Use CONFIG_VAL(DEBUG_UART_BASE) instead of CONFIG_DEBUG_UART_BASE, so proper config value (CONFIG_DEBUG_UART_BASE or CONFIG_SPL_DEBUG_UART_BASE) is used based on building target. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
04ee76c9 |
|
09-Apr-2022 |
Johan Jonker <jbx6244@gmail.com> |
rockchip: serial: move driver alias to serial_rockchip.c The Rockchip uart DT nodes have "snps,dw-apb-uart" as fall back string. The driver ns16550.c has CONFIG_IS_ENABLED(OF_REAL) as condition to of_match and does not copy dtplat data. For TPL/SPL the driver serial_rockchip.c is used. Move driver alias to correct driver. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
f899cc14 |
|
12-Sep-2021 |
Tom Rini <trini@konsulko.com> |
ti: keystone: Move away from CONFIG_SOC_KEYSTONE We have individual SOC symbols for each keystone 2 platform. Use the existing CONFIG_ARCH_KEYSTONE rather than CONFIG_SOC_KEYSTONE to encompass all of the keystone families. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
414cc151 |
|
07-Aug-2021 |
Simon Glass <sjg@chromium.org> |
treewide: Simply conditions with the new OF_REAL Use this new Kconfig to simplify the compilation conditions where appropriate. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
384b62c0 |
|
03-Feb-2021 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Handle zero <clock-frequency> value A working device tree node of ns16550 should never be populated with value zero for the <clock-frequency> property. Unfortunately this is the case for the QEMU ppce500 target. Let's try to assign plat->clock to CONFIG_SYS_NS16550_CLK as the last resort to handle such case. This commit should be reverted when: - The following QEMU patch [1] is merged, and - U-Boot CI has upgraded its QEMU version that contains the fix [1] http://patchwork.ozlabs.org/project/qemu-devel/patch/1612362288-22216-2-git-send-email-bmeng.cn@gmail.com/ Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
09bd0840 |
|
03-Feb-2021 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Correct the base address type Currently ns16550_serial_assign_base() treats the argument 'base' with type `ulong`. This is incorrect because the base address was obtained from device tree with type `fdt_addr_t` that can represent a physical address larger than 32-bit in a 32-bit system. Fixes: 9e6ce62190b7 ("serial: ns16550: Fix ordering of getting base address") Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
401d1c4f |
|
30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
bdf8fd76 |
|
28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
0fd3d911 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com> |
#
2d6bf754 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
#
d30c7209 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
41575d8e |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo |
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de> |
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> |
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se> |
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> |
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com |
#
9ad3b049 |
|
02-Nov-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: add setconfig support Add possibility to update the serial parity used. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com> |
#
46879196 |
|
24-Oct-2018 |
Bin Meng <bmeng.cn@gmail.com> |
serial: Remove DM_FLAG_PRE_RELOC flag in various drivers When a driver declares DM_FLAG_PRE_RELOC flag, it wishes to be bound before relocation. However due to a bug in the DM core, the flag only takes effect when devices are statically declared via U_BOOT_DEVICE(). This bug has been fixed recently by commit "dm: core: Respect drivers with the DM_FLAG_PRE_RELOC flag in lists_bind_fdt()", but with the fix, it has a side effect that all existing drivers that declared DM_FLAG_PRE_RELOC flag will be bound before relocation now. This may expose potential boot failure on some boards due to insufficient memory during the pre-relocation stage. To mitigate this potential impact, the following changes are implemented: - Remove DM_FLAG_PRE_RELOC flag in the driver, if the driver only supports configuration from device tree (OF_CONTROL) - Keep DM_FLAG_PRE_RELOC flag in the driver only if the device is statically declared via U_BOOT_DEVICE() - Surround DM_FLAG_PRE_RELOC flag with OF_CONTROL check, for drivers that support both statically declared devices and configuration from device tree Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
6f57c344 |
|
09-Aug-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), let's rather ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
5d754197 |
|
27-Aug-2018 |
Lokesh Vutla <lokeshvutla@ti.com> |
serial: omap: Introduce DM specific omap serial Add driver model support for OMAP_SERIAL while reusing the functions in ns16550.c Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Tested-by: Derald D. Woods <woods.technical@gmail.com> |
#
b051eecb |
|
14-Jun-2018 |
Ley Foon Tan <ley.foon.tan@intel.com> |
serial: ns16550: Add reset ctrl to driver Add code to reset all reset signals as in serial DT node. A reset property is an optional feature, so do not fail if a reset property is not present. If a reset property is discovered, then use it to deassert, thus bringing the IP out of reset. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
78b7d37b |
|
15-Feb-2018 |
Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> |
ns16550: Fix mem mapped endian check Do a explicit check for CONFIG_SYS_BIG_ENDIAN and CONFIG_SYS_LITTLE_ENDIAN to avoid errors on platforms where both are undefined (x86). Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> Reviewed-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com> |
#
4dbf9bed |
|
15-Jan-2018 |
Mario Six <mario.six@gdsys.cc> |
serial: ns16550: Fix style violation Clarify the computation precedence in two ternary operator constructions. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc> |
#
7fded0ce |
|
16-Aug-2017 |
Stefan Roese <sr@denx.de> |
Revert "serial: ns16550: Add RX interrupt buffer support" This reverts commit 6822cf3ec7c8768b8727573b8f4b2cb3d870b881. As Bin Meng has tested and pointed out, we don't need the RX interrupt for the RX buffer support at all. Just reading all available characters into a buffer is sufficient to solve the problem with the dropped characters upon long lines pasted into the U-Boot prompt. Since this RX buffer support can be implemented in a generic way, without any device specifica (e.g. for the ns16550), I'll post a new patch with a new serial RX buffer support for DM, which all DM based serial drivers can use. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
6822cf3e |
|
14-Jul-2017 |
Stefan Roese <sr@denx.de> |
serial: ns16550: Add RX interrupt buffer support Pasting longer lines into the U-Boot console prompt sometimes leads to characters missing. One problem here is the small 16-byte FIFO of the legacy NS16550 UART, e.g. on x86 platforms. This patch now introduces a Kconfig option to enable RX interrupt buffer support for NS16550 style UARTs. With this option enabled, I was able paste really long lines into the U-Boot console, without any characters missing. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> [trini: Guard ns16550_serial_remove with CONFIG_IS_ENABLED(SERIAL_PRESENT) to match struct assignment] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
8d3a2568 |
|
11-Jul-2017 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-dm
|
#
db9f8f6a |
|
12-Jun-2017 |
Simon Glass <sjg@chromium.org> |
dm: serial: ns16550: Convert to livetree Update this driver to support a live device tree. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Tested-on: Beaver, Jetson-TK1 |
#
3d40479f |
|
07-Jun-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
rockchip: ns16550: dm: convert fdt_get to dev_read With the new dev_read functions available, we can convert the rockchip architecture-specific drivers and common drivers used by these devices over to the dev_read family of calls. This covers the serial driver (ns16550 and compatible) used for the Rockchip devices. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
a821c4af |
|
17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: Rename dev_addr..() functions These support the flat device tree. We want to use the dev_read_..() prefix for functions that support both flat tree and live tree. So rename the existing functions to avoid confusion. In the end we will have: 1. dev_read_addr...() - works on devices, supports flat/live tree 2. devfdt_get_addr...() - current functions, flat tree only 3. of_get_address() etc. - new functions, live tree only All drivers will be written to use 1. That function will in turn call either 2 or 3 depending on whether the flat or live tree is in use. Note this involves changing some dead code - the imx_lpi2c.c file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
89024ddc |
|
12-May-2017 |
Tom Rini <trini@konsulko.com> |
TI: Drop 'CONFIG_OMAP' In the two cases in the code where we use CONFIG_OMAP as a useful test currently we can make use of CONFIG_ARCH_OMAP2PLUS instead. With that changed we can drop all defines of CONFIG_OMAP. While in here, CONFIG_OMAP3430 is only defined and then never used, so drop. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
a52cf086 |
|
22-Apr-2017 |
Lokesh Vutla <lokeshvutla@ti.com> |
serial: omap: Support debug UART Add debug UART functions to permit omap specific ns16550 to provide an early debug UART. This is mostly in common with DEBUG_UART_NS16550 except for Mode definition register which is required for selecting UART mode(16x auto-baud or 13x mode). Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
6f8c351e |
|
27-Mar-2017 |
Alexandru Gagniuc <alex.g@adaptrum.com> |
serial: ns16550: Link in the DM driver when when using platdata Do not condition the compilation of the U_BOOT_DRIVER by !OF_PLATDATA. This is inconsistent with the majority of other drivers. This also blocks OF_PLATDATA boards with an 16550-compatible serial from using serial in SPL. Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com> Reviewed-by: Simon Glass <sjg@chromium.org> Added tweak for rock to avoid a TPL build failure: Signed-off-by: Simon Glass <sjg@chromium.org> |
#
e160f7d4 |
|
17-Jan-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
17fa0326 |
|
18-Jan-2017 |
Heiko Schocher <hs@denx.de> |
serial, ns16550: bugfix: ns16550 fifo not enabled commit: 65f83802b7a5b "serial: 16550: Add getfcr accessor" breaks u-boot commandline working with long commands sending to the board. Since the above patch, you have to setup the fcr register. For board/archs which enable OF_PLATDATA, the new field fcr in struct ns16550_platdata is not filled with a default value ... This leads in not setting up the uarts fifo, which ends in problems, when you send long commands to u-boots commandline. Detected this issue with automated tbot tests on am335x based shc board. The error does not popup, if you type commands. You need to copy&paste a long command to u-boots commandshell (or send a long command with tbot) Possible boards/plattforms with problems: ./arch/arm/cpu/arm926ejs/lpc32xx/devices.c ./arch/arm/mach-tegra/board.c ./board/overo/overo.c ./board/quipos/cairo/cairo.c ./board/logicpd/omap3som/omap3logic.c ./board/logicpd/zoom1/zoom1.c ./board/timll/devkit8000/devkit8000.c ./board/lg/sniper/sniper.c ./board/ti/beagle/beagle.c ./drivers/serial/serial_rockchip.c Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Tested-by: Adam Ford <aford173@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
0b060eef |
|
30-Nov-2016 |
Marek Vasut <marex@denx.de> |
serial: 16550: Add Ingenic JZ4780 support Add compatibility string for the Ingenic JZ4780 SoC, the necessary UART enable bit into FCR and register shift. Neither are encoded in the DTS coming from Linux, so we need to support it this way. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
79fd9281 |
|
30-Nov-2016 |
Marek Vasut <marex@denx.de> |
serial: 16550: Add port type as driver data Add driver data to each compatible string to identify the type of the port. Since all the ports in the driver are entirely compatible with 16550 for now, all are marked with PORT_NS16550. But, there are ports which have specific quirks, like the JZ4780 UART, which do not have any DT property to denote the quirks. Instead, Linux uses the compatible string to discern such ports and enable the necessary quirks. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> |
#
65f83802 |
|
30-Nov-2016 |
Marek Vasut <marex@denx.de> |
serial: 16550: Add getfcr accessor Add function which allows fetching the default FCR register setting from platform data for DM , while retaining old behavior for non-DM by returning UART_FCRVAL. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
021abf69 |
|
26-Sep-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
Revert "ns16650: Make sure we have CONFIG_CLK set before using infrastructure" This reverts commit 82f5279b0cd99a9163d34cfe926d0316d9dc0d37. The build failure of k2*evm boards was fixed in a different way by the previous commit. It is nasty to patch generic drivers around with #ifdef CONFIG_CLK just for the KeyStone's matter. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
ab895d6a |
|
30-Sep-2016 |
Alexandre Courbot <acourbot@nvidia.com> |
serial: ns16550: Handle -ENOENT when requesting clock When calling clk_get_by_index(), fall back to the legacy method of getting the clock if -ENOENT is returned. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> |
#
82f5279b |
|
22-Sep-2016 |
Tom Rini <trini@konsulko.com> |
ns16650: Make sure we have CONFIG_CLK set before using infrastructure We cannot call on the CONFIG_CLK based clk_get_rate function unless CONFIG_CLK is set. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
50fce1d5 |
|
08-Sep-2016 |
Paul Burton <paul.burton@mips.com> |
serial: ns16550: Support clocks via phandle Previously ns16550 compatible UARTs probed via device tree have needed their device tree nodes to contain a clock-frequency property. An alternative to this commonly used with Linux is to reference a clock via a phandle. This patch allows U-Boot to support that, retrieving the clock frequency by probing the appropriate clock device. For example, a system might choose to provide the UART base clock as a reference to a clock common to multiple devices: sys_clk: clock { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <10000000>; }; uart0: uart@10000000 { compatible = "ns16550a"; reg = <0x10000000 0x1000>; clocks = <&sys_clk>; }; uart1: uart@10000000 { compatible = "ns16550a"; reg = <0x10001000 0x1000>; clocks = <&sys_clk>; }; This removes the need for the frequency information to be duplicated in multiple nodes and allows the device tree to be more descriptive of the system. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
b2927fba |
|
04-Jul-2016 |
Simon Glass <sjg@chromium.org> |
dm: serial: ns16550: Update to support of-platdata With of-platdata this driver cannot know the format of the of-platdata struct, so we cannot use generic code for accessing the of-platdata. Each SoC that uses this driver will need to set up ns16550's platdata for it. So don't compile in the generic code. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
03c6f176 |
|
24-May-2016 |
Marek Vasut <marex@denx.de> |
serial: 16550: Drop OMAP1510 support The CONFIG_OMAP1510 is no longer defined, so remove this dead code. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Nishanth Menon <nm@ti.com> |
#
fa4ce723 |
|
24-May-2016 |
Marek Vasut <marex@denx.de> |
serial: 16550: Make serial_io/out_shift available to debug mode The ns16550 driver needs serial_in_shift() and serial_out_shift() when compiled in debug UART mode, so shift the DM_SERIAL check a little to make these functions available. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
df8ec55d |
|
17-May-2016 |
Paul Burton <paul.burton@mips.com> |
dm: ns16550: Don't map_physmem for I/O ports If the UART is to be accessed using I/O port accessors (inb & outb) then using map_physmem doesn't make sense, since it operates in a different memory space. Remove the call to map_physmem when CONFIG_SYS_NS16550_PORT_MAPPED is defined, allowing I/O port addresses to not be mangled by the incorrect mapping. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> |
#
59b35ddd |
|
16-Feb-2016 |
Michal Simek <michal.simek@amd.com> |
dm: ns16550: Add support for reg-offset property reg-offset is the part of standard 8250 binding in the kernel. It is shifting start of address space by reg-offset. On Xilinx platform this offset is typically 0x1000. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Moved the new field to the end of the struct to avoid problems: Signed-off-by: Simon Glass <sjg@chromium.org> |
#
e5e88c65 |
|
29-Feb-2016 |
Tom Rini <trini@konsulko.com> |
Revert "dm: ns16550: Add support for reg-offset property" This reverts commit d9a3bec682f9756621615f4306718a356a3230e3. While this is a correct change to do long term it unfortunately breaks a number of platforms that are using pdata and not named struct members so they are getting all of their data after 'base' incorrect. Acked-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
d9a3bec6 |
|
16-Feb-2016 |
Michal Simek <michal.simek@amd.com> |
dm: ns16550: Add support for reg-offset property reg-offset is the part of standard 8250 binding in the kernel. It is shifting start of address space by reg-offset. On Xilinx platform this offset is typically 0x1000. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
cc4228f9 |
|
14-Dec-2015 |
Thomas Chou <thomas@wytron.com.tw> |
ns16550: zap the rockchip serial compatible string Zap the rockchip serial compatible string, because rockchip serial has "snps,dw-apb-uart" compatible string in the dts. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org> |
#
b7e29834 |
|
13-Dec-2015 |
Simon Glass <sjg@chromium.org> |
dm: ns16550: Allow the driver to be omitted if requested Allow the ns16550 debug UART to be used without the full driver. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Thomas Chou <thomas@wytron.com.tw> |
#
fcc0a877 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: serial: Convert ns16550 driver to use driver model PCI API Use the driver model version of the function to find the BAR. This updates the fdtdec function, of which ns16550 is the only user. The fdtdec_get_pci_bdf() function is dropped for several reasons: - with driver model we should use 'struct udevice *' rather than passing the device tree offset explicitly - there are no other users in the tree - the function parses for information which is already available in the PCI device structure (specifically struct pci_child_platdata which is available at dev_get_parent_platdata(dev) Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> |
#
b7e5a643 |
|
04-Dec-2015 |
Simon Glass <sjg@chromium.org> |
dm: serial: ns16550: Add pre-reloc flag to the driver For platforms that don't use device tree in SPL the only way to mark this driver as 'required by relocation' is with the DM_FLAG_PRE_RELOC flag. Add this to ensure that the driver is bound. Fixes: fde7e18938d8 ("dm: tegra: pci: Move CONFIG_PCI_TEGRA to Kconfig") Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Stephen Warren <swarren@nvidia.com> Acked-by: Thomas Chou <thomas@wytron.com.tw> |
#
80e06146 |
|
28-Nov-2015 |
Thomas Chou <thomas@wytron.com.tw> |
ns16550: change reg-shift property default to zero Change reg-shift property default to zero. When the integer property is missing, it should be taken as zero. This is consistent to Linux drivers/tty/serial/of_serial.c. The x86 and most powerpc use reg-shift of 0. Most others use reg-shift of 2. While reg-shift of 1 is rarely used. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
a51dbebf |
|
16-Nov-2015 |
huang lin <hl@rock-chips.com> |
rockchip: serial driver support rk3036 Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
4fb60552 |
|
19-Nov-2015 |
Thomas Chou <thomas@wytron.com.tw> |
ns16550: zap CONFIG_NS16550_SERIAL Zap CONFIG_NS16550_SERIAL, as the unification of ns16550 drivers is completed. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
8e62d32e |
|
19-Nov-2015 |
Thomas Chou <thomas@wytron.com.tw> |
ns16550: add generic binding to unify the drivers Add generic binding to unify ns16550 drivers. There are several drivers using almost the same code, such as serial_dw, serial_keystone, serial_omap, serial_ppc, serial_rockchip, serial_tegra.c, and serial_x86. But each is platform specific. The key difference between these drivers is the way to get input clock frequency. With this unified approach, fixed clock frequency should be extracted from "clock-frequency" property of device tree blob. If this property is not available, the macro CONFIG_SYS_NS16550_CLK will be used. It can be a constant or a function to get clock, eg, get_serial_clock(). Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de> Acked-by: Simon Glass <sjg@chromium.org> |
#
77d7b5cd |
|
19-Nov-2015 |
Thomas Chou <thomas@wytron.com.tw> |
ns16550: change map_sysmem to map_physmem Change map_sysmem() to map_physmem(,,MAP_NOCACHE). Though map_sysmem() can be used to map system memory, it might be wrong to use it for I/O ports. The map_physmem() serves the same purpose to translate physical address to virtual address with the additional flag to take care of cache property. Most drivers use map_physmem() since I/O ports access should be uncached. As ns16550 is a driver, it should use map_physmem() rather than map_sysmem(). Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org> |
#
97b05973 |
|
18-Oct-2015 |
Simon Glass <sjg@chromium.org> |
debug_uart: Adjust the declaration of debug_uart_init() We want to be able to add other common code to this function. So change the driver's version to have an underscore before it, just like _debug_uart_putc(). Define debug_uart_init() to call this version. Update all drivers to this new method. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
4e9838c1 |
|
11-Aug-2015 |
Simon Glass <sjg@chromium.org> |
dm: Use dev_get_addr() where possible This is a convenient way for a driver to get the hardware address of a device, when regmap or syscon are not being used. Change existing callers to use it as an example to others. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> |
#
0f925822 |
|
11-Aug-2015 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
of: clean up OF_CONTROL ifdef conditionals We have flipped CONFIG_SPL_DISABLE_OF_CONTROL. We have cleansing devices, $(SPL_) and CONFIG_IS_ENABLED(), so we are ready to clear away the ugly logic in include/fdtdec.h: #ifdef CONFIG_OF_CONTROL # if defined(CONFIG_SPL_BUILD) && !defined(SPL_OF_CONTROL) # define OF_CONTROL 0 # else # define OF_CONTROL 1 # endif #else # define OF_CONTROL 0 #endif Now CONFIG_IS_ENABLED(OF_CONTROL) is the substitute. It refers to CONFIG_OF_CONTROL for U-boot proper and CONFIG_SPL_OF_CONTROL for SPL. Also, we no longer have to cancel CONFIG_OF_CONTROL in include/config_uncmd_spl.h and scripts/Makefile.spl. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> |
#
6e780c7a |
|
23-Jun-2015 |
Simon Glass <sjg@chromium.org> |
ns16550: Improve debug UART so it can work with 32-bit access Since Rockchip requires 32-bit serial access, add this to the driver. Refactor a little to make this easier. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
90914008 |
|
12-May-2015 |
Simon Glass <sjg@chromium.org> |
dm: ns16550: Support CONFIG_SYS_NS16550_MEM32 with driver model This option is used by some boards, so support it with driver model. This is really ugly - we should rewrite this driver once all users are moved to driver model. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4f60166c |
|
24-Apr-2015 |
Axel Lin <axel.lin@ingics.com> |
serial: ns16550: Remove hard-coded baud_divisor setting This was accidentally added by commit dd0b0122bacc "serial: ns16550: Add an option to specify the debug UART register shift". Remove it. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
ab9fd2e8 |
|
27-Feb-2015 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Remove unnecessary init on UART setup It is not necessary to write a zero baud rate to the device, and for some chips this will cause problems. Drop this code. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
363e6da1 |
|
27-Feb-2015 |
Simon Glass <sjg@chromium.org> |
dm: ns16550: Support non-byte register spacing with driver model Allow this driver to support boards where the register shift is not 0. This fixes some compiler warnings which appear in that case. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
dd0b0122 |
|
27-Feb-2015 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Add an option to specify the debug UART register shift This UART permits different register spacing. To support the debug UART on devices which have a spacing other than 1 byte, allow the shift value to be specified. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
0eb25b61 |
|
22-Mar-2015 |
Joe Hershberger <joe.hershberger@ni.com> |
common: Make sure arch-specific map_sysmem() is defined In the case where the arch defines a custom map_sysmem(), make sure that including just mapmem.h is sufficient to have these functions as they are when the arch does not override it. Also split the non-arch specific functions out of common.h Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
20379c11 |
|
28-Feb-2015 |
Axel Lin <axel.lin@ingics.com> |
serial: ns16550: Fix build error due to a typo Fix trivial typo. Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Axel Lin <axel.lin@ingics.com> |
#
21d00436 |
|
26-Jan-2015 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support debug UART Add debug UART functions to permit ns16550 to provide an early debug UART. Try to avoid using the stack so that this can be called from assembler before a stack is set up (at least on ARM and PowerPC). Signed-off-by: Simon Glass <sjg@chromium.org> |
#
76571674 |
|
26-Jan-2015 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Add access functions that don't need platdata For the debug UART we need to be able to provide any parameters before driver model is set up. Add parameters to the low-level access functions to make this possible. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
3db886a5 |
|
31-Dec-2014 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Support ns16550 compatible pci uart devices There are many pci uart devices which are ns16550 compatible. We can describe them in the board dts file and use it as the U-Boot serial console as specified in the chosen node 'stdout-path' property. Those pci uart devices can have their register be memory-mapped, or i/o-mapped. The driver will try to use the memory-mapped register if the reg property in the node has an entry to describe the memory-mapped register, otherwise i/o-mapped register will be used. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
956a8bae |
|
10-Nov-2014 |
Gregoire Gentil <gregoire@gentil.com> |
ns16550.c: Fix for ns16550 driver hanging on OMAP4 The same problem that is seen on some OMAP3 is also seen on some OMAP4 so include them in the test in order to prevent some hangs during SPL. [trini: Re-word commit message, make apply cleanly] Signed-off-by: Tom Rini <trini@ti.com> |
#
1f77690e |
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10-Oct-2014 |
Simon Glass <sjg@chromium.org> |
dm: serial: ns16550: Add a cast to the I/O operations This generates a warning when driver model is enabled, so fix it by adding a cast. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
11c1a878 |
|
22-Oct-2014 |
Simon Glass <sjg@chromium.org> |
dm: ns16550: Correct the probe logic for platform data The probe logic sets up the pointer to the platform data in the device tree decode method. It should be done in the probe() method, and anyway the device tree decode method can't be used when CONFIG_OF_CONTROL is not enabled. Fix these two problems. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@ti.com> |
#
167efe01 |
|
22-Oct-2014 |
Simon Glass <sjg@chromium.org> |
dm: ns16550: Use an address instead of a pointer for the uart base It is inconvenient to have to use casts when specifying platform data. Also it is not strictly correct, since we should use map_sysmem() to convert an address to a pointer. Adjust the platform data to use an address. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@ti.com> |
#
aea2be20 |
|
22-Oct-2014 |
Simon Glass <sjg@chromium.org> |
dm: serial: ns16550: Correct logic for checking for character There is a bug in the logic which checks for an available character. This can cause invalid characters to be received - this was noticed on beaglebone. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@ti.com> |
#
12e431b2 |
|
04-Sep-2014 |
Simon Glass <sjg@chromium.org> |
dm: serial: Add driver model support for ns16550 Add driver model support so that ns16550 can support operation both with and without driver model. The driver needs a clock frequency so cannot stand alone unfortunately. The clock frequency must be provided by a separate driver. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8bbe33c8 |
|
04-Sep-2014 |
Simon Glass <sjg@chromium.org> |
dm: serial: Collect common baud rate code in ns16550 The same sequence is used in several places, so move it into a function. Note that UART_LCR_BKSE is an alias for UART_LCR_DLAB. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
fa54eb12 |
|
04-Sep-2014 |
Simon Glass <sjg@chromium.org> |
dm: serial: Move baud rate calculation to ns16550.c Move the function that calculates the baud rate divisor into ns16550.c so it can be used by that file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8ac22a60 |
|
30-Jul-2014 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
omap: clean-up dead configs The following configs are not defined at all. - CONFIG_OMAP1510 - CONFIG_OMAP_1510P1 - CONFIG_OMAP_SX1 - CONFIG_OMAP3_DMA - CONFIG_OMAP3_ZOOM2 - CONFIG_OMAP_INNOVATOR Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Tom Rini <trini@ti.com> |
#
7c387646 |
|
15-Jul-2014 |
Khoronzhuk, Ivan <ivan.khoronzhuk@ti.com> |
keystone2: use CONFIG_SOC_KEYSTONE in common places Use CONFIG_SOC_KEYSTONE in common places instead of defining a lot of "if def .. || if def " for different Keystone2 SoC types. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> |
#
d57dee57 |
|
09-Apr-2014 |
Karicheri, Muralidharan <m-karicheri2@ti.com> |
serial: nsl16550: add hw flow control support keystone serial hw support hw flow control. This patch enables hw flow control for keystone EVMs as an optional feature based on CONFIG_SERIAL_HW_FLOW_CONTROL. Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> |
#
ef509b90 |
|
04-Apr-2014 |
Vitaly Andrianov <vitalya@ti.com> |
k2hk: add support for k2hk SOC and EVM k2hk EVM is based on Texas Instruments Keystone2 Hawking/Kepler SoC. Keystone2 SoC has ARM v7 Cortex-A15 MPCore processor. Please refer the ti/k2hk_evm/README for details on the board, build and other information. This patch add support for keystone architecture and k2hk evm. Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: WingMan Kwok <w-kwok2@ti.com> Signed-off-by: Sandeep Nair <sandeep_n@ti.com> |
#
456ccfdf |
|
20-Dec-2013 |
Tom Rini <trini@konsulko.com> |
TI:omap3: Drop omap3_zoom2 The omap3_zoom2 board has not been updated for a correct CONFIG_SYS_HZ and Tom Rix's email has long been bouncing. Signed-off-by: Tom Rini <trini@ti.com> |
#
9ed6e412 |
|
01-Jul-2013 |
TENART Antoine <atenart@adeneo-embedded.com> |
Prepare for TI816X : reuse existing code from TI814X Rename some CONFIG_TI814X to a more generic CONFIG_TI81XX Signed-off-by: Antoine Tenart <atenart@adeneo-embedded.com> [trini: Adapt for CONFIG_OMAP_COMMON changes, AM43XX] Signed-off-by: Tom Rini <trini@ti.com> |
#
57180408 |
|
30-Jul-2013 |
Lokesh Vutla <lokeshvutla@ti.com> |
ARM: AM43xx: Add build support Add AM43xx support in the required places Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> |
#
7f5eef93 |
|
03-Jun-2013 |
Tom Rini <trini@konsulko.com> |
arm: Remove OMAP2420H4 and all omap24xx support The omap2420H4 was the only mainline omap24xx board. Prior to being fixed by Jon Hunter in time for v2013.04 it had been functionally broken for a very long time. Remove this board as there's not been interest in it in U-Boot for quite a long time. Signed-off-by: Tom Rini <trini@ti.com> |
#
fd2aeac5 |
|
28-Mar-2013 |
Manfred Huber <man.huber@arcor.de> |
omap3_beagle: Flush UART3 xmit on enable if TEMT is broken Flush UART3 xmit on enable if TEMT is broken On some OMAP3 devices when UART3 is configured for boot mode before SPL starts only THRE bit is set. We have to empty the transmitter before initialization starts. This patch avoids the use of CONFIG_SYS_NS16550_BROKEN_TEMT. Signed-off-by: Manfred Huber <man.huber@arcor.de> Tested-by: Javier Martinez Canillas <javier@dowhile0.org> Tested-by: Andreas Bießmann <andreas.devel@googlemail.com> |
#
6213a68f |
|
15-Mar-2013 |
Matt Porter <mporter@ti.com> |
ns16550: enable quirks for ti814x TI814X requires the same quirks as AM33XX to be enabled. Signed-off-by: Matt Porter <mporter@ti.com> Reviewed-by: Tom Rini <trini@ti.com> |
#
69e06832 |
|
05-Mar-2013 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Remove unwanted cast This cast does not seem correct, since we should be writing to a pointer, not a ulong. This fixes the following warning on nds32: -ns16550.c:49: warning: passing argument 2 of 'writeb' makes pointer from integer without a cast Signed-off-by: Simon Glass <sjg@chromium.org> |
#
7de0fe1a |
|
06-Jan-2013 |
Javier Martinez Canillas <javier@dowhile0.org> |
serial/ns16550: add an option to avoid hanging on broken platforms Some platforms (e.g. IGEPv2 board) has a broken ns16550 UART that does not set the TEMT bit when the transmitter is empty in SPL. This makes U-Boot to hang while waiting for TEMT to be set. Add a new option to avoid this: CONFIG_SYS_NS16550_BROKEN_TEMT 16550 UART set the Transmitter Empty (TEMT) Bit when all output has finished and the transmitter is totally empty. U-Boot waits for this bit to be set to initialize the serial console. On some broken platforms this bit is not set in SPL making U-Boot to hang while waiting for TEMT. Define this option to avoid it. Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> |
#
cb55b332 |
|
18-Sep-2012 |
Scott Wood <scottwood@freescale.com> |
serial/ns16550: wait for TEMT before initializing TEMT is set when the transmitter is totally empty and all output has finished. This prevents output problems (including a loss of synchronization observed on p2020 that persisted for quite a while) if SPL has output still on its way out. Signed-off-by: Scott Wood <scottwood@freescale.com> -- v2: fixed typo in subject, and explained what the bit does in the changelog |
#
f2041388 |
|
15-Sep-2012 |
Marek Vasut <marex@denx.de> |
serial: ns16550: Call usbtty_poll only in non-SPL build Having both USBTTY and CONFIG_SERIAL_MULTI enabled in SPL, the usbtty.c file is protected in Makefile to not be compiled into the SPL. Yet, the ns16550 serial driver does not contain such protection. Add it to avoid missing symbol error. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Marek Vasut <marek.vasut@gmail.com> Cc: Tom Rini <trini@ti.com> |
#
99b603e7 |
|
09-Jul-2012 |
Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com> |
serial/ns16550: ns16550 has a different register layout on SOC_DA8XX also fix NS16550_init() as we need 16x divider Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com> Acked-by: Christian Riesch <christian.riesch@omicron.at> Tested-by: Christian Riesch <christian.riesch@omicron.at> Acked-by: Sughosh Ganu <urwithsughosh@gmail.com> Tested-by: Sughosh Ganu <urwithsughosh@gmail.com> |
#
5289e83a |
|
13-Oct-2011 |
Chandan Nath <chandan.nath@ti.com> |
ARM:AM33XX: Add support for TI AM335X EVM This patch adds basic support for booting the board. This patch adds support for the UART necessary to get to the u-boot prompt. Signed-off-by: Chandan Nath <chandan.nath@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> |
#
f8df9d0d |
|
15-Oct-2011 |
Simon Glass <sjg@chromium.org> |
NS16550: trivial code clean for checkpatch This removes most checkpatch warnings from the ns16550 driver and its header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
79df1208 |
|
01-Sep-2011 |
Dave Aldridge <fovsoft@gmail.com> |
ns16550: change to allow 32 bit access to registers If CONFIG_SYS_NS16550_MEM32 is defined then 32 bit memory mapped access will be used to read/write the uart registers. This is especially useful for SoC devices that implement 16550 compatible uarts but that have peripheral access width constraints. Signed-off-by: Dave Aldridge <fovsoft@gmail.com> |
#
a160ea0b |
|
27-Oct-2010 |
Prafulla Wadaskar <prafulla@marvell.com> |
Serial: ns16550: Add support for CONFIG_SYS_NS16550_IER macro On some processors this ier register configuration is different for ex. Marvell Armada100 This patch introduce CONFIG_SYS_NS16550_IER macro support to unconditionally initialize this register. Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com> |
#
1a2d9b30 |
|
12-Oct-2010 |
Stefan Roese <sr@denx.de> |
ns16550: Add WATCHDOG_RESET to putc for short watchdog timeout boards Call watchdog_reset() upon newline. This is done here in putc since the environment code uses a single puts() to print the complete envrironment upon "printenv". So we can't put this watchdog call in puts(). This is needed for boards with a very short watchdog timeout, like the lwmon5 with a 100ms timeout. Without this patch this board resets in the commands with long outputs, like "printenv" or "fdt print". Note that the image size is not increased with this patch when CONFIG_HW_WATCHDOG or CONFIG_WATCHDOG are not defined since the compiler optimizes this additional code away. Signed-off-by: Stefan Roese <sr@denx.de> Fix typo in comment. Signed-off-by: Wolfgang Denk <wd@denx.de> |
#
167cdad1 |
|
23-Apr-2010 |
Graeme Russ <graeme.russ@gmail.com> |
SERIAL: Enable port-mapped access The x86 architecture exclusively uses Port-Mapped I/O (inb/outb) to access the 16550 UARTs. This patch mimics how Linux selects between Memory-Mapped and Port-Mapped I/O. This allows x86 boards to use CONFIG_SERIAL_MUTLI and drop the custom serial port driver Signed-off-by: Graeme Russ <graeme.russ@gmail.com> |
#
a47a12be |
|
15-Apr-2010 |
Stefan Roese <sr@denx.de> |
Move arch/ppc to arch/powerpc As discussed on the list, move "arch/ppc" to "arch/powerpc" to better match the Linux directory structure. Please note that this patch also changes the "ppc" target in MAKEALL to "powerpc" to match this new infrastructure. But "ppc" is kept as an alias for now, to not break compatibility with scripts using this name. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Wolfgang Denk <wd@denx.de> Acked-by: Detlev Zundel <dzu@denx.de> Acked-by: Kim Phillips <kim.phillips@freescale.com> Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Anatolij Gustschin <agust@denx.de> |
#
a1b322a9 |
|
01-Feb-2010 |
Ladislav Michl <ladis@linux-mips.org> |
ns16550: kick watchdog while waiting for a character ns16550 busyloops waiting for incoming byte causing watchdog to reboot while waiting for a key press. A call to WATCHDOG_RESET in NS16550_getc loop fixes it. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> |
#
660888b7 |
|
30-May-2009 |
Tom Rix <Tom.Rix@windriver.com> |
ZOOM2 Add serial support. Zoom2 serial is in general supplied by one of the 4 UARTS on the debug board. The default serial is from the USB connector on left side of the debug board. The USB connector will produce 2 of the 4 UARTS. On your host pick the first enumeration. The details of the setting of the serial gpmc setup are not available. The values were provided by another party. The serial port set up is the same with Zoom1. Baud rate 115200, 8 bit data, no parity, 1 stop bit, no flow. The kernel bootargs are console=ttyS3,115200n8 Signed-off-by: Tom Rix <Tom.Rix@windriver.com> |
#
200779e3 |
|
03-Apr-2009 |
Detlev Zundel <dzu@denx.de> |
Rename common ns16550 constants with UART_ prefix to prevent conflicts Fix problems introduced in commit 7b5611cdd12ca0cc33f994f0d4a4454788fc3124 [inka4x0: Add hardware diagnosis functions for inka4x0] which redefined MSR_RI which is already used on PowerPC systems. Also eliminate redundant definitions in ps2mult.h. More cleanup will be needed for other redundant occurrences though. Signed-off-by: Detlev Zundel <dzu@denx.de> |
#
b4746d8b |
|
11-Feb-2009 |
Mike Frysinger <vapier@gentoo.org> |
drivers/serial/ns16550: move ifdef into Makefile COBJS-$(...) Signed-off-by: Mike Frysinger <vapier@gentoo.org> |
#
f5675aa5 |
|
18-Feb-2009 |
Ron Madrid <ron_madrid@sbcglobal.net> |
Create configuration option for restricted ns16550 functions This patch will create a configuration option for a minimum configuration for the ns16550 serial driver at drivers/serial/ns16550.c and will apply this new configuration option to the SIMPC8313.h config file in order to fix the NAND bootstrap build error. This option will exclude all functions with exception of NS16550_putc and NS16550_init. This will be used primarily to save space and remove unused code from builds in which space is limited. Signed-off-by: Ron Madrid <ron_madrid@sbcglobal.net> |
#
6d0f6bcf |
|
16-Oct-2008 |
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
rename CFG_ macros to CONFIG_SYS Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
#
7ec8bb15 |
|
27-Dec-2007 |
Wolfgang Denk <wd@denx.de> |
OMAP5912: fix FIFO handling in UART driver According to the OMAP5912 Serial Interfaces Reference Guide (see http://focus.ti.com/lit/ug/spru760c/spru760c.pdf, page 150), the FIFO_EN enable bit in the FIFO Control Register (FCR) can only be changed when the baud clock is not running, i. e. when both DLL and DLH are set to 0. Thus make sure that DLL and DLH are 0 when writing the FCR. Signed-off-by: Wolfgang Denk <wd@denx.de> |
#
1378df79 |
|
24-Nov-2007 |
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
drivers/serial : move serial drivers to drivers/serial Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
#
29caf930 |
|
02-Sep-2022 |
Stefan Roese <sr@denx.de> |
cyclic: Use schedule() instead of WATCHDOG_RESET() Globally replace all occurances of WATCHDOG_RESET() with schedule(), which handles the HW_WATCHDOG functionality and the cyclic infrastructure. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Tom Rini <trini@konsulko.com> [am335x_evm, mx6cuboxi, rpi_3,dra7xx_evm, pine64_plus, am65x_evm, j721e_evm] |
#
5e998b4d |
|
23-Jun-2022 |
Pali Rohár <pali@kernel.org> |
serial: ns16550: Wait in debug_uart_init until tx buffer is empty Commit d293759d55cc ("serial: ns16550: Add support for SPL_DEBUG_UART_BASE") fixed support for setting correct early debug UART base address in SPL. But after this commit, output from Marvell A385 BootROM is truncated or lost and not fully present on serial console. Debugging this issue showed that BootROM just put bytes into UART HW output buffer and does not wait until UART HW transmit all characters. U-Boot ns16550 early debug is initialized very early and during its initialization is resetting UART HW and flushing remaining transmit buffer (which still contains BootROM output). Fix this issue by waiting in init function prior resetting UART HW until TxEmpty bit in UART Line Status Register is set. TxEmpty is set when all remaining bytes from HW buffer are transmitted. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> [trini: Add comment, move ';' to new line per checkpatch.pl] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
d293759d |
|
06-May-2022 |
Pali Rohár <pali@kernel.org> |
serial: ns16550: Add support for SPL_DEBUG_UART_BASE Use CONFIG_VAL(DEBUG_UART_BASE) instead of CONFIG_DEBUG_UART_BASE, so proper config value (CONFIG_DEBUG_UART_BASE or CONFIG_SPL_DEBUG_UART_BASE) is used based on building target. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
04ee76c9 |
|
09-Apr-2022 |
Johan Jonker <jbx6244@gmail.com> |
rockchip: serial: move driver alias to serial_rockchip.c The Rockchip uart DT nodes have "snps,dw-apb-uart" as fall back string. The driver ns16550.c has CONFIG_IS_ENABLED(OF_REAL) as condition to of_match and does not copy dtplat data. For TPL/SPL the driver serial_rockchip.c is used. Move driver alias to correct driver. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
f899cc14 |
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12-Sep-2021 |
Tom Rini <trini@konsulko.com> |
ti: keystone: Move away from CONFIG_SOC_KEYSTONE We have individual SOC symbols for each keystone 2 platform. Use the existing CONFIG_ARCH_KEYSTONE rather than CONFIG_SOC_KEYSTONE to encompass all of the keystone families. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
414cc151 |
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07-Aug-2021 |
Simon Glass <sjg@chromium.org> |
treewide: Simply conditions with the new OF_REAL Use this new Kconfig to simplify the compilation conditions where appropriate. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
384b62c0 |
|
03-Feb-2021 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Handle zero <clock-frequency> value A working device tree node of ns16550 should never be populated with value zero for the <clock-frequency> property. Unfortunately this is the case for the QEMU ppce500 target. Let's try to assign plat->clock to CONFIG_SYS_NS16550_CLK as the last resort to handle such case. This commit should be reverted when: - The following QEMU patch [1] is merged, and - U-Boot CI has upgraded its QEMU version that contains the fix [1] http://patchwork.ozlabs.org/project/qemu-devel/patch/1612362288-22216-2-git-send-email-bmeng.cn@gmail.com/ Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
09bd0840 |
|
03-Feb-2021 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Correct the base address type Currently ns16550_serial_assign_base() treats the argument 'base' with type `ulong`. This is incorrect because the base address was obtained from device tree with type `fdt_addr_t` that can represent a physical address larger than 32-bit in a 32-bit system. Fixes: 9e6ce62190b7 ("serial: ns16550: Fix ordering of getting base address") Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
401d1c4f |
|
30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
bdf8fd76 |
|
28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
0fd3d911 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com> |
#
2d6bf754 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
#
d30c7209 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
41575d8e |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo |
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de> |
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> |
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se> |
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> |
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com |
#
9ad3b049 |
|
02-Nov-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: add setconfig support Add possibility to update the serial parity used. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com> |
#
46879196 |
|
24-Oct-2018 |
Bin Meng <bmeng.cn@gmail.com> |
serial: Remove DM_FLAG_PRE_RELOC flag in various drivers When a driver declares DM_FLAG_PRE_RELOC flag, it wishes to be bound before relocation. However due to a bug in the DM core, the flag only takes effect when devices are statically declared via U_BOOT_DEVICE(). This bug has been fixed recently by commit "dm: core: Respect drivers with the DM_FLAG_PRE_RELOC flag in lists_bind_fdt()", but with the fix, it has a side effect that all existing drivers that declared DM_FLAG_PRE_RELOC flag will be bound before relocation now. This may expose potential boot failure on some boards due to insufficient memory during the pre-relocation stage. To mitigate this potential impact, the following changes are implemented: - Remove DM_FLAG_PRE_RELOC flag in the driver, if the driver only supports configuration from device tree (OF_CONTROL) - Keep DM_FLAG_PRE_RELOC flag in the driver only if the device is statically declared via U_BOOT_DEVICE() - Surround DM_FLAG_PRE_RELOC flag with OF_CONTROL check, for drivers that support both statically declared devices and configuration from device tree Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
6f57c344 |
|
09-Aug-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), let's rather ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
5d754197 |
|
27-Aug-2018 |
Lokesh Vutla <lokeshvutla@ti.com> |
serial: omap: Introduce DM specific omap serial Add driver model support for OMAP_SERIAL while reusing the functions in ns16550.c Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Tested-by: Derald D. Woods <woods.technical@gmail.com> |
#
b051eecb |
|
14-Jun-2018 |
Ley Foon Tan <ley.foon.tan@intel.com> |
serial: ns16550: Add reset ctrl to driver Add code to reset all reset signals as in serial DT node. A reset property is an optional feature, so do not fail if a reset property is not present. If a reset property is discovered, then use it to deassert, thus bringing the IP out of reset. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
78b7d37b |
|
15-Feb-2018 |
Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> |
ns16550: Fix mem mapped endian check Do a explicit check for CONFIG_SYS_BIG_ENDIAN and CONFIG_SYS_LITTLE_ENDIAN to avoid errors on platforms where both are undefined (x86). Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> Reviewed-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com> |
#
4dbf9bed |
|
15-Jan-2018 |
Mario Six <mario.six@gdsys.cc> |
serial: ns16550: Fix style violation Clarify the computation precedence in two ternary operator constructions. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc> |
#
7fded0ce |
|
16-Aug-2017 |
Stefan Roese <sr@denx.de> |
Revert "serial: ns16550: Add RX interrupt buffer support" This reverts commit 6822cf3ec7c8768b8727573b8f4b2cb3d870b881. As Bin Meng has tested and pointed out, we don't need the RX interrupt for the RX buffer support at all. Just reading all available characters into a buffer is sufficient to solve the problem with the dropped characters upon long lines pasted into the U-Boot prompt. Since this RX buffer support can be implemented in a generic way, without any device specifica (e.g. for the ns16550), I'll post a new patch with a new serial RX buffer support for DM, which all DM based serial drivers can use. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
6822cf3e |
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14-Jul-2017 |
Stefan Roese <sr@denx.de> |
serial: ns16550: Add RX interrupt buffer support Pasting longer lines into the U-Boot console prompt sometimes leads to characters missing. One problem here is the small 16-byte FIFO of the legacy NS16550 UART, e.g. on x86 platforms. This patch now introduces a Kconfig option to enable RX interrupt buffer support for NS16550 style UARTs. With this option enabled, I was able paste really long lines into the U-Boot console, without any characters missing. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> [trini: Guard ns16550_serial_remove with CONFIG_IS_ENABLED(SERIAL_PRESENT) to match struct assignment] Signed-off-by: Tom Rini <trini@konsulko.com> |
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8d3a2568 |
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11-Jul-2017 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-dm
|
#
db9f8f6a |
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12-Jun-2017 |
Simon Glass <sjg@chromium.org> |
dm: serial: ns16550: Convert to livetree Update this driver to support a live device tree. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Tested-on: Beaver, Jetson-TK1 |
#
3d40479f |
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07-Jun-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
rockchip: ns16550: dm: convert fdt_get to dev_read With the new dev_read functions available, we can convert the rockchip architecture-specific drivers and common drivers used by these devices over to the dev_read family of calls. This covers the serial driver (ns16550 and compatible) used for the Rockchip devices. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
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a821c4af |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: Rename dev_addr..() functions These support the flat device tree. We want to use the dev_read_..() prefix for functions that support both flat tree and live tree. So rename the existing functions to avoid confusion. In the end we will have: 1. dev_read_addr...() - works on devices, supports flat/live tree 2. devfdt_get_addr...() - current functions, flat tree only 3. of_get_address() etc. - new functions, live tree only All drivers will be written to use 1. That function will in turn call either 2 or 3 depending on whether the flat or live tree is in use. Note this involves changing some dead code - the imx_lpi2c.c file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
89024ddc |
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12-May-2017 |
Tom Rini <trini@konsulko.com> |
TI: Drop 'CONFIG_OMAP' In the two cases in the code where we use CONFIG_OMAP as a useful test currently we can make use of CONFIG_ARCH_OMAP2PLUS instead. With that changed we can drop all defines of CONFIG_OMAP. While in here, CONFIG_OMAP3430 is only defined and then never used, so drop. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
a52cf086 |
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22-Apr-2017 |
Lokesh Vutla <lokeshvutla@ti.com> |
serial: omap: Support debug UART Add debug UART functions to permit omap specific ns16550 to provide an early debug UART. This is mostly in common with DEBUG_UART_NS16550 except for Mode definition register which is required for selecting UART mode(16x auto-baud or 13x mode). Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
6f8c351e |
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27-Mar-2017 |
Alexandru Gagniuc <alex.g@adaptrum.com> |
serial: ns16550: Link in the DM driver when when using platdata Do not condition the compilation of the U_BOOT_DRIVER by !OF_PLATDATA. This is inconsistent with the majority of other drivers. This also blocks OF_PLATDATA boards with an 16550-compatible serial from using serial in SPL. Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com> Reviewed-by: Simon Glass <sjg@chromium.org> Added tweak for rock to avoid a TPL build failure: Signed-off-by: Simon Glass <sjg@chromium.org> |
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e160f7d4 |
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17-Jan-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
17fa0326 |
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18-Jan-2017 |
Heiko Schocher <hs@denx.de> |
serial, ns16550: bugfix: ns16550 fifo not enabled commit: 65f83802b7a5b "serial: 16550: Add getfcr accessor" breaks u-boot commandline working with long commands sending to the board. Since the above patch, you have to setup the fcr register. For board/archs which enable OF_PLATDATA, the new field fcr in struct ns16550_platdata is not filled with a default value ... This leads in not setting up the uarts fifo, which ends in problems, when you send long commands to u-boots commandline. Detected this issue with automated tbot tests on am335x based shc board. The error does not popup, if you type commands. You need to copy&paste a long command to u-boots commandshell (or send a long command with tbot) Possible boards/plattforms with problems: ./arch/arm/cpu/arm926ejs/lpc32xx/devices.c ./arch/arm/mach-tegra/board.c ./board/overo/overo.c ./board/quipos/cairo/cairo.c ./board/logicpd/omap3som/omap3logic.c ./board/logicpd/zoom1/zoom1.c ./board/timll/devkit8000/devkit8000.c ./board/lg/sniper/sniper.c ./board/ti/beagle/beagle.c ./drivers/serial/serial_rockchip.c Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Tested-by: Adam Ford <aford173@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
0b060eef |
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30-Nov-2016 |
Marek Vasut <marex@denx.de> |
serial: 16550: Add Ingenic JZ4780 support Add compatibility string for the Ingenic JZ4780 SoC, the necessary UART enable bit into FCR and register shift. Neither are encoded in the DTS coming from Linux, so we need to support it this way. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
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79fd9281 |
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30-Nov-2016 |
Marek Vasut <marex@denx.de> |
serial: 16550: Add port type as driver data Add driver data to each compatible string to identify the type of the port. Since all the ports in the driver are entirely compatible with 16550 for now, all are marked with PORT_NS16550. But, there are ports which have specific quirks, like the JZ4780 UART, which do not have any DT property to denote the quirks. Instead, Linux uses the compatible string to discern such ports and enable the necessary quirks. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> |
#
65f83802 |
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30-Nov-2016 |
Marek Vasut <marex@denx.de> |
serial: 16550: Add getfcr accessor Add function which allows fetching the default FCR register setting from platform data for DM , while retaining old behavior for non-DM by returning UART_FCRVAL. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
021abf69 |
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26-Sep-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
Revert "ns16650: Make sure we have CONFIG_CLK set before using infrastructure" This reverts commit 82f5279b0cd99a9163d34cfe926d0316d9dc0d37. The build failure of k2*evm boards was fixed in a different way by the previous commit. It is nasty to patch generic drivers around with #ifdef CONFIG_CLK just for the KeyStone's matter. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
ab895d6a |
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30-Sep-2016 |
Alexandre Courbot <acourbot@nvidia.com> |
serial: ns16550: Handle -ENOENT when requesting clock When calling clk_get_by_index(), fall back to the legacy method of getting the clock if -ENOENT is returned. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> |
#
82f5279b |
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22-Sep-2016 |
Tom Rini <trini@konsulko.com> |
ns16650: Make sure we have CONFIG_CLK set before using infrastructure We cannot call on the CONFIG_CLK based clk_get_rate function unless CONFIG_CLK is set. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
50fce1d5 |
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08-Sep-2016 |
Paul Burton <paul.burton@mips.com> |
serial: ns16550: Support clocks via phandle Previously ns16550 compatible UARTs probed via device tree have needed their device tree nodes to contain a clock-frequency property. An alternative to this commonly used with Linux is to reference a clock via a phandle. This patch allows U-Boot to support that, retrieving the clock frequency by probing the appropriate clock device. For example, a system might choose to provide the UART base clock as a reference to a clock common to multiple devices: sys_clk: clock { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <10000000>; }; uart0: uart@10000000 { compatible = "ns16550a"; reg = <0x10000000 0x1000>; clocks = <&sys_clk>; }; uart1: uart@10000000 { compatible = "ns16550a"; reg = <0x10001000 0x1000>; clocks = <&sys_clk>; }; This removes the need for the frequency information to be duplicated in multiple nodes and allows the device tree to be more descriptive of the system. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
b2927fba |
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04-Jul-2016 |
Simon Glass <sjg@chromium.org> |
dm: serial: ns16550: Update to support of-platdata With of-platdata this driver cannot know the format of the of-platdata struct, so we cannot use generic code for accessing the of-platdata. Each SoC that uses this driver will need to set up ns16550's platdata for it. So don't compile in the generic code. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
03c6f176 |
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24-May-2016 |
Marek Vasut <marex@denx.de> |
serial: 16550: Drop OMAP1510 support The CONFIG_OMAP1510 is no longer defined, so remove this dead code. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Nishanth Menon <nm@ti.com> |
#
fa4ce723 |
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24-May-2016 |
Marek Vasut <marex@denx.de> |
serial: 16550: Make serial_io/out_shift available to debug mode The ns16550 driver needs serial_in_shift() and serial_out_shift() when compiled in debug UART mode, so shift the DM_SERIAL check a little to make these functions available. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
df8ec55d |
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17-May-2016 |
Paul Burton <paul.burton@mips.com> |
dm: ns16550: Don't map_physmem for I/O ports If the UART is to be accessed using I/O port accessors (inb & outb) then using map_physmem doesn't make sense, since it operates in a different memory space. Remove the call to map_physmem when CONFIG_SYS_NS16550_PORT_MAPPED is defined, allowing I/O port addresses to not be mangled by the incorrect mapping. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> |
#
59b35ddd |
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16-Feb-2016 |
Michal Simek <michal.simek@amd.com> |
dm: ns16550: Add support for reg-offset property reg-offset is the part of standard 8250 binding in the kernel. It is shifting start of address space by reg-offset. On Xilinx platform this offset is typically 0x1000. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Moved the new field to the end of the struct to avoid problems: Signed-off-by: Simon Glass <sjg@chromium.org> |
#
e5e88c65 |
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29-Feb-2016 |
Tom Rini <trini@konsulko.com> |
Revert "dm: ns16550: Add support for reg-offset property" This reverts commit d9a3bec682f9756621615f4306718a356a3230e3. While this is a correct change to do long term it unfortunately breaks a number of platforms that are using pdata and not named struct members so they are getting all of their data after 'base' incorrect. Acked-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
d9a3bec6 |
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16-Feb-2016 |
Michal Simek <michal.simek@amd.com> |
dm: ns16550: Add support for reg-offset property reg-offset is the part of standard 8250 binding in the kernel. It is shifting start of address space by reg-offset. On Xilinx platform this offset is typically 0x1000. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
cc4228f9 |
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14-Dec-2015 |
Thomas Chou <thomas@wytron.com.tw> |
ns16550: zap the rockchip serial compatible string Zap the rockchip serial compatible string, because rockchip serial has "snps,dw-apb-uart" compatible string in the dts. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org> |
#
b7e29834 |
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13-Dec-2015 |
Simon Glass <sjg@chromium.org> |
dm: ns16550: Allow the driver to be omitted if requested Allow the ns16550 debug UART to be used without the full driver. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Thomas Chou <thomas@wytron.com.tw> |
#
fcc0a877 |
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29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: serial: Convert ns16550 driver to use driver model PCI API Use the driver model version of the function to find the BAR. This updates the fdtdec function, of which ns16550 is the only user. The fdtdec_get_pci_bdf() function is dropped for several reasons: - with driver model we should use 'struct udevice *' rather than passing the device tree offset explicitly - there are no other users in the tree - the function parses for information which is already available in the PCI device structure (specifically struct pci_child_platdata which is available at dev_get_parent_platdata(dev) Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> |
#
b7e5a643 |
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04-Dec-2015 |
Simon Glass <sjg@chromium.org> |
dm: serial: ns16550: Add pre-reloc flag to the driver For platforms that don't use device tree in SPL the only way to mark this driver as 'required by relocation' is with the DM_FLAG_PRE_RELOC flag. Add this to ensure that the driver is bound. Fixes: fde7e18938d8 ("dm: tegra: pci: Move CONFIG_PCI_TEGRA to Kconfig") Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Stephen Warren <swarren@nvidia.com> Acked-by: Thomas Chou <thomas@wytron.com.tw> |
#
80e06146 |
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28-Nov-2015 |
Thomas Chou <thomas@wytron.com.tw> |
ns16550: change reg-shift property default to zero Change reg-shift property default to zero. When the integer property is missing, it should be taken as zero. This is consistent to Linux drivers/tty/serial/of_serial.c. The x86 and most powerpc use reg-shift of 0. Most others use reg-shift of 2. While reg-shift of 1 is rarely used. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Acked-by: Simon Glass <sjg@chromium.org> |
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a51dbebf |
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16-Nov-2015 |
huang lin <hl@rock-chips.com> |
rockchip: serial driver support rk3036 Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
4fb60552 |
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19-Nov-2015 |
Thomas Chou <thomas@wytron.com.tw> |
ns16550: zap CONFIG_NS16550_SERIAL Zap CONFIG_NS16550_SERIAL, as the unification of ns16550 drivers is completed. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
8e62d32e |
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19-Nov-2015 |
Thomas Chou <thomas@wytron.com.tw> |
ns16550: add generic binding to unify the drivers Add generic binding to unify ns16550 drivers. There are several drivers using almost the same code, such as serial_dw, serial_keystone, serial_omap, serial_ppc, serial_rockchip, serial_tegra.c, and serial_x86. But each is platform specific. The key difference between these drivers is the way to get input clock frequency. With this unified approach, fixed clock frequency should be extracted from "clock-frequency" property of device tree blob. If this property is not available, the macro CONFIG_SYS_NS16550_CLK will be used. It can be a constant or a function to get clock, eg, get_serial_clock(). Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de> Acked-by: Simon Glass <sjg@chromium.org> |
#
77d7b5cd |
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19-Nov-2015 |
Thomas Chou <thomas@wytron.com.tw> |
ns16550: change map_sysmem to map_physmem Change map_sysmem() to map_physmem(,,MAP_NOCACHE). Though map_sysmem() can be used to map system memory, it might be wrong to use it for I/O ports. The map_physmem() serves the same purpose to translate physical address to virtual address with the additional flag to take care of cache property. Most drivers use map_physmem() since I/O ports access should be uncached. As ns16550 is a driver, it should use map_physmem() rather than map_sysmem(). Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org> |
#
97b05973 |
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18-Oct-2015 |
Simon Glass <sjg@chromium.org> |
debug_uart: Adjust the declaration of debug_uart_init() We want to be able to add other common code to this function. So change the driver's version to have an underscore before it, just like _debug_uart_putc(). Define debug_uart_init() to call this version. Update all drivers to this new method. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
4e9838c1 |
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11-Aug-2015 |
Simon Glass <sjg@chromium.org> |
dm: Use dev_get_addr() where possible This is a convenient way for a driver to get the hardware address of a device, when regmap or syscon are not being used. Change existing callers to use it as an example to others. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> |
#
0f925822 |
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11-Aug-2015 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
of: clean up OF_CONTROL ifdef conditionals We have flipped CONFIG_SPL_DISABLE_OF_CONTROL. We have cleansing devices, $(SPL_) and CONFIG_IS_ENABLED(), so we are ready to clear away the ugly logic in include/fdtdec.h: #ifdef CONFIG_OF_CONTROL # if defined(CONFIG_SPL_BUILD) && !defined(SPL_OF_CONTROL) # define OF_CONTROL 0 # else # define OF_CONTROL 1 # endif #else # define OF_CONTROL 0 #endif Now CONFIG_IS_ENABLED(OF_CONTROL) is the substitute. It refers to CONFIG_OF_CONTROL for U-boot proper and CONFIG_SPL_OF_CONTROL for SPL. Also, we no longer have to cancel CONFIG_OF_CONTROL in include/config_uncmd_spl.h and scripts/Makefile.spl. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> |
#
6e780c7a |
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23-Jun-2015 |
Simon Glass <sjg@chromium.org> |
ns16550: Improve debug UART so it can work with 32-bit access Since Rockchip requires 32-bit serial access, add this to the driver. Refactor a little to make this easier. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
90914008 |
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12-May-2015 |
Simon Glass <sjg@chromium.org> |
dm: ns16550: Support CONFIG_SYS_NS16550_MEM32 with driver model This option is used by some boards, so support it with driver model. This is really ugly - we should rewrite this driver once all users are moved to driver model. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4f60166c |
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24-Apr-2015 |
Axel Lin <axel.lin@ingics.com> |
serial: ns16550: Remove hard-coded baud_divisor setting This was accidentally added by commit dd0b0122bacc "serial: ns16550: Add an option to specify the debug UART register shift". Remove it. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
ab9fd2e8 |
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27-Feb-2015 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Remove unnecessary init on UART setup It is not necessary to write a zero baud rate to the device, and for some chips this will cause problems. Drop this code. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
363e6da1 |
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27-Feb-2015 |
Simon Glass <sjg@chromium.org> |
dm: ns16550: Support non-byte register spacing with driver model Allow this driver to support boards where the register shift is not 0. This fixes some compiler warnings which appear in that case. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
dd0b0122 |
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27-Feb-2015 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Add an option to specify the debug UART register shift This UART permits different register spacing. To support the debug UART on devices which have a spacing other than 1 byte, allow the shift value to be specified. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
0eb25b61 |
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22-Mar-2015 |
Joe Hershberger <joe.hershberger@ni.com> |
common: Make sure arch-specific map_sysmem() is defined In the case where the arch defines a custom map_sysmem(), make sure that including just mapmem.h is sufficient to have these functions as they are when the arch does not override it. Also split the non-arch specific functions out of common.h Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
20379c11 |
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28-Feb-2015 |
Axel Lin <axel.lin@ingics.com> |
serial: ns16550: Fix build error due to a typo Fix trivial typo. Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Axel Lin <axel.lin@ingics.com> |
#
21d00436 |
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26-Jan-2015 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support debug UART Add debug UART functions to permit ns16550 to provide an early debug UART. Try to avoid using the stack so that this can be called from assembler before a stack is set up (at least on ARM and PowerPC). Signed-off-by: Simon Glass <sjg@chromium.org> |
#
76571674 |
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26-Jan-2015 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Add access functions that don't need platdata For the debug UART we need to be able to provide any parameters before driver model is set up. Add parameters to the low-level access functions to make this possible. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
3db886a5 |
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31-Dec-2014 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Support ns16550 compatible pci uart devices There are many pci uart devices which are ns16550 compatible. We can describe them in the board dts file and use it as the U-Boot serial console as specified in the chosen node 'stdout-path' property. Those pci uart devices can have their register be memory-mapped, or i/o-mapped. The driver will try to use the memory-mapped register if the reg property in the node has an entry to describe the memory-mapped register, otherwise i/o-mapped register will be used. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
956a8bae |
|
10-Nov-2014 |
Gregoire Gentil <gregoire@gentil.com> |
ns16550.c: Fix for ns16550 driver hanging on OMAP4 The same problem that is seen on some OMAP3 is also seen on some OMAP4 so include them in the test in order to prevent some hangs during SPL. [trini: Re-word commit message, make apply cleanly] Signed-off-by: Tom Rini <trini@ti.com> |
#
1f77690e |
|
10-Oct-2014 |
Simon Glass <sjg@chromium.org> |
dm: serial: ns16550: Add a cast to the I/O operations This generates a warning when driver model is enabled, so fix it by adding a cast. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
11c1a878 |
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22-Oct-2014 |
Simon Glass <sjg@chromium.org> |
dm: ns16550: Correct the probe logic for platform data The probe logic sets up the pointer to the platform data in the device tree decode method. It should be done in the probe() method, and anyway the device tree decode method can't be used when CONFIG_OF_CONTROL is not enabled. Fix these two problems. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@ti.com> |
#
167efe01 |
|
22-Oct-2014 |
Simon Glass <sjg@chromium.org> |
dm: ns16550: Use an address instead of a pointer for the uart base It is inconvenient to have to use casts when specifying platform data. Also it is not strictly correct, since we should use map_sysmem() to convert an address to a pointer. Adjust the platform data to use an address. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@ti.com> |
#
aea2be20 |
|
22-Oct-2014 |
Simon Glass <sjg@chromium.org> |
dm: serial: ns16550: Correct logic for checking for character There is a bug in the logic which checks for an available character. This can cause invalid characters to be received - this was noticed on beaglebone. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@ti.com> |
#
12e431b2 |
|
04-Sep-2014 |
Simon Glass <sjg@chromium.org> |
dm: serial: Add driver model support for ns16550 Add driver model support so that ns16550 can support operation both with and without driver model. The driver needs a clock frequency so cannot stand alone unfortunately. The clock frequency must be provided by a separate driver. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8bbe33c8 |
|
04-Sep-2014 |
Simon Glass <sjg@chromium.org> |
dm: serial: Collect common baud rate code in ns16550 The same sequence is used in several places, so move it into a function. Note that UART_LCR_BKSE is an alias for UART_LCR_DLAB. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
fa54eb12 |
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04-Sep-2014 |
Simon Glass <sjg@chromium.org> |
dm: serial: Move baud rate calculation to ns16550.c Move the function that calculates the baud rate divisor into ns16550.c so it can be used by that file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8ac22a60 |
|
30-Jul-2014 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
omap: clean-up dead configs The following configs are not defined at all. - CONFIG_OMAP1510 - CONFIG_OMAP_1510P1 - CONFIG_OMAP_SX1 - CONFIG_OMAP3_DMA - CONFIG_OMAP3_ZOOM2 - CONFIG_OMAP_INNOVATOR Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Tom Rini <trini@ti.com> |
#
7c387646 |
|
15-Jul-2014 |
Khoronzhuk, Ivan <ivan.khoronzhuk@ti.com> |
keystone2: use CONFIG_SOC_KEYSTONE in common places Use CONFIG_SOC_KEYSTONE in common places instead of defining a lot of "if def .. || if def " for different Keystone2 SoC types. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> |
#
d57dee57 |
|
09-Apr-2014 |
Karicheri, Muralidharan <m-karicheri2@ti.com> |
serial: nsl16550: add hw flow control support keystone serial hw support hw flow control. This patch enables hw flow control for keystone EVMs as an optional feature based on CONFIG_SERIAL_HW_FLOW_CONTROL. Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> |
#
ef509b90 |
|
04-Apr-2014 |
Vitaly Andrianov <vitalya@ti.com> |
k2hk: add support for k2hk SOC and EVM k2hk EVM is based on Texas Instruments Keystone2 Hawking/Kepler SoC. Keystone2 SoC has ARM v7 Cortex-A15 MPCore processor. Please refer the ti/k2hk_evm/README for details on the board, build and other information. This patch add support for keystone architecture and k2hk evm. Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: WingMan Kwok <w-kwok2@ti.com> Signed-off-by: Sandeep Nair <sandeep_n@ti.com> |
#
456ccfdf |
|
20-Dec-2013 |
Tom Rini <trini@konsulko.com> |
TI:omap3: Drop omap3_zoom2 The omap3_zoom2 board has not been updated for a correct CONFIG_SYS_HZ and Tom Rix's email has long been bouncing. Signed-off-by: Tom Rini <trini@ti.com> |
#
9ed6e412 |
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01-Jul-2013 |
TENART Antoine <atenart@adeneo-embedded.com> |
Prepare for TI816X : reuse existing code from TI814X Rename some CONFIG_TI814X to a more generic CONFIG_TI81XX Signed-off-by: Antoine Tenart <atenart@adeneo-embedded.com> [trini: Adapt for CONFIG_OMAP_COMMON changes, AM43XX] Signed-off-by: Tom Rini <trini@ti.com> |
#
57180408 |
|
30-Jul-2013 |
Lokesh Vutla <lokeshvutla@ti.com> |
ARM: AM43xx: Add build support Add AM43xx support in the required places Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> |
#
7f5eef93 |
|
03-Jun-2013 |
Tom Rini <trini@konsulko.com> |
arm: Remove OMAP2420H4 and all omap24xx support The omap2420H4 was the only mainline omap24xx board. Prior to being fixed by Jon Hunter in time for v2013.04 it had been functionally broken for a very long time. Remove this board as there's not been interest in it in U-Boot for quite a long time. Signed-off-by: Tom Rini <trini@ti.com> |
#
fd2aeac5 |
|
28-Mar-2013 |
Manfred Huber <man.huber@arcor.de> |
omap3_beagle: Flush UART3 xmit on enable if TEMT is broken Flush UART3 xmit on enable if TEMT is broken On some OMAP3 devices when UART3 is configured for boot mode before SPL starts only THRE bit is set. We have to empty the transmitter before initialization starts. This patch avoids the use of CONFIG_SYS_NS16550_BROKEN_TEMT. Signed-off-by: Manfred Huber <man.huber@arcor.de> Tested-by: Javier Martinez Canillas <javier@dowhile0.org> Tested-by: Andreas Bießmann <andreas.devel@googlemail.com> |
#
6213a68f |
|
15-Mar-2013 |
Matt Porter <mporter@ti.com> |
ns16550: enable quirks for ti814x TI814X requires the same quirks as AM33XX to be enabled. Signed-off-by: Matt Porter <mporter@ti.com> Reviewed-by: Tom Rini <trini@ti.com> |
#
69e06832 |
|
05-Mar-2013 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Remove unwanted cast This cast does not seem correct, since we should be writing to a pointer, not a ulong. This fixes the following warning on nds32: -ns16550.c:49: warning: passing argument 2 of 'writeb' makes pointer from integer without a cast Signed-off-by: Simon Glass <sjg@chromium.org> |
#
7de0fe1a |
|
06-Jan-2013 |
Javier Martinez Canillas <javier@dowhile0.org> |
serial/ns16550: add an option to avoid hanging on broken platforms Some platforms (e.g. IGEPv2 board) has a broken ns16550 UART that does not set the TEMT bit when the transmitter is empty in SPL. This makes U-Boot to hang while waiting for TEMT to be set. Add a new option to avoid this: CONFIG_SYS_NS16550_BROKEN_TEMT 16550 UART set the Transmitter Empty (TEMT) Bit when all output has finished and the transmitter is totally empty. U-Boot waits for this bit to be set to initialize the serial console. On some broken platforms this bit is not set in SPL making U-Boot to hang while waiting for TEMT. Define this option to avoid it. Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> |
#
cb55b332 |
|
18-Sep-2012 |
Scott Wood <scottwood@freescale.com> |
serial/ns16550: wait for TEMT before initializing TEMT is set when the transmitter is totally empty and all output has finished. This prevents output problems (including a loss of synchronization observed on p2020 that persisted for quite a while) if SPL has output still on its way out. Signed-off-by: Scott Wood <scottwood@freescale.com> -- v2: fixed typo in subject, and explained what the bit does in the changelog |
#
f2041388 |
|
15-Sep-2012 |
Marek Vasut <marex@denx.de> |
serial: ns16550: Call usbtty_poll only in non-SPL build Having both USBTTY and CONFIG_SERIAL_MULTI enabled in SPL, the usbtty.c file is protected in Makefile to not be compiled into the SPL. Yet, the ns16550 serial driver does not contain such protection. Add it to avoid missing symbol error. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Marek Vasut <marek.vasut@gmail.com> Cc: Tom Rini <trini@ti.com> |
#
99b603e7 |
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09-Jul-2012 |
Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com> |
serial/ns16550: ns16550 has a different register layout on SOC_DA8XX also fix NS16550_init() as we need 16x divider Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com> Acked-by: Christian Riesch <christian.riesch@omicron.at> Tested-by: Christian Riesch <christian.riesch@omicron.at> Acked-by: Sughosh Ganu <urwithsughosh@gmail.com> Tested-by: Sughosh Ganu <urwithsughosh@gmail.com> |
#
5289e83a |
|
13-Oct-2011 |
Chandan Nath <chandan.nath@ti.com> |
ARM:AM33XX: Add support for TI AM335X EVM This patch adds basic support for booting the board. This patch adds support for the UART necessary to get to the u-boot prompt. Signed-off-by: Chandan Nath <chandan.nath@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> |
#
f8df9d0d |
|
15-Oct-2011 |
Simon Glass <sjg@chromium.org> |
NS16550: trivial code clean for checkpatch This removes most checkpatch warnings from the ns16550 driver and its header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
79df1208 |
|
01-Sep-2011 |
Dave Aldridge <fovsoft@gmail.com> |
ns16550: change to allow 32 bit access to registers If CONFIG_SYS_NS16550_MEM32 is defined then 32 bit memory mapped access will be used to read/write the uart registers. This is especially useful for SoC devices that implement 16550 compatible uarts but that have peripheral access width constraints. Signed-off-by: Dave Aldridge <fovsoft@gmail.com> |
#
a160ea0b |
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27-Oct-2010 |
Prafulla Wadaskar <prafulla@marvell.com> |
Serial: ns16550: Add support for CONFIG_SYS_NS16550_IER macro On some processors this ier register configuration is different for ex. Marvell Armada100 This patch introduce CONFIG_SYS_NS16550_IER macro support to unconditionally initialize this register. Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com> |
#
1a2d9b30 |
|
12-Oct-2010 |
Stefan Roese <sr@denx.de> |
ns16550: Add WATCHDOG_RESET to putc for short watchdog timeout boards Call watchdog_reset() upon newline. This is done here in putc since the environment code uses a single puts() to print the complete envrironment upon "printenv". So we can't put this watchdog call in puts(). This is needed for boards with a very short watchdog timeout, like the lwmon5 with a 100ms timeout. Without this patch this board resets in the commands with long outputs, like "printenv" or "fdt print". Note that the image size is not increased with this patch when CONFIG_HW_WATCHDOG or CONFIG_WATCHDOG are not defined since the compiler optimizes this additional code away. Signed-off-by: Stefan Roese <sr@denx.de> Fix typo in comment. Signed-off-by: Wolfgang Denk <wd@denx.de> |
#
167cdad1 |
|
23-Apr-2010 |
Graeme Russ <graeme.russ@gmail.com> |
SERIAL: Enable port-mapped access The x86 architecture exclusively uses Port-Mapped I/O (inb/outb) to access the 16550 UARTs. This patch mimics how Linux selects between Memory-Mapped and Port-Mapped I/O. This allows x86 boards to use CONFIG_SERIAL_MUTLI and drop the custom serial port driver Signed-off-by: Graeme Russ <graeme.russ@gmail.com> |
#
a47a12be |
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15-Apr-2010 |
Stefan Roese <sr@denx.de> |
Move arch/ppc to arch/powerpc As discussed on the list, move "arch/ppc" to "arch/powerpc" to better match the Linux directory structure. Please note that this patch also changes the "ppc" target in MAKEALL to "powerpc" to match this new infrastructure. But "ppc" is kept as an alias for now, to not break compatibility with scripts using this name. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Wolfgang Denk <wd@denx.de> Acked-by: Detlev Zundel <dzu@denx.de> Acked-by: Kim Phillips <kim.phillips@freescale.com> Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Anatolij Gustschin <agust@denx.de> |
#
a1b322a9 |
|
01-Feb-2010 |
Ladislav Michl <ladis@linux-mips.org> |
ns16550: kick watchdog while waiting for a character ns16550 busyloops waiting for incoming byte causing watchdog to reboot while waiting for a key press. A call to WATCHDOG_RESET in NS16550_getc loop fixes it. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> |
#
660888b7 |
|
30-May-2009 |
Tom Rix <Tom.Rix@windriver.com> |
ZOOM2 Add serial support. Zoom2 serial is in general supplied by one of the 4 UARTS on the debug board. The default serial is from the USB connector on left side of the debug board. The USB connector will produce 2 of the 4 UARTS. On your host pick the first enumeration. The details of the setting of the serial gpmc setup are not available. The values were provided by another party. The serial port set up is the same with Zoom1. Baud rate 115200, 8 bit data, no parity, 1 stop bit, no flow. The kernel bootargs are console=ttyS3,115200n8 Signed-off-by: Tom Rix <Tom.Rix@windriver.com> |
#
200779e3 |
|
03-Apr-2009 |
Detlev Zundel <dzu@denx.de> |
Rename common ns16550 constants with UART_ prefix to prevent conflicts Fix problems introduced in commit 7b5611cdd12ca0cc33f994f0d4a4454788fc3124 [inka4x0: Add hardware diagnosis functions for inka4x0] which redefined MSR_RI which is already used on PowerPC systems. Also eliminate redundant definitions in ps2mult.h. More cleanup will be needed for other redundant occurrences though. Signed-off-by: Detlev Zundel <dzu@denx.de> |
#
b4746d8b |
|
11-Feb-2009 |
Mike Frysinger <vapier@gentoo.org> |
drivers/serial/ns16550: move ifdef into Makefile COBJS-$(...) Signed-off-by: Mike Frysinger <vapier@gentoo.org> |
#
f5675aa5 |
|
18-Feb-2009 |
Ron Madrid <ron_madrid@sbcglobal.net> |
Create configuration option for restricted ns16550 functions This patch will create a configuration option for a minimum configuration for the ns16550 serial driver at drivers/serial/ns16550.c and will apply this new configuration option to the SIMPC8313.h config file in order to fix the NAND bootstrap build error. This option will exclude all functions with exception of NS16550_putc and NS16550_init. This will be used primarily to save space and remove unused code from builds in which space is limited. Signed-off-by: Ron Madrid <ron_madrid@sbcglobal.net> |
#
6d0f6bcf |
|
16-Oct-2008 |
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
rename CFG_ macros to CONFIG_SYS Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
#
7ec8bb15 |
|
27-Dec-2007 |
Wolfgang Denk <wd@denx.de> |
OMAP5912: fix FIFO handling in UART driver According to the OMAP5912 Serial Interfaces Reference Guide (see http://focus.ti.com/lit/ug/spru760c/spru760c.pdf, page 150), the FIFO_EN enable bit in the FIFO Control Register (FCR) can only be changed when the baud clock is not running, i. e. when both DLL and DLH are set to 0. Thus make sure that DLL and DLH are 0 when writing the FCR. Signed-off-by: Wolfgang Denk <wd@denx.de> |
#
1378df79 |
|
24-Nov-2007 |
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
drivers/serial : move serial drivers to drivers/serial Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
#
5e998b4d |
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23-Jun-2022 |
Pali Rohár <pali@kernel.org> |
serial: ns16550: Wait in debug_uart_init until tx buffer is empty Commit d293759d55cc ("serial: ns16550: Add support for SPL_DEBUG_UART_BASE") fixed support for setting correct early debug UART base address in SPL. But after this commit, output from Marvell A385 BootROM is truncated or lost and not fully present on serial console. Debugging this issue showed that BootROM just put bytes into UART HW output buffer and does not wait until UART HW transmit all characters. U-Boot ns16550 early debug is initialized very early and during its initialization is resetting UART HW and flushing remaining transmit buffer (which still contains BootROM output). Fix this issue by waiting in init function prior resetting UART HW until TxEmpty bit in UART Line Status Register is set. TxEmpty is set when all remaining bytes from HW buffer are transmitted. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> [trini: Add comment, move ';' to new line per checkpatch.pl] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
d293759d |
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06-May-2022 |
Pali Rohár <pali@kernel.org> |
serial: ns16550: Add support for SPL_DEBUG_UART_BASE Use CONFIG_VAL(DEBUG_UART_BASE) instead of CONFIG_DEBUG_UART_BASE, so proper config value (CONFIG_DEBUG_UART_BASE or CONFIG_SPL_DEBUG_UART_BASE) is used based on building target. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
04ee76c9 |
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09-Apr-2022 |
Johan Jonker <jbx6244@gmail.com> |
rockchip: serial: move driver alias to serial_rockchip.c The Rockchip uart DT nodes have "snps,dw-apb-uart" as fall back string. The driver ns16550.c has CONFIG_IS_ENABLED(OF_REAL) as condition to of_match and does not copy dtplat data. For TPL/SPL the driver serial_rockchip.c is used. Move driver alias to correct driver. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
f899cc14 |
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12-Sep-2021 |
Tom Rini <trini@konsulko.com> |
ti: keystone: Move away from CONFIG_SOC_KEYSTONE We have individual SOC symbols for each keystone 2 platform. Use the existing CONFIG_ARCH_KEYSTONE rather than CONFIG_SOC_KEYSTONE to encompass all of the keystone families. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
414cc151 |
|
07-Aug-2021 |
Simon Glass <sjg@chromium.org> |
treewide: Simply conditions with the new OF_REAL Use this new Kconfig to simplify the compilation conditions where appropriate. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
384b62c0 |
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03-Feb-2021 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Handle zero <clock-frequency> value A working device tree node of ns16550 should never be populated with value zero for the <clock-frequency> property. Unfortunately this is the case for the QEMU ppce500 target. Let's try to assign plat->clock to CONFIG_SYS_NS16550_CLK as the last resort to handle such case. This commit should be reverted when: - The following QEMU patch [1] is merged, and - U-Boot CI has upgraded its QEMU version that contains the fix [1] http://patchwork.ozlabs.org/project/qemu-devel/patch/1612362288-22216-2-git-send-email-bmeng.cn@gmail.com/ Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
09bd0840 |
|
03-Feb-2021 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Correct the base address type Currently ns16550_serial_assign_base() treats the argument 'base' with type `ulong`. This is incorrect because the base address was obtained from device tree with type `fdt_addr_t` that can represent a physical address larger than 32-bit in a 32-bit system. Fixes: 9e6ce62190b7 ("serial: ns16550: Fix ordering of getting base address") Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
401d1c4f |
|
30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
bdf8fd76 |
|
28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
0fd3d911 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com> |
#
2d6bf754 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
#
d30c7209 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo |
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de> |
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> |
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se> |
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> |
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com |
#
9ad3b049 |
|
02-Nov-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: add setconfig support Add possibility to update the serial parity used. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com> |
#
46879196 |
|
24-Oct-2018 |
Bin Meng <bmeng.cn@gmail.com> |
serial: Remove DM_FLAG_PRE_RELOC flag in various drivers When a driver declares DM_FLAG_PRE_RELOC flag, it wishes to be bound before relocation. However due to a bug in the DM core, the flag only takes effect when devices are statically declared via U_BOOT_DEVICE(). This bug has been fixed recently by commit "dm: core: Respect drivers with the DM_FLAG_PRE_RELOC flag in lists_bind_fdt()", but with the fix, it has a side effect that all existing drivers that declared DM_FLAG_PRE_RELOC flag will be bound before relocation now. This may expose potential boot failure on some boards due to insufficient memory during the pre-relocation stage. To mitigate this potential impact, the following changes are implemented: - Remove DM_FLAG_PRE_RELOC flag in the driver, if the driver only supports configuration from device tree (OF_CONTROL) - Keep DM_FLAG_PRE_RELOC flag in the driver only if the device is statically declared via U_BOOT_DEVICE() - Surround DM_FLAG_PRE_RELOC flag with OF_CONTROL check, for drivers that support both statically declared devices and configuration from device tree Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
6f57c344 |
|
09-Aug-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), let's rather ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
5d754197 |
|
27-Aug-2018 |
Lokesh Vutla <lokeshvutla@ti.com> |
serial: omap: Introduce DM specific omap serial Add driver model support for OMAP_SERIAL while reusing the functions in ns16550.c Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Tested-by: Derald D. Woods <woods.technical@gmail.com> |
#
b051eecb |
|
14-Jun-2018 |
Ley Foon Tan <ley.foon.tan@intel.com> |
serial: ns16550: Add reset ctrl to driver Add code to reset all reset signals as in serial DT node. A reset property is an optional feature, so do not fail if a reset property is not present. If a reset property is discovered, then use it to deassert, thus bringing the IP out of reset. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
78b7d37b |
|
15-Feb-2018 |
Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> |
ns16550: Fix mem mapped endian check Do a explicit check for CONFIG_SYS_BIG_ENDIAN and CONFIG_SYS_LITTLE_ENDIAN to avoid errors on platforms where both are undefined (x86). Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> Reviewed-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com> |
#
4dbf9bed |
|
15-Jan-2018 |
Mario Six <mario.six@gdsys.cc> |
serial: ns16550: Fix style violation Clarify the computation precedence in two ternary operator constructions. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc> |
#
7fded0ce |
|
16-Aug-2017 |
Stefan Roese <sr@denx.de> |
Revert "serial: ns16550: Add RX interrupt buffer support" This reverts commit 6822cf3ec7c8768b8727573b8f4b2cb3d870b881. As Bin Meng has tested and pointed out, we don't need the RX interrupt for the RX buffer support at all. Just reading all available characters into a buffer is sufficient to solve the problem with the dropped characters upon long lines pasted into the U-Boot prompt. Since this RX buffer support can be implemented in a generic way, without any device specifica (e.g. for the ns16550), I'll post a new patch with a new serial RX buffer support for DM, which all DM based serial drivers can use. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
6822cf3e |
|
14-Jul-2017 |
Stefan Roese <sr@denx.de> |
serial: ns16550: Add RX interrupt buffer support Pasting longer lines into the U-Boot console prompt sometimes leads to characters missing. One problem here is the small 16-byte FIFO of the legacy NS16550 UART, e.g. on x86 platforms. This patch now introduces a Kconfig option to enable RX interrupt buffer support for NS16550 style UARTs. With this option enabled, I was able paste really long lines into the U-Boot console, without any characters missing. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> [trini: Guard ns16550_serial_remove with CONFIG_IS_ENABLED(SERIAL_PRESENT) to match struct assignment] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
8d3a2568 |
|
11-Jul-2017 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-dm
|
#
db9f8f6a |
|
12-Jun-2017 |
Simon Glass <sjg@chromium.org> |
dm: serial: ns16550: Convert to livetree Update this driver to support a live device tree. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Tested-on: Beaver, Jetson-TK1 |
#
3d40479f |
|
07-Jun-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
rockchip: ns16550: dm: convert fdt_get to dev_read With the new dev_read functions available, we can convert the rockchip architecture-specific drivers and common drivers used by these devices over to the dev_read family of calls. This covers the serial driver (ns16550 and compatible) used for the Rockchip devices. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
a821c4af |
|
17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: Rename dev_addr..() functions These support the flat device tree. We want to use the dev_read_..() prefix for functions that support both flat tree and live tree. So rename the existing functions to avoid confusion. In the end we will have: 1. dev_read_addr...() - works on devices, supports flat/live tree 2. devfdt_get_addr...() - current functions, flat tree only 3. of_get_address() etc. - new functions, live tree only All drivers will be written to use 1. That function will in turn call either 2 or 3 depending on whether the flat or live tree is in use. Note this involves changing some dead code - the imx_lpi2c.c file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
89024ddc |
|
12-May-2017 |
Tom Rini <trini@konsulko.com> |
TI: Drop 'CONFIG_OMAP' In the two cases in the code where we use CONFIG_OMAP as a useful test currently we can make use of CONFIG_ARCH_OMAP2PLUS instead. With that changed we can drop all defines of CONFIG_OMAP. While in here, CONFIG_OMAP3430 is only defined and then never used, so drop. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
a52cf086 |
|
22-Apr-2017 |
Lokesh Vutla <lokeshvutla@ti.com> |
serial: omap: Support debug UART Add debug UART functions to permit omap specific ns16550 to provide an early debug UART. This is mostly in common with DEBUG_UART_NS16550 except for Mode definition register which is required for selecting UART mode(16x auto-baud or 13x mode). Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
6f8c351e |
|
27-Mar-2017 |
Alexandru Gagniuc <alex.g@adaptrum.com> |
serial: ns16550: Link in the DM driver when when using platdata Do not condition the compilation of the U_BOOT_DRIVER by !OF_PLATDATA. This is inconsistent with the majority of other drivers. This also blocks OF_PLATDATA boards with an 16550-compatible serial from using serial in SPL. Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com> Reviewed-by: Simon Glass <sjg@chromium.org> Added tweak for rock to avoid a TPL build failure: Signed-off-by: Simon Glass <sjg@chromium.org> |
#
e160f7d4 |
|
17-Jan-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
17fa0326 |
|
18-Jan-2017 |
Heiko Schocher <hs@denx.de> |
serial, ns16550: bugfix: ns16550 fifo not enabled commit: 65f83802b7a5b "serial: 16550: Add getfcr accessor" breaks u-boot commandline working with long commands sending to the board. Since the above patch, you have to setup the fcr register. For board/archs which enable OF_PLATDATA, the new field fcr in struct ns16550_platdata is not filled with a default value ... This leads in not setting up the uarts fifo, which ends in problems, when you send long commands to u-boots commandline. Detected this issue with automated tbot tests on am335x based shc board. The error does not popup, if you type commands. You need to copy&paste a long command to u-boots commandshell (or send a long command with tbot) Possible boards/plattforms with problems: ./arch/arm/cpu/arm926ejs/lpc32xx/devices.c ./arch/arm/mach-tegra/board.c ./board/overo/overo.c ./board/quipos/cairo/cairo.c ./board/logicpd/omap3som/omap3logic.c ./board/logicpd/zoom1/zoom1.c ./board/timll/devkit8000/devkit8000.c ./board/lg/sniper/sniper.c ./board/ti/beagle/beagle.c ./drivers/serial/serial_rockchip.c Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Tested-by: Adam Ford <aford173@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
0b060eef |
|
30-Nov-2016 |
Marek Vasut <marex@denx.de> |
serial: 16550: Add Ingenic JZ4780 support Add compatibility string for the Ingenic JZ4780 SoC, the necessary UART enable bit into FCR and register shift. Neither are encoded in the DTS coming from Linux, so we need to support it this way. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
79fd9281 |
|
30-Nov-2016 |
Marek Vasut <marex@denx.de> |
serial: 16550: Add port type as driver data Add driver data to each compatible string to identify the type of the port. Since all the ports in the driver are entirely compatible with 16550 for now, all are marked with PORT_NS16550. But, there are ports which have specific quirks, like the JZ4780 UART, which do not have any DT property to denote the quirks. Instead, Linux uses the compatible string to discern such ports and enable the necessary quirks. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> |
#
65f83802 |
|
30-Nov-2016 |
Marek Vasut <marex@denx.de> |
serial: 16550: Add getfcr accessor Add function which allows fetching the default FCR register setting from platform data for DM , while retaining old behavior for non-DM by returning UART_FCRVAL. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
021abf69 |
|
26-Sep-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
Revert "ns16650: Make sure we have CONFIG_CLK set before using infrastructure" This reverts commit 82f5279b0cd99a9163d34cfe926d0316d9dc0d37. The build failure of k2*evm boards was fixed in a different way by the previous commit. It is nasty to patch generic drivers around with #ifdef CONFIG_CLK just for the KeyStone's matter. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
ab895d6a |
|
30-Sep-2016 |
Alexandre Courbot <acourbot@nvidia.com> |
serial: ns16550: Handle -ENOENT when requesting clock When calling clk_get_by_index(), fall back to the legacy method of getting the clock if -ENOENT is returned. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> |
#
82f5279b |
|
22-Sep-2016 |
Tom Rini <trini@konsulko.com> |
ns16650: Make sure we have CONFIG_CLK set before using infrastructure We cannot call on the CONFIG_CLK based clk_get_rate function unless CONFIG_CLK is set. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
50fce1d5 |
|
08-Sep-2016 |
Paul Burton <paul.burton@mips.com> |
serial: ns16550: Support clocks via phandle Previously ns16550 compatible UARTs probed via device tree have needed their device tree nodes to contain a clock-frequency property. An alternative to this commonly used with Linux is to reference a clock via a phandle. This patch allows U-Boot to support that, retrieving the clock frequency by probing the appropriate clock device. For example, a system might choose to provide the UART base clock as a reference to a clock common to multiple devices: sys_clk: clock { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <10000000>; }; uart0: uart@10000000 { compatible = "ns16550a"; reg = <0x10000000 0x1000>; clocks = <&sys_clk>; }; uart1: uart@10000000 { compatible = "ns16550a"; reg = <0x10001000 0x1000>; clocks = <&sys_clk>; }; This removes the need for the frequency information to be duplicated in multiple nodes and allows the device tree to be more descriptive of the system. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
b2927fba |
|
04-Jul-2016 |
Simon Glass <sjg@chromium.org> |
dm: serial: ns16550: Update to support of-platdata With of-platdata this driver cannot know the format of the of-platdata struct, so we cannot use generic code for accessing the of-platdata. Each SoC that uses this driver will need to set up ns16550's platdata for it. So don't compile in the generic code. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
03c6f176 |
|
24-May-2016 |
Marek Vasut <marex@denx.de> |
serial: 16550: Drop OMAP1510 support The CONFIG_OMAP1510 is no longer defined, so remove this dead code. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Nishanth Menon <nm@ti.com> |
#
fa4ce723 |
|
24-May-2016 |
Marek Vasut <marex@denx.de> |
serial: 16550: Make serial_io/out_shift available to debug mode The ns16550 driver needs serial_in_shift() and serial_out_shift() when compiled in debug UART mode, so shift the DM_SERIAL check a little to make these functions available. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
df8ec55d |
|
17-May-2016 |
Paul Burton <paul.burton@mips.com> |
dm: ns16550: Don't map_physmem for I/O ports If the UART is to be accessed using I/O port accessors (inb & outb) then using map_physmem doesn't make sense, since it operates in a different memory space. Remove the call to map_physmem when CONFIG_SYS_NS16550_PORT_MAPPED is defined, allowing I/O port addresses to not be mangled by the incorrect mapping. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> |
#
59b35ddd |
|
16-Feb-2016 |
Michal Simek <michal.simek@amd.com> |
dm: ns16550: Add support for reg-offset property reg-offset is the part of standard 8250 binding in the kernel. It is shifting start of address space by reg-offset. On Xilinx platform this offset is typically 0x1000. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Moved the new field to the end of the struct to avoid problems: Signed-off-by: Simon Glass <sjg@chromium.org> |
#
e5e88c65 |
|
29-Feb-2016 |
Tom Rini <trini@konsulko.com> |
Revert "dm: ns16550: Add support for reg-offset property" This reverts commit d9a3bec682f9756621615f4306718a356a3230e3. While this is a correct change to do long term it unfortunately breaks a number of platforms that are using pdata and not named struct members so they are getting all of their data after 'base' incorrect. Acked-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
d9a3bec6 |
|
16-Feb-2016 |
Michal Simek <michal.simek@amd.com> |
dm: ns16550: Add support for reg-offset property reg-offset is the part of standard 8250 binding in the kernel. It is shifting start of address space by reg-offset. On Xilinx platform this offset is typically 0x1000. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
cc4228f9 |
|
14-Dec-2015 |
Thomas Chou <thomas@wytron.com.tw> |
ns16550: zap the rockchip serial compatible string Zap the rockchip serial compatible string, because rockchip serial has "snps,dw-apb-uart" compatible string in the dts. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org> |
#
b7e29834 |
|
13-Dec-2015 |
Simon Glass <sjg@chromium.org> |
dm: ns16550: Allow the driver to be omitted if requested Allow the ns16550 debug UART to be used without the full driver. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Thomas Chou <thomas@wytron.com.tw> |
#
fcc0a877 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: serial: Convert ns16550 driver to use driver model PCI API Use the driver model version of the function to find the BAR. This updates the fdtdec function, of which ns16550 is the only user. The fdtdec_get_pci_bdf() function is dropped for several reasons: - with driver model we should use 'struct udevice *' rather than passing the device tree offset explicitly - there are no other users in the tree - the function parses for information which is already available in the PCI device structure (specifically struct pci_child_platdata which is available at dev_get_parent_platdata(dev) Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> |
#
b7e5a643 |
|
04-Dec-2015 |
Simon Glass <sjg@chromium.org> |
dm: serial: ns16550: Add pre-reloc flag to the driver For platforms that don't use device tree in SPL the only way to mark this driver as 'required by relocation' is with the DM_FLAG_PRE_RELOC flag. Add this to ensure that the driver is bound. Fixes: fde7e18938d8 ("dm: tegra: pci: Move CONFIG_PCI_TEGRA to Kconfig") Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Stephen Warren <swarren@nvidia.com> Acked-by: Thomas Chou <thomas@wytron.com.tw> |
#
80e06146 |
|
28-Nov-2015 |
Thomas Chou <thomas@wytron.com.tw> |
ns16550: change reg-shift property default to zero Change reg-shift property default to zero. When the integer property is missing, it should be taken as zero. This is consistent to Linux drivers/tty/serial/of_serial.c. The x86 and most powerpc use reg-shift of 0. Most others use reg-shift of 2. While reg-shift of 1 is rarely used. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
a51dbebf |
|
16-Nov-2015 |
huang lin <hl@rock-chips.com> |
rockchip: serial driver support rk3036 Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
4fb60552 |
|
19-Nov-2015 |
Thomas Chou <thomas@wytron.com.tw> |
ns16550: zap CONFIG_NS16550_SERIAL Zap CONFIG_NS16550_SERIAL, as the unification of ns16550 drivers is completed. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
8e62d32e |
|
19-Nov-2015 |
Thomas Chou <thomas@wytron.com.tw> |
ns16550: add generic binding to unify the drivers Add generic binding to unify ns16550 drivers. There are several drivers using almost the same code, such as serial_dw, serial_keystone, serial_omap, serial_ppc, serial_rockchip, serial_tegra.c, and serial_x86. But each is platform specific. The key difference between these drivers is the way to get input clock frequency. With this unified approach, fixed clock frequency should be extracted from "clock-frequency" property of device tree blob. If this property is not available, the macro CONFIG_SYS_NS16550_CLK will be used. It can be a constant or a function to get clock, eg, get_serial_clock(). Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de> Acked-by: Simon Glass <sjg@chromium.org> |
#
77d7b5cd |
|
19-Nov-2015 |
Thomas Chou <thomas@wytron.com.tw> |
ns16550: change map_sysmem to map_physmem Change map_sysmem() to map_physmem(,,MAP_NOCACHE). Though map_sysmem() can be used to map system memory, it might be wrong to use it for I/O ports. The map_physmem() serves the same purpose to translate physical address to virtual address with the additional flag to take care of cache property. Most drivers use map_physmem() since I/O ports access should be uncached. As ns16550 is a driver, it should use map_physmem() rather than map_sysmem(). Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org> |
#
97b05973 |
|
18-Oct-2015 |
Simon Glass <sjg@chromium.org> |
debug_uart: Adjust the declaration of debug_uart_init() We want to be able to add other common code to this function. So change the driver's version to have an underscore before it, just like _debug_uart_putc(). Define debug_uart_init() to call this version. Update all drivers to this new method. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
4e9838c1 |
|
11-Aug-2015 |
Simon Glass <sjg@chromium.org> |
dm: Use dev_get_addr() where possible This is a convenient way for a driver to get the hardware address of a device, when regmap or syscon are not being used. Change existing callers to use it as an example to others. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> |
#
0f925822 |
|
11-Aug-2015 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
of: clean up OF_CONTROL ifdef conditionals We have flipped CONFIG_SPL_DISABLE_OF_CONTROL. We have cleansing devices, $(SPL_) and CONFIG_IS_ENABLED(), so we are ready to clear away the ugly logic in include/fdtdec.h: #ifdef CONFIG_OF_CONTROL # if defined(CONFIG_SPL_BUILD) && !defined(SPL_OF_CONTROL) # define OF_CONTROL 0 # else # define OF_CONTROL 1 # endif #else # define OF_CONTROL 0 #endif Now CONFIG_IS_ENABLED(OF_CONTROL) is the substitute. It refers to CONFIG_OF_CONTROL for U-boot proper and CONFIG_SPL_OF_CONTROL for SPL. Also, we no longer have to cancel CONFIG_OF_CONTROL in include/config_uncmd_spl.h and scripts/Makefile.spl. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> |
#
6e780c7a |
|
23-Jun-2015 |
Simon Glass <sjg@chromium.org> |
ns16550: Improve debug UART so it can work with 32-bit access Since Rockchip requires 32-bit serial access, add this to the driver. Refactor a little to make this easier. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
90914008 |
|
12-May-2015 |
Simon Glass <sjg@chromium.org> |
dm: ns16550: Support CONFIG_SYS_NS16550_MEM32 with driver model This option is used by some boards, so support it with driver model. This is really ugly - we should rewrite this driver once all users are moved to driver model. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4f60166c |
|
24-Apr-2015 |
Axel Lin <axel.lin@ingics.com> |
serial: ns16550: Remove hard-coded baud_divisor setting This was accidentally added by commit dd0b0122bacc "serial: ns16550: Add an option to specify the debug UART register shift". Remove it. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
ab9fd2e8 |
|
27-Feb-2015 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Remove unnecessary init on UART setup It is not necessary to write a zero baud rate to the device, and for some chips this will cause problems. Drop this code. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
363e6da1 |
|
27-Feb-2015 |
Simon Glass <sjg@chromium.org> |
dm: ns16550: Support non-byte register spacing with driver model Allow this driver to support boards where the register shift is not 0. This fixes some compiler warnings which appear in that case. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
dd0b0122 |
|
27-Feb-2015 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Add an option to specify the debug UART register shift This UART permits different register spacing. To support the debug UART on devices which have a spacing other than 1 byte, allow the shift value to be specified. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
0eb25b61 |
|
22-Mar-2015 |
Joe Hershberger <joe.hershberger@ni.com> |
common: Make sure arch-specific map_sysmem() is defined In the case where the arch defines a custom map_sysmem(), make sure that including just mapmem.h is sufficient to have these functions as they are when the arch does not override it. Also split the non-arch specific functions out of common.h Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
20379c11 |
|
28-Feb-2015 |
Axel Lin <axel.lin@ingics.com> |
serial: ns16550: Fix build error due to a typo Fix trivial typo. Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Axel Lin <axel.lin@ingics.com> |
#
21d00436 |
|
26-Jan-2015 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support debug UART Add debug UART functions to permit ns16550 to provide an early debug UART. Try to avoid using the stack so that this can be called from assembler before a stack is set up (at least on ARM and PowerPC). Signed-off-by: Simon Glass <sjg@chromium.org> |
#
76571674 |
|
26-Jan-2015 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Add access functions that don't need platdata For the debug UART we need to be able to provide any parameters before driver model is set up. Add parameters to the low-level access functions to make this possible. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
3db886a5 |
|
31-Dec-2014 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Support ns16550 compatible pci uart devices There are many pci uart devices which are ns16550 compatible. We can describe them in the board dts file and use it as the U-Boot serial console as specified in the chosen node 'stdout-path' property. Those pci uart devices can have their register be memory-mapped, or i/o-mapped. The driver will try to use the memory-mapped register if the reg property in the node has an entry to describe the memory-mapped register, otherwise i/o-mapped register will be used. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
956a8bae |
|
10-Nov-2014 |
Gregoire Gentil <gregoire@gentil.com> |
ns16550.c: Fix for ns16550 driver hanging on OMAP4 The same problem that is seen on some OMAP3 is also seen on some OMAP4 so include them in the test in order to prevent some hangs during SPL. [trini: Re-word commit message, make apply cleanly] Signed-off-by: Tom Rini <trini@ti.com> |
#
1f77690e |
|
10-Oct-2014 |
Simon Glass <sjg@chromium.org> |
dm: serial: ns16550: Add a cast to the I/O operations This generates a warning when driver model is enabled, so fix it by adding a cast. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
11c1a878 |
|
22-Oct-2014 |
Simon Glass <sjg@chromium.org> |
dm: ns16550: Correct the probe logic for platform data The probe logic sets up the pointer to the platform data in the device tree decode method. It should be done in the probe() method, and anyway the device tree decode method can't be used when CONFIG_OF_CONTROL is not enabled. Fix these two problems. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@ti.com> |
#
167efe01 |
|
22-Oct-2014 |
Simon Glass <sjg@chromium.org> |
dm: ns16550: Use an address instead of a pointer for the uart base It is inconvenient to have to use casts when specifying platform data. Also it is not strictly correct, since we should use map_sysmem() to convert an address to a pointer. Adjust the platform data to use an address. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@ti.com> |
#
aea2be20 |
|
22-Oct-2014 |
Simon Glass <sjg@chromium.org> |
dm: serial: ns16550: Correct logic for checking for character There is a bug in the logic which checks for an available character. This can cause invalid characters to be received - this was noticed on beaglebone. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@ti.com> |
#
12e431b2 |
|
04-Sep-2014 |
Simon Glass <sjg@chromium.org> |
dm: serial: Add driver model support for ns16550 Add driver model support so that ns16550 can support operation both with and without driver model. The driver needs a clock frequency so cannot stand alone unfortunately. The clock frequency must be provided by a separate driver. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8bbe33c8 |
|
04-Sep-2014 |
Simon Glass <sjg@chromium.org> |
dm: serial: Collect common baud rate code in ns16550 The same sequence is used in several places, so move it into a function. Note that UART_LCR_BKSE is an alias for UART_LCR_DLAB. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
fa54eb12 |
|
04-Sep-2014 |
Simon Glass <sjg@chromium.org> |
dm: serial: Move baud rate calculation to ns16550.c Move the function that calculates the baud rate divisor into ns16550.c so it can be used by that file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8ac22a60 |
|
30-Jul-2014 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
omap: clean-up dead configs The following configs are not defined at all. - CONFIG_OMAP1510 - CONFIG_OMAP_1510P1 - CONFIG_OMAP_SX1 - CONFIG_OMAP3_DMA - CONFIG_OMAP3_ZOOM2 - CONFIG_OMAP_INNOVATOR Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Tom Rini <trini@ti.com> |
#
7c387646 |
|
15-Jul-2014 |
Khoronzhuk, Ivan <ivan.khoronzhuk@ti.com> |
keystone2: use CONFIG_SOC_KEYSTONE in common places Use CONFIG_SOC_KEYSTONE in common places instead of defining a lot of "if def .. || if def " for different Keystone2 SoC types. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> |
#
d57dee57 |
|
09-Apr-2014 |
Karicheri, Muralidharan <m-karicheri2@ti.com> |
serial: nsl16550: add hw flow control support keystone serial hw support hw flow control. This patch enables hw flow control for keystone EVMs as an optional feature based on CONFIG_SERIAL_HW_FLOW_CONTROL. Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> |
#
ef509b90 |
|
04-Apr-2014 |
Vitaly Andrianov <vitalya@ti.com> |
k2hk: add support for k2hk SOC and EVM k2hk EVM is based on Texas Instruments Keystone2 Hawking/Kepler SoC. Keystone2 SoC has ARM v7 Cortex-A15 MPCore processor. Please refer the ti/k2hk_evm/README for details on the board, build and other information. This patch add support for keystone architecture and k2hk evm. Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: WingMan Kwok <w-kwok2@ti.com> Signed-off-by: Sandeep Nair <sandeep_n@ti.com> |
#
456ccfdf |
|
20-Dec-2013 |
Tom Rini <trini@konsulko.com> |
TI:omap3: Drop omap3_zoom2 The omap3_zoom2 board has not been updated for a correct CONFIG_SYS_HZ and Tom Rix's email has long been bouncing. Signed-off-by: Tom Rini <trini@ti.com> |
#
9ed6e412 |
|
01-Jul-2013 |
TENART Antoine <atenart@adeneo-embedded.com> |
Prepare for TI816X : reuse existing code from TI814X Rename some CONFIG_TI814X to a more generic CONFIG_TI81XX Signed-off-by: Antoine Tenart <atenart@adeneo-embedded.com> [trini: Adapt for CONFIG_OMAP_COMMON changes, AM43XX] Signed-off-by: Tom Rini <trini@ti.com> |
#
57180408 |
|
30-Jul-2013 |
Lokesh Vutla <lokeshvutla@ti.com> |
ARM: AM43xx: Add build support Add AM43xx support in the required places Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> |
#
7f5eef93 |
|
03-Jun-2013 |
Tom Rini <trini@konsulko.com> |
arm: Remove OMAP2420H4 and all omap24xx support The omap2420H4 was the only mainline omap24xx board. Prior to being fixed by Jon Hunter in time for v2013.04 it had been functionally broken for a very long time. Remove this board as there's not been interest in it in U-Boot for quite a long time. Signed-off-by: Tom Rini <trini@ti.com> |
#
fd2aeac5 |
|
28-Mar-2013 |
Manfred Huber <man.huber@arcor.de> |
omap3_beagle: Flush UART3 xmit on enable if TEMT is broken Flush UART3 xmit on enable if TEMT is broken On some OMAP3 devices when UART3 is configured for boot mode before SPL starts only THRE bit is set. We have to empty the transmitter before initialization starts. This patch avoids the use of CONFIG_SYS_NS16550_BROKEN_TEMT. Signed-off-by: Manfred Huber <man.huber@arcor.de> Tested-by: Javier Martinez Canillas <javier@dowhile0.org> Tested-by: Andreas Bießmann <andreas.devel@googlemail.com> |
#
6213a68f |
|
15-Mar-2013 |
Matt Porter <mporter@ti.com> |
ns16550: enable quirks for ti814x TI814X requires the same quirks as AM33XX to be enabled. Signed-off-by: Matt Porter <mporter@ti.com> Reviewed-by: Tom Rini <trini@ti.com> |
#
69e06832 |
|
05-Mar-2013 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Remove unwanted cast This cast does not seem correct, since we should be writing to a pointer, not a ulong. This fixes the following warning on nds32: -ns16550.c:49: warning: passing argument 2 of 'writeb' makes pointer from integer without a cast Signed-off-by: Simon Glass <sjg@chromium.org> |
#
7de0fe1a |
|
06-Jan-2013 |
Javier Martinez Canillas <javier@dowhile0.org> |
serial/ns16550: add an option to avoid hanging on broken platforms Some platforms (e.g. IGEPv2 board) has a broken ns16550 UART that does not set the TEMT bit when the transmitter is empty in SPL. This makes U-Boot to hang while waiting for TEMT to be set. Add a new option to avoid this: CONFIG_SYS_NS16550_BROKEN_TEMT 16550 UART set the Transmitter Empty (TEMT) Bit when all output has finished and the transmitter is totally empty. U-Boot waits for this bit to be set to initialize the serial console. On some broken platforms this bit is not set in SPL making U-Boot to hang while waiting for TEMT. Define this option to avoid it. Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> |
#
cb55b332 |
|
18-Sep-2012 |
Scott Wood <scottwood@freescale.com> |
serial/ns16550: wait for TEMT before initializing TEMT is set when the transmitter is totally empty and all output has finished. This prevents output problems (including a loss of synchronization observed on p2020 that persisted for quite a while) if SPL has output still on its way out. Signed-off-by: Scott Wood <scottwood@freescale.com> -- v2: fixed typo in subject, and explained what the bit does in the changelog |
#
f2041388 |
|
15-Sep-2012 |
Marek Vasut <marex@denx.de> |
serial: ns16550: Call usbtty_poll only in non-SPL build Having both USBTTY and CONFIG_SERIAL_MULTI enabled in SPL, the usbtty.c file is protected in Makefile to not be compiled into the SPL. Yet, the ns16550 serial driver does not contain such protection. Add it to avoid missing symbol error. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Marek Vasut <marek.vasut@gmail.com> Cc: Tom Rini <trini@ti.com> |
#
99b603e7 |
|
09-Jul-2012 |
Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com> |
serial/ns16550: ns16550 has a different register layout on SOC_DA8XX also fix NS16550_init() as we need 16x divider Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com> Acked-by: Christian Riesch <christian.riesch@omicron.at> Tested-by: Christian Riesch <christian.riesch@omicron.at> Acked-by: Sughosh Ganu <urwithsughosh@gmail.com> Tested-by: Sughosh Ganu <urwithsughosh@gmail.com> |
#
5289e83a |
|
13-Oct-2011 |
Chandan Nath <chandan.nath@ti.com> |
ARM:AM33XX: Add support for TI AM335X EVM This patch adds basic support for booting the board. This patch adds support for the UART necessary to get to the u-boot prompt. Signed-off-by: Chandan Nath <chandan.nath@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> |
#
f8df9d0d |
|
15-Oct-2011 |
Simon Glass <sjg@chromium.org> |
NS16550: trivial code clean for checkpatch This removes most checkpatch warnings from the ns16550 driver and its header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
79df1208 |
|
01-Sep-2011 |
Dave Aldridge <fovsoft@gmail.com> |
ns16550: change to allow 32 bit access to registers If CONFIG_SYS_NS16550_MEM32 is defined then 32 bit memory mapped access will be used to read/write the uart registers. This is especially useful for SoC devices that implement 16550 compatible uarts but that have peripheral access width constraints. Signed-off-by: Dave Aldridge <fovsoft@gmail.com> |
#
a160ea0b |
|
27-Oct-2010 |
Prafulla Wadaskar <prafulla@marvell.com> |
Serial: ns16550: Add support for CONFIG_SYS_NS16550_IER macro On some processors this ier register configuration is different for ex. Marvell Armada100 This patch introduce CONFIG_SYS_NS16550_IER macro support to unconditionally initialize this register. Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com> |
#
1a2d9b30 |
|
12-Oct-2010 |
Stefan Roese <sr@denx.de> |
ns16550: Add WATCHDOG_RESET to putc for short watchdog timeout boards Call watchdog_reset() upon newline. This is done here in putc since the environment code uses a single puts() to print the complete envrironment upon "printenv". So we can't put this watchdog call in puts(). This is needed for boards with a very short watchdog timeout, like the lwmon5 with a 100ms timeout. Without this patch this board resets in the commands with long outputs, like "printenv" or "fdt print". Note that the image size is not increased with this patch when CONFIG_HW_WATCHDOG or CONFIG_WATCHDOG are not defined since the compiler optimizes this additional code away. Signed-off-by: Stefan Roese <sr@denx.de> Fix typo in comment. Signed-off-by: Wolfgang Denk <wd@denx.de> |
#
167cdad1 |
|
23-Apr-2010 |
Graeme Russ <graeme.russ@gmail.com> |
SERIAL: Enable port-mapped access The x86 architecture exclusively uses Port-Mapped I/O (inb/outb) to access the 16550 UARTs. This patch mimics how Linux selects between Memory-Mapped and Port-Mapped I/O. This allows x86 boards to use CONFIG_SERIAL_MUTLI and drop the custom serial port driver Signed-off-by: Graeme Russ <graeme.russ@gmail.com> |
#
a47a12be |
|
15-Apr-2010 |
Stefan Roese <sr@denx.de> |
Move arch/ppc to arch/powerpc As discussed on the list, move "arch/ppc" to "arch/powerpc" to better match the Linux directory structure. Please note that this patch also changes the "ppc" target in MAKEALL to "powerpc" to match this new infrastructure. But "ppc" is kept as an alias for now, to not break compatibility with scripts using this name. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Wolfgang Denk <wd@denx.de> Acked-by: Detlev Zundel <dzu@denx.de> Acked-by: Kim Phillips <kim.phillips@freescale.com> Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Anatolij Gustschin <agust@denx.de> |
#
a1b322a9 |
|
01-Feb-2010 |
Ladislav Michl <ladis@linux-mips.org> |
ns16550: kick watchdog while waiting for a character ns16550 busyloops waiting for incoming byte causing watchdog to reboot while waiting for a key press. A call to WATCHDOG_RESET in NS16550_getc loop fixes it. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> |
#
660888b7 |
|
30-May-2009 |
Tom Rix <Tom.Rix@windriver.com> |
ZOOM2 Add serial support. Zoom2 serial is in general supplied by one of the 4 UARTS on the debug board. The default serial is from the USB connector on left side of the debug board. The USB connector will produce 2 of the 4 UARTS. On your host pick the first enumeration. The details of the setting of the serial gpmc setup are not available. The values were provided by another party. The serial port set up is the same with Zoom1. Baud rate 115200, 8 bit data, no parity, 1 stop bit, no flow. The kernel bootargs are console=ttyS3,115200n8 Signed-off-by: Tom Rix <Tom.Rix@windriver.com> |
#
200779e3 |
|
03-Apr-2009 |
Detlev Zundel <dzu@denx.de> |
Rename common ns16550 constants with UART_ prefix to prevent conflicts Fix problems introduced in commit 7b5611cdd12ca0cc33f994f0d4a4454788fc3124 [inka4x0: Add hardware diagnosis functions for inka4x0] which redefined MSR_RI which is already used on PowerPC systems. Also eliminate redundant definitions in ps2mult.h. More cleanup will be needed for other redundant occurrences though. Signed-off-by: Detlev Zundel <dzu@denx.de> |
#
b4746d8b |
|
11-Feb-2009 |
Mike Frysinger <vapier@gentoo.org> |
drivers/serial/ns16550: move ifdef into Makefile COBJS-$(...) Signed-off-by: Mike Frysinger <vapier@gentoo.org> |
#
f5675aa5 |
|
18-Feb-2009 |
Ron Madrid <ron_madrid@sbcglobal.net> |
Create configuration option for restricted ns16550 functions This patch will create a configuration option for a minimum configuration for the ns16550 serial driver at drivers/serial/ns16550.c and will apply this new configuration option to the SIMPC8313.h config file in order to fix the NAND bootstrap build error. This option will exclude all functions with exception of NS16550_putc and NS16550_init. This will be used primarily to save space and remove unused code from builds in which space is limited. Signed-off-by: Ron Madrid <ron_madrid@sbcglobal.net> |
#
6d0f6bcf |
|
16-Oct-2008 |
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
rename CFG_ macros to CONFIG_SYS Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
#
7ec8bb15 |
|
27-Dec-2007 |
Wolfgang Denk <wd@denx.de> |
OMAP5912: fix FIFO handling in UART driver According to the OMAP5912 Serial Interfaces Reference Guide (see http://focus.ti.com/lit/ug/spru760c/spru760c.pdf, page 150), the FIFO_EN enable bit in the FIFO Control Register (FCR) can only be changed when the baud clock is not running, i. e. when both DLL and DLH are set to 0. Thus make sure that DLL and DLH are 0 when writing the FCR. Signed-off-by: Wolfgang Denk <wd@denx.de> |
#
1378df79 |
|
24-Nov-2007 |
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
drivers/serial : move serial drivers to drivers/serial Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
#
d293759d |
|
06-May-2022 |
Pali Rohár <pali@kernel.org> |
serial: ns16550: Add support for SPL_DEBUG_UART_BASE Use CONFIG_VAL(DEBUG_UART_BASE) instead of CONFIG_DEBUG_UART_BASE, so proper config value (CONFIG_DEBUG_UART_BASE or CONFIG_SPL_DEBUG_UART_BASE) is used based on building target. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
04ee76c9 |
|
09-Apr-2022 |
Johan Jonker <jbx6244@gmail.com> |
rockchip: serial: move driver alias to serial_rockchip.c The Rockchip uart DT nodes have "snps,dw-apb-uart" as fall back string. The driver ns16550.c has CONFIG_IS_ENABLED(OF_REAL) as condition to of_match and does not copy dtplat data. For TPL/SPL the driver serial_rockchip.c is used. Move driver alias to correct driver. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
f899cc14 |
|
12-Sep-2021 |
Tom Rini <trini@konsulko.com> |
ti: keystone: Move away from CONFIG_SOC_KEYSTONE We have individual SOC symbols for each keystone 2 platform. Use the existing CONFIG_ARCH_KEYSTONE rather than CONFIG_SOC_KEYSTONE to encompass all of the keystone families. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
414cc151 |
|
07-Aug-2021 |
Simon Glass <sjg@chromium.org> |
treewide: Simply conditions with the new OF_REAL Use this new Kconfig to simplify the compilation conditions where appropriate. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
384b62c0 |
|
03-Feb-2021 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Handle zero <clock-frequency> value A working device tree node of ns16550 should never be populated with value zero for the <clock-frequency> property. Unfortunately this is the case for the QEMU ppce500 target. Let's try to assign plat->clock to CONFIG_SYS_NS16550_CLK as the last resort to handle such case. This commit should be reverted when: - The following QEMU patch [1] is merged, and - U-Boot CI has upgraded its QEMU version that contains the fix [1] http://patchwork.ozlabs.org/project/qemu-devel/patch/1612362288-22216-2-git-send-email-bmeng.cn@gmail.com/ Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
09bd0840 |
|
03-Feb-2021 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Correct the base address type Currently ns16550_serial_assign_base() treats the argument 'base' with type `ulong`. This is incorrect because the base address was obtained from device tree with type `fdt_addr_t` that can represent a physical address larger than 32-bit in a 32-bit system. Fixes: 9e6ce62190b7 ("serial: ns16550: Fix ordering of getting base address") Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
401d1c4f |
|
30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
bdf8fd76 |
|
28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
0fd3d911 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com> |
#
2d6bf754 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
#
d30c7209 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
41575d8e |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo |
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de> |
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> |
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se> |
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> |
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com |
#
9ad3b049 |
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02-Nov-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: add setconfig support Add possibility to update the serial parity used. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com> |
#
46879196 |
|
24-Oct-2018 |
Bin Meng <bmeng.cn@gmail.com> |
serial: Remove DM_FLAG_PRE_RELOC flag in various drivers When a driver declares DM_FLAG_PRE_RELOC flag, it wishes to be bound before relocation. However due to a bug in the DM core, the flag only takes effect when devices are statically declared via U_BOOT_DEVICE(). This bug has been fixed recently by commit "dm: core: Respect drivers with the DM_FLAG_PRE_RELOC flag in lists_bind_fdt()", but with the fix, it has a side effect that all existing drivers that declared DM_FLAG_PRE_RELOC flag will be bound before relocation now. This may expose potential boot failure on some boards due to insufficient memory during the pre-relocation stage. To mitigate this potential impact, the following changes are implemented: - Remove DM_FLAG_PRE_RELOC flag in the driver, if the driver only supports configuration from device tree (OF_CONTROL) - Keep DM_FLAG_PRE_RELOC flag in the driver only if the device is statically declared via U_BOOT_DEVICE() - Surround DM_FLAG_PRE_RELOC flag with OF_CONTROL check, for drivers that support both statically declared devices and configuration from device tree Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
6f57c344 |
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09-Aug-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), let's rather ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
5d754197 |
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27-Aug-2018 |
Lokesh Vutla <lokeshvutla@ti.com> |
serial: omap: Introduce DM specific omap serial Add driver model support for OMAP_SERIAL while reusing the functions in ns16550.c Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Tested-by: Derald D. Woods <woods.technical@gmail.com> |
#
b051eecb |
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14-Jun-2018 |
Ley Foon Tan <ley.foon.tan@intel.com> |
serial: ns16550: Add reset ctrl to driver Add code to reset all reset signals as in serial DT node. A reset property is an optional feature, so do not fail if a reset property is not present. If a reset property is discovered, then use it to deassert, thus bringing the IP out of reset. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
78b7d37b |
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15-Feb-2018 |
Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> |
ns16550: Fix mem mapped endian check Do a explicit check for CONFIG_SYS_BIG_ENDIAN and CONFIG_SYS_LITTLE_ENDIAN to avoid errors on platforms where both are undefined (x86). Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> Reviewed-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com> |
#
4dbf9bed |
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15-Jan-2018 |
Mario Six <mario.six@gdsys.cc> |
serial: ns16550: Fix style violation Clarify the computation precedence in two ternary operator constructions. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc> |
#
7fded0ce |
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16-Aug-2017 |
Stefan Roese <sr@denx.de> |
Revert "serial: ns16550: Add RX interrupt buffer support" This reverts commit 6822cf3ec7c8768b8727573b8f4b2cb3d870b881. As Bin Meng has tested and pointed out, we don't need the RX interrupt for the RX buffer support at all. Just reading all available characters into a buffer is sufficient to solve the problem with the dropped characters upon long lines pasted into the U-Boot prompt. Since this RX buffer support can be implemented in a generic way, without any device specifica (e.g. for the ns16550), I'll post a new patch with a new serial RX buffer support for DM, which all DM based serial drivers can use. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
6822cf3e |
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14-Jul-2017 |
Stefan Roese <sr@denx.de> |
serial: ns16550: Add RX interrupt buffer support Pasting longer lines into the U-Boot console prompt sometimes leads to characters missing. One problem here is the small 16-byte FIFO of the legacy NS16550 UART, e.g. on x86 platforms. This patch now introduces a Kconfig option to enable RX interrupt buffer support for NS16550 style UARTs. With this option enabled, I was able paste really long lines into the U-Boot console, without any characters missing. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> [trini: Guard ns16550_serial_remove with CONFIG_IS_ENABLED(SERIAL_PRESENT) to match struct assignment] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
8d3a2568 |
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11-Jul-2017 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-dm
|
#
db9f8f6a |
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12-Jun-2017 |
Simon Glass <sjg@chromium.org> |
dm: serial: ns16550: Convert to livetree Update this driver to support a live device tree. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Tested-on: Beaver, Jetson-TK1 |
#
3d40479f |
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07-Jun-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
rockchip: ns16550: dm: convert fdt_get to dev_read With the new dev_read functions available, we can convert the rockchip architecture-specific drivers and common drivers used by these devices over to the dev_read family of calls. This covers the serial driver (ns16550 and compatible) used for the Rockchip devices. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
a821c4af |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: Rename dev_addr..() functions These support the flat device tree. We want to use the dev_read_..() prefix for functions that support both flat tree and live tree. So rename the existing functions to avoid confusion. In the end we will have: 1. dev_read_addr...() - works on devices, supports flat/live tree 2. devfdt_get_addr...() - current functions, flat tree only 3. of_get_address() etc. - new functions, live tree only All drivers will be written to use 1. That function will in turn call either 2 or 3 depending on whether the flat or live tree is in use. Note this involves changing some dead code - the imx_lpi2c.c file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
89024ddc |
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12-May-2017 |
Tom Rini <trini@konsulko.com> |
TI: Drop 'CONFIG_OMAP' In the two cases in the code where we use CONFIG_OMAP as a useful test currently we can make use of CONFIG_ARCH_OMAP2PLUS instead. With that changed we can drop all defines of CONFIG_OMAP. While in here, CONFIG_OMAP3430 is only defined and then never used, so drop. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
a52cf086 |
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22-Apr-2017 |
Lokesh Vutla <lokeshvutla@ti.com> |
serial: omap: Support debug UART Add debug UART functions to permit omap specific ns16550 to provide an early debug UART. This is mostly in common with DEBUG_UART_NS16550 except for Mode definition register which is required for selecting UART mode(16x auto-baud or 13x mode). Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
6f8c351e |
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27-Mar-2017 |
Alexandru Gagniuc <alex.g@adaptrum.com> |
serial: ns16550: Link in the DM driver when when using platdata Do not condition the compilation of the U_BOOT_DRIVER by !OF_PLATDATA. This is inconsistent with the majority of other drivers. This also blocks OF_PLATDATA boards with an 16550-compatible serial from using serial in SPL. Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com> Reviewed-by: Simon Glass <sjg@chromium.org> Added tweak for rock to avoid a TPL build failure: Signed-off-by: Simon Glass <sjg@chromium.org> |
#
e160f7d4 |
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17-Jan-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
17fa0326 |
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18-Jan-2017 |
Heiko Schocher <hs@denx.de> |
serial, ns16550: bugfix: ns16550 fifo not enabled commit: 65f83802b7a5b "serial: 16550: Add getfcr accessor" breaks u-boot commandline working with long commands sending to the board. Since the above patch, you have to setup the fcr register. For board/archs which enable OF_PLATDATA, the new field fcr in struct ns16550_platdata is not filled with a default value ... This leads in not setting up the uarts fifo, which ends in problems, when you send long commands to u-boots commandline. Detected this issue with automated tbot tests on am335x based shc board. The error does not popup, if you type commands. You need to copy&paste a long command to u-boots commandshell (or send a long command with tbot) Possible boards/plattforms with problems: ./arch/arm/cpu/arm926ejs/lpc32xx/devices.c ./arch/arm/mach-tegra/board.c ./board/overo/overo.c ./board/quipos/cairo/cairo.c ./board/logicpd/omap3som/omap3logic.c ./board/logicpd/zoom1/zoom1.c ./board/timll/devkit8000/devkit8000.c ./board/lg/sniper/sniper.c ./board/ti/beagle/beagle.c ./drivers/serial/serial_rockchip.c Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Tested-by: Adam Ford <aford173@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
0b060eef |
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30-Nov-2016 |
Marek Vasut <marex@denx.de> |
serial: 16550: Add Ingenic JZ4780 support Add compatibility string for the Ingenic JZ4780 SoC, the necessary UART enable bit into FCR and register shift. Neither are encoded in the DTS coming from Linux, so we need to support it this way. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
79fd9281 |
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30-Nov-2016 |
Marek Vasut <marex@denx.de> |
serial: 16550: Add port type as driver data Add driver data to each compatible string to identify the type of the port. Since all the ports in the driver are entirely compatible with 16550 for now, all are marked with PORT_NS16550. But, there are ports which have specific quirks, like the JZ4780 UART, which do not have any DT property to denote the quirks. Instead, Linux uses the compatible string to discern such ports and enable the necessary quirks. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> |
#
65f83802 |
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30-Nov-2016 |
Marek Vasut <marex@denx.de> |
serial: 16550: Add getfcr accessor Add function which allows fetching the default FCR register setting from platform data for DM , while retaining old behavior for non-DM by returning UART_FCRVAL. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
021abf69 |
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26-Sep-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
Revert "ns16650: Make sure we have CONFIG_CLK set before using infrastructure" This reverts commit 82f5279b0cd99a9163d34cfe926d0316d9dc0d37. The build failure of k2*evm boards was fixed in a different way by the previous commit. It is nasty to patch generic drivers around with #ifdef CONFIG_CLK just for the KeyStone's matter. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
ab895d6a |
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30-Sep-2016 |
Alexandre Courbot <acourbot@nvidia.com> |
serial: ns16550: Handle -ENOENT when requesting clock When calling clk_get_by_index(), fall back to the legacy method of getting the clock if -ENOENT is returned. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> |
#
82f5279b |
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22-Sep-2016 |
Tom Rini <trini@konsulko.com> |
ns16650: Make sure we have CONFIG_CLK set before using infrastructure We cannot call on the CONFIG_CLK based clk_get_rate function unless CONFIG_CLK is set. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
50fce1d5 |
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08-Sep-2016 |
Paul Burton <paul.burton@mips.com> |
serial: ns16550: Support clocks via phandle Previously ns16550 compatible UARTs probed via device tree have needed their device tree nodes to contain a clock-frequency property. An alternative to this commonly used with Linux is to reference a clock via a phandle. This patch allows U-Boot to support that, retrieving the clock frequency by probing the appropriate clock device. For example, a system might choose to provide the UART base clock as a reference to a clock common to multiple devices: sys_clk: clock { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <10000000>; }; uart0: uart@10000000 { compatible = "ns16550a"; reg = <0x10000000 0x1000>; clocks = <&sys_clk>; }; uart1: uart@10000000 { compatible = "ns16550a"; reg = <0x10001000 0x1000>; clocks = <&sys_clk>; }; This removes the need for the frequency information to be duplicated in multiple nodes and allows the device tree to be more descriptive of the system. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
b2927fba |
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04-Jul-2016 |
Simon Glass <sjg@chromium.org> |
dm: serial: ns16550: Update to support of-platdata With of-platdata this driver cannot know the format of the of-platdata struct, so we cannot use generic code for accessing the of-platdata. Each SoC that uses this driver will need to set up ns16550's platdata for it. So don't compile in the generic code. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
03c6f176 |
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24-May-2016 |
Marek Vasut <marex@denx.de> |
serial: 16550: Drop OMAP1510 support The CONFIG_OMAP1510 is no longer defined, so remove this dead code. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Nishanth Menon <nm@ti.com> |
#
fa4ce723 |
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24-May-2016 |
Marek Vasut <marex@denx.de> |
serial: 16550: Make serial_io/out_shift available to debug mode The ns16550 driver needs serial_in_shift() and serial_out_shift() when compiled in debug UART mode, so shift the DM_SERIAL check a little to make these functions available. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
df8ec55d |
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17-May-2016 |
Paul Burton <paul.burton@mips.com> |
dm: ns16550: Don't map_physmem for I/O ports If the UART is to be accessed using I/O port accessors (inb & outb) then using map_physmem doesn't make sense, since it operates in a different memory space. Remove the call to map_physmem when CONFIG_SYS_NS16550_PORT_MAPPED is defined, allowing I/O port addresses to not be mangled by the incorrect mapping. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> |
#
59b35ddd |
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16-Feb-2016 |
Michal Simek <michal.simek@amd.com> |
dm: ns16550: Add support for reg-offset property reg-offset is the part of standard 8250 binding in the kernel. It is shifting start of address space by reg-offset. On Xilinx platform this offset is typically 0x1000. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Moved the new field to the end of the struct to avoid problems: Signed-off-by: Simon Glass <sjg@chromium.org> |
#
e5e88c65 |
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29-Feb-2016 |
Tom Rini <trini@konsulko.com> |
Revert "dm: ns16550: Add support for reg-offset property" This reverts commit d9a3bec682f9756621615f4306718a356a3230e3. While this is a correct change to do long term it unfortunately breaks a number of platforms that are using pdata and not named struct members so they are getting all of their data after 'base' incorrect. Acked-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
d9a3bec6 |
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16-Feb-2016 |
Michal Simek <michal.simek@amd.com> |
dm: ns16550: Add support for reg-offset property reg-offset is the part of standard 8250 binding in the kernel. It is shifting start of address space by reg-offset. On Xilinx platform this offset is typically 0x1000. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
cc4228f9 |
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14-Dec-2015 |
Thomas Chou <thomas@wytron.com.tw> |
ns16550: zap the rockchip serial compatible string Zap the rockchip serial compatible string, because rockchip serial has "snps,dw-apb-uart" compatible string in the dts. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org> |
#
b7e29834 |
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13-Dec-2015 |
Simon Glass <sjg@chromium.org> |
dm: ns16550: Allow the driver to be omitted if requested Allow the ns16550 debug UART to be used without the full driver. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Thomas Chou <thomas@wytron.com.tw> |
#
fcc0a877 |
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29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: serial: Convert ns16550 driver to use driver model PCI API Use the driver model version of the function to find the BAR. This updates the fdtdec function, of which ns16550 is the only user. The fdtdec_get_pci_bdf() function is dropped for several reasons: - with driver model we should use 'struct udevice *' rather than passing the device tree offset explicitly - there are no other users in the tree - the function parses for information which is already available in the PCI device structure (specifically struct pci_child_platdata which is available at dev_get_parent_platdata(dev) Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> |
#
b7e5a643 |
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04-Dec-2015 |
Simon Glass <sjg@chromium.org> |
dm: serial: ns16550: Add pre-reloc flag to the driver For platforms that don't use device tree in SPL the only way to mark this driver as 'required by relocation' is with the DM_FLAG_PRE_RELOC flag. Add this to ensure that the driver is bound. Fixes: fde7e18938d8 ("dm: tegra: pci: Move CONFIG_PCI_TEGRA to Kconfig") Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Stephen Warren <swarren@nvidia.com> Acked-by: Thomas Chou <thomas@wytron.com.tw> |
#
80e06146 |
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28-Nov-2015 |
Thomas Chou <thomas@wytron.com.tw> |
ns16550: change reg-shift property default to zero Change reg-shift property default to zero. When the integer property is missing, it should be taken as zero. This is consistent to Linux drivers/tty/serial/of_serial.c. The x86 and most powerpc use reg-shift of 0. Most others use reg-shift of 2. While reg-shift of 1 is rarely used. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
a51dbebf |
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16-Nov-2015 |
huang lin <hl@rock-chips.com> |
rockchip: serial driver support rk3036 Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
4fb60552 |
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19-Nov-2015 |
Thomas Chou <thomas@wytron.com.tw> |
ns16550: zap CONFIG_NS16550_SERIAL Zap CONFIG_NS16550_SERIAL, as the unification of ns16550 drivers is completed. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
8e62d32e |
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19-Nov-2015 |
Thomas Chou <thomas@wytron.com.tw> |
ns16550: add generic binding to unify the drivers Add generic binding to unify ns16550 drivers. There are several drivers using almost the same code, such as serial_dw, serial_keystone, serial_omap, serial_ppc, serial_rockchip, serial_tegra.c, and serial_x86. But each is platform specific. The key difference between these drivers is the way to get input clock frequency. With this unified approach, fixed clock frequency should be extracted from "clock-frequency" property of device tree blob. If this property is not available, the macro CONFIG_SYS_NS16550_CLK will be used. It can be a constant or a function to get clock, eg, get_serial_clock(). Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de> Acked-by: Simon Glass <sjg@chromium.org> |
#
77d7b5cd |
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19-Nov-2015 |
Thomas Chou <thomas@wytron.com.tw> |
ns16550: change map_sysmem to map_physmem Change map_sysmem() to map_physmem(,,MAP_NOCACHE). Though map_sysmem() can be used to map system memory, it might be wrong to use it for I/O ports. The map_physmem() serves the same purpose to translate physical address to virtual address with the additional flag to take care of cache property. Most drivers use map_physmem() since I/O ports access should be uncached. As ns16550 is a driver, it should use map_physmem() rather than map_sysmem(). Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org> |
#
97b05973 |
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18-Oct-2015 |
Simon Glass <sjg@chromium.org> |
debug_uart: Adjust the declaration of debug_uart_init() We want to be able to add other common code to this function. So change the driver's version to have an underscore before it, just like _debug_uart_putc(). Define debug_uart_init() to call this version. Update all drivers to this new method. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
4e9838c1 |
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11-Aug-2015 |
Simon Glass <sjg@chromium.org> |
dm: Use dev_get_addr() where possible This is a convenient way for a driver to get the hardware address of a device, when regmap or syscon are not being used. Change existing callers to use it as an example to others. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> |
#
0f925822 |
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11-Aug-2015 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
of: clean up OF_CONTROL ifdef conditionals We have flipped CONFIG_SPL_DISABLE_OF_CONTROL. We have cleansing devices, $(SPL_) and CONFIG_IS_ENABLED(), so we are ready to clear away the ugly logic in include/fdtdec.h: #ifdef CONFIG_OF_CONTROL # if defined(CONFIG_SPL_BUILD) && !defined(SPL_OF_CONTROL) # define OF_CONTROL 0 # else # define OF_CONTROL 1 # endif #else # define OF_CONTROL 0 #endif Now CONFIG_IS_ENABLED(OF_CONTROL) is the substitute. It refers to CONFIG_OF_CONTROL for U-boot proper and CONFIG_SPL_OF_CONTROL for SPL. Also, we no longer have to cancel CONFIG_OF_CONTROL in include/config_uncmd_spl.h and scripts/Makefile.spl. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> |
#
6e780c7a |
|
23-Jun-2015 |
Simon Glass <sjg@chromium.org> |
ns16550: Improve debug UART so it can work with 32-bit access Since Rockchip requires 32-bit serial access, add this to the driver. Refactor a little to make this easier. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
90914008 |
|
12-May-2015 |
Simon Glass <sjg@chromium.org> |
dm: ns16550: Support CONFIG_SYS_NS16550_MEM32 with driver model This option is used by some boards, so support it with driver model. This is really ugly - we should rewrite this driver once all users are moved to driver model. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4f60166c |
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24-Apr-2015 |
Axel Lin <axel.lin@ingics.com> |
serial: ns16550: Remove hard-coded baud_divisor setting This was accidentally added by commit dd0b0122bacc "serial: ns16550: Add an option to specify the debug UART register shift". Remove it. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
ab9fd2e8 |
|
27-Feb-2015 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Remove unnecessary init on UART setup It is not necessary to write a zero baud rate to the device, and for some chips this will cause problems. Drop this code. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
363e6da1 |
|
27-Feb-2015 |
Simon Glass <sjg@chromium.org> |
dm: ns16550: Support non-byte register spacing with driver model Allow this driver to support boards where the register shift is not 0. This fixes some compiler warnings which appear in that case. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
dd0b0122 |
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27-Feb-2015 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Add an option to specify the debug UART register shift This UART permits different register spacing. To support the debug UART on devices which have a spacing other than 1 byte, allow the shift value to be specified. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
0eb25b61 |
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22-Mar-2015 |
Joe Hershberger <joe.hershberger@ni.com> |
common: Make sure arch-specific map_sysmem() is defined In the case where the arch defines a custom map_sysmem(), make sure that including just mapmem.h is sufficient to have these functions as they are when the arch does not override it. Also split the non-arch specific functions out of common.h Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
20379c11 |
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28-Feb-2015 |
Axel Lin <axel.lin@ingics.com> |
serial: ns16550: Fix build error due to a typo Fix trivial typo. Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Axel Lin <axel.lin@ingics.com> |
#
21d00436 |
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26-Jan-2015 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support debug UART Add debug UART functions to permit ns16550 to provide an early debug UART. Try to avoid using the stack so that this can be called from assembler before a stack is set up (at least on ARM and PowerPC). Signed-off-by: Simon Glass <sjg@chromium.org> |
#
76571674 |
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26-Jan-2015 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Add access functions that don't need platdata For the debug UART we need to be able to provide any parameters before driver model is set up. Add parameters to the low-level access functions to make this possible. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
3db886a5 |
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31-Dec-2014 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Support ns16550 compatible pci uart devices There are many pci uart devices which are ns16550 compatible. We can describe them in the board dts file and use it as the U-Boot serial console as specified in the chosen node 'stdout-path' property. Those pci uart devices can have their register be memory-mapped, or i/o-mapped. The driver will try to use the memory-mapped register if the reg property in the node has an entry to describe the memory-mapped register, otherwise i/o-mapped register will be used. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
956a8bae |
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10-Nov-2014 |
Gregoire Gentil <gregoire@gentil.com> |
ns16550.c: Fix for ns16550 driver hanging on OMAP4 The same problem that is seen on some OMAP3 is also seen on some OMAP4 so include them in the test in order to prevent some hangs during SPL. [trini: Re-word commit message, make apply cleanly] Signed-off-by: Tom Rini <trini@ti.com> |
#
1f77690e |
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10-Oct-2014 |
Simon Glass <sjg@chromium.org> |
dm: serial: ns16550: Add a cast to the I/O operations This generates a warning when driver model is enabled, so fix it by adding a cast. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
11c1a878 |
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22-Oct-2014 |
Simon Glass <sjg@chromium.org> |
dm: ns16550: Correct the probe logic for platform data The probe logic sets up the pointer to the platform data in the device tree decode method. It should be done in the probe() method, and anyway the device tree decode method can't be used when CONFIG_OF_CONTROL is not enabled. Fix these two problems. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@ti.com> |
#
167efe01 |
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22-Oct-2014 |
Simon Glass <sjg@chromium.org> |
dm: ns16550: Use an address instead of a pointer for the uart base It is inconvenient to have to use casts when specifying platform data. Also it is not strictly correct, since we should use map_sysmem() to convert an address to a pointer. Adjust the platform data to use an address. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@ti.com> |
#
aea2be20 |
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22-Oct-2014 |
Simon Glass <sjg@chromium.org> |
dm: serial: ns16550: Correct logic for checking for character There is a bug in the logic which checks for an available character. This can cause invalid characters to be received - this was noticed on beaglebone. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@ti.com> |
#
12e431b2 |
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04-Sep-2014 |
Simon Glass <sjg@chromium.org> |
dm: serial: Add driver model support for ns16550 Add driver model support so that ns16550 can support operation both with and without driver model. The driver needs a clock frequency so cannot stand alone unfortunately. The clock frequency must be provided by a separate driver. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8bbe33c8 |
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04-Sep-2014 |
Simon Glass <sjg@chromium.org> |
dm: serial: Collect common baud rate code in ns16550 The same sequence is used in several places, so move it into a function. Note that UART_LCR_BKSE is an alias for UART_LCR_DLAB. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
fa54eb12 |
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04-Sep-2014 |
Simon Glass <sjg@chromium.org> |
dm: serial: Move baud rate calculation to ns16550.c Move the function that calculates the baud rate divisor into ns16550.c so it can be used by that file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8ac22a60 |
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30-Jul-2014 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
omap: clean-up dead configs The following configs are not defined at all. - CONFIG_OMAP1510 - CONFIG_OMAP_1510P1 - CONFIG_OMAP_SX1 - CONFIG_OMAP3_DMA - CONFIG_OMAP3_ZOOM2 - CONFIG_OMAP_INNOVATOR Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Tom Rini <trini@ti.com> |
#
7c387646 |
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15-Jul-2014 |
Khoronzhuk, Ivan <ivan.khoronzhuk@ti.com> |
keystone2: use CONFIG_SOC_KEYSTONE in common places Use CONFIG_SOC_KEYSTONE in common places instead of defining a lot of "if def .. || if def " for different Keystone2 SoC types. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> |
#
d57dee57 |
|
09-Apr-2014 |
Karicheri, Muralidharan <m-karicheri2@ti.com> |
serial: nsl16550: add hw flow control support keystone serial hw support hw flow control. This patch enables hw flow control for keystone EVMs as an optional feature based on CONFIG_SERIAL_HW_FLOW_CONTROL. Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> |
#
ef509b90 |
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04-Apr-2014 |
Vitaly Andrianov <vitalya@ti.com> |
k2hk: add support for k2hk SOC and EVM k2hk EVM is based on Texas Instruments Keystone2 Hawking/Kepler SoC. Keystone2 SoC has ARM v7 Cortex-A15 MPCore processor. Please refer the ti/k2hk_evm/README for details on the board, build and other information. This patch add support for keystone architecture and k2hk evm. Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: WingMan Kwok <w-kwok2@ti.com> Signed-off-by: Sandeep Nair <sandeep_n@ti.com> |
#
456ccfdf |
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20-Dec-2013 |
Tom Rini <trini@konsulko.com> |
TI:omap3: Drop omap3_zoom2 The omap3_zoom2 board has not been updated for a correct CONFIG_SYS_HZ and Tom Rix's email has long been bouncing. Signed-off-by: Tom Rini <trini@ti.com> |
#
9ed6e412 |
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01-Jul-2013 |
TENART Antoine <atenart@adeneo-embedded.com> |
Prepare for TI816X : reuse existing code from TI814X Rename some CONFIG_TI814X to a more generic CONFIG_TI81XX Signed-off-by: Antoine Tenart <atenart@adeneo-embedded.com> [trini: Adapt for CONFIG_OMAP_COMMON changes, AM43XX] Signed-off-by: Tom Rini <trini@ti.com> |
#
57180408 |
|
30-Jul-2013 |
Lokesh Vutla <lokeshvutla@ti.com> |
ARM: AM43xx: Add build support Add AM43xx support in the required places Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> |
#
7f5eef93 |
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03-Jun-2013 |
Tom Rini <trini@konsulko.com> |
arm: Remove OMAP2420H4 and all omap24xx support The omap2420H4 was the only mainline omap24xx board. Prior to being fixed by Jon Hunter in time for v2013.04 it had been functionally broken for a very long time. Remove this board as there's not been interest in it in U-Boot for quite a long time. Signed-off-by: Tom Rini <trini@ti.com> |
#
fd2aeac5 |
|
28-Mar-2013 |
Manfred Huber <man.huber@arcor.de> |
omap3_beagle: Flush UART3 xmit on enable if TEMT is broken Flush UART3 xmit on enable if TEMT is broken On some OMAP3 devices when UART3 is configured for boot mode before SPL starts only THRE bit is set. We have to empty the transmitter before initialization starts. This patch avoids the use of CONFIG_SYS_NS16550_BROKEN_TEMT. Signed-off-by: Manfred Huber <man.huber@arcor.de> Tested-by: Javier Martinez Canillas <javier@dowhile0.org> Tested-by: Andreas Bießmann <andreas.devel@googlemail.com> |
#
6213a68f |
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15-Mar-2013 |
Matt Porter <mporter@ti.com> |
ns16550: enable quirks for ti814x TI814X requires the same quirks as AM33XX to be enabled. Signed-off-by: Matt Porter <mporter@ti.com> Reviewed-by: Tom Rini <trini@ti.com> |
#
69e06832 |
|
05-Mar-2013 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Remove unwanted cast This cast does not seem correct, since we should be writing to a pointer, not a ulong. This fixes the following warning on nds32: -ns16550.c:49: warning: passing argument 2 of 'writeb' makes pointer from integer without a cast Signed-off-by: Simon Glass <sjg@chromium.org> |
#
7de0fe1a |
|
06-Jan-2013 |
Javier Martinez Canillas <javier@dowhile0.org> |
serial/ns16550: add an option to avoid hanging on broken platforms Some platforms (e.g. IGEPv2 board) has a broken ns16550 UART that does not set the TEMT bit when the transmitter is empty in SPL. This makes U-Boot to hang while waiting for TEMT to be set. Add a new option to avoid this: CONFIG_SYS_NS16550_BROKEN_TEMT 16550 UART set the Transmitter Empty (TEMT) Bit when all output has finished and the transmitter is totally empty. U-Boot waits for this bit to be set to initialize the serial console. On some broken platforms this bit is not set in SPL making U-Boot to hang while waiting for TEMT. Define this option to avoid it. Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> |
#
cb55b332 |
|
18-Sep-2012 |
Scott Wood <scottwood@freescale.com> |
serial/ns16550: wait for TEMT before initializing TEMT is set when the transmitter is totally empty and all output has finished. This prevents output problems (including a loss of synchronization observed on p2020 that persisted for quite a while) if SPL has output still on its way out. Signed-off-by: Scott Wood <scottwood@freescale.com> -- v2: fixed typo in subject, and explained what the bit does in the changelog |
#
f2041388 |
|
15-Sep-2012 |
Marek Vasut <marex@denx.de> |
serial: ns16550: Call usbtty_poll only in non-SPL build Having both USBTTY and CONFIG_SERIAL_MULTI enabled in SPL, the usbtty.c file is protected in Makefile to not be compiled into the SPL. Yet, the ns16550 serial driver does not contain such protection. Add it to avoid missing symbol error. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Marek Vasut <marek.vasut@gmail.com> Cc: Tom Rini <trini@ti.com> |
#
99b603e7 |
|
09-Jul-2012 |
Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com> |
serial/ns16550: ns16550 has a different register layout on SOC_DA8XX also fix NS16550_init() as we need 16x divider Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com> Acked-by: Christian Riesch <christian.riesch@omicron.at> Tested-by: Christian Riesch <christian.riesch@omicron.at> Acked-by: Sughosh Ganu <urwithsughosh@gmail.com> Tested-by: Sughosh Ganu <urwithsughosh@gmail.com> |
#
5289e83a |
|
13-Oct-2011 |
Chandan Nath <chandan.nath@ti.com> |
ARM:AM33XX: Add support for TI AM335X EVM This patch adds basic support for booting the board. This patch adds support for the UART necessary to get to the u-boot prompt. Signed-off-by: Chandan Nath <chandan.nath@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> |
#
f8df9d0d |
|
15-Oct-2011 |
Simon Glass <sjg@chromium.org> |
NS16550: trivial code clean for checkpatch This removes most checkpatch warnings from the ns16550 driver and its header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
79df1208 |
|
01-Sep-2011 |
Dave Aldridge <fovsoft@gmail.com> |
ns16550: change to allow 32 bit access to registers If CONFIG_SYS_NS16550_MEM32 is defined then 32 bit memory mapped access will be used to read/write the uart registers. This is especially useful for SoC devices that implement 16550 compatible uarts but that have peripheral access width constraints. Signed-off-by: Dave Aldridge <fovsoft@gmail.com> |
#
a160ea0b |
|
27-Oct-2010 |
Prafulla Wadaskar <prafulla@marvell.com> |
Serial: ns16550: Add support for CONFIG_SYS_NS16550_IER macro On some processors this ier register configuration is different for ex. Marvell Armada100 This patch introduce CONFIG_SYS_NS16550_IER macro support to unconditionally initialize this register. Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com> |
#
1a2d9b30 |
|
12-Oct-2010 |
Stefan Roese <sr@denx.de> |
ns16550: Add WATCHDOG_RESET to putc for short watchdog timeout boards Call watchdog_reset() upon newline. This is done here in putc since the environment code uses a single puts() to print the complete envrironment upon "printenv". So we can't put this watchdog call in puts(). This is needed for boards with a very short watchdog timeout, like the lwmon5 with a 100ms timeout. Without this patch this board resets in the commands with long outputs, like "printenv" or "fdt print". Note that the image size is not increased with this patch when CONFIG_HW_WATCHDOG or CONFIG_WATCHDOG are not defined since the compiler optimizes this additional code away. Signed-off-by: Stefan Roese <sr@denx.de> Fix typo in comment. Signed-off-by: Wolfgang Denk <wd@denx.de> |
#
167cdad1 |
|
23-Apr-2010 |
Graeme Russ <graeme.russ@gmail.com> |
SERIAL: Enable port-mapped access The x86 architecture exclusively uses Port-Mapped I/O (inb/outb) to access the 16550 UARTs. This patch mimics how Linux selects between Memory-Mapped and Port-Mapped I/O. This allows x86 boards to use CONFIG_SERIAL_MUTLI and drop the custom serial port driver Signed-off-by: Graeme Russ <graeme.russ@gmail.com> |
#
a47a12be |
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15-Apr-2010 |
Stefan Roese <sr@denx.de> |
Move arch/ppc to arch/powerpc As discussed on the list, move "arch/ppc" to "arch/powerpc" to better match the Linux directory structure. Please note that this patch also changes the "ppc" target in MAKEALL to "powerpc" to match this new infrastructure. But "ppc" is kept as an alias for now, to not break compatibility with scripts using this name. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Wolfgang Denk <wd@denx.de> Acked-by: Detlev Zundel <dzu@denx.de> Acked-by: Kim Phillips <kim.phillips@freescale.com> Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Anatolij Gustschin <agust@denx.de> |
#
a1b322a9 |
|
01-Feb-2010 |
Ladislav Michl <ladis@linux-mips.org> |
ns16550: kick watchdog while waiting for a character ns16550 busyloops waiting for incoming byte causing watchdog to reboot while waiting for a key press. A call to WATCHDOG_RESET in NS16550_getc loop fixes it. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> |
#
660888b7 |
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30-May-2009 |
Tom Rix <Tom.Rix@windriver.com> |
ZOOM2 Add serial support. Zoom2 serial is in general supplied by one of the 4 UARTS on the debug board. The default serial is from the USB connector on left side of the debug board. The USB connector will produce 2 of the 4 UARTS. On your host pick the first enumeration. The details of the setting of the serial gpmc setup are not available. The values were provided by another party. The serial port set up is the same with Zoom1. Baud rate 115200, 8 bit data, no parity, 1 stop bit, no flow. The kernel bootargs are console=ttyS3,115200n8 Signed-off-by: Tom Rix <Tom.Rix@windriver.com> |
#
200779e3 |
|
03-Apr-2009 |
Detlev Zundel <dzu@denx.de> |
Rename common ns16550 constants with UART_ prefix to prevent conflicts Fix problems introduced in commit 7b5611cdd12ca0cc33f994f0d4a4454788fc3124 [inka4x0: Add hardware diagnosis functions for inka4x0] which redefined MSR_RI which is already used on PowerPC systems. Also eliminate redundant definitions in ps2mult.h. More cleanup will be needed for other redundant occurrences though. Signed-off-by: Detlev Zundel <dzu@denx.de> |
#
b4746d8b |
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11-Feb-2009 |
Mike Frysinger <vapier@gentoo.org> |
drivers/serial/ns16550: move ifdef into Makefile COBJS-$(...) Signed-off-by: Mike Frysinger <vapier@gentoo.org> |
#
f5675aa5 |
|
18-Feb-2009 |
Ron Madrid <ron_madrid@sbcglobal.net> |
Create configuration option for restricted ns16550 functions This patch will create a configuration option for a minimum configuration for the ns16550 serial driver at drivers/serial/ns16550.c and will apply this new configuration option to the SIMPC8313.h config file in order to fix the NAND bootstrap build error. This option will exclude all functions with exception of NS16550_putc and NS16550_init. This will be used primarily to save space and remove unused code from builds in which space is limited. Signed-off-by: Ron Madrid <ron_madrid@sbcglobal.net> |
#
6d0f6bcf |
|
16-Oct-2008 |
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
rename CFG_ macros to CONFIG_SYS Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
#
7ec8bb15 |
|
27-Dec-2007 |
Wolfgang Denk <wd@denx.de> |
OMAP5912: fix FIFO handling in UART driver According to the OMAP5912 Serial Interfaces Reference Guide (see http://focus.ti.com/lit/ug/spru760c/spru760c.pdf, page 150), the FIFO_EN enable bit in the FIFO Control Register (FCR) can only be changed when the baud clock is not running, i. e. when both DLL and DLH are set to 0. Thus make sure that DLL and DLH are 0 when writing the FCR. Signed-off-by: Wolfgang Denk <wd@denx.de> |
#
1378df79 |
|
24-Nov-2007 |
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
drivers/serial : move serial drivers to drivers/serial Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
#
04ee76c9 |
|
09-Apr-2022 |
Johan Jonker <jbx6244@gmail.com> |
rockchip: serial: move driver alias to serial_rockchip.c The Rockchip uart DT nodes have "snps,dw-apb-uart" as fall back string. The driver ns16550.c has CONFIG_IS_ENABLED(OF_REAL) as condition to of_match and does not copy dtplat data. For TPL/SPL the driver serial_rockchip.c is used. Move driver alias to correct driver. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
f899cc14 |
|
12-Sep-2021 |
Tom Rini <trini@konsulko.com> |
ti: keystone: Move away from CONFIG_SOC_KEYSTONE We have individual SOC symbols for each keystone 2 platform. Use the existing CONFIG_ARCH_KEYSTONE rather than CONFIG_SOC_KEYSTONE to encompass all of the keystone families. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
414cc151 |
|
07-Aug-2021 |
Simon Glass <sjg@chromium.org> |
treewide: Simply conditions with the new OF_REAL Use this new Kconfig to simplify the compilation conditions where appropriate. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
384b62c0 |
|
03-Feb-2021 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Handle zero <clock-frequency> value A working device tree node of ns16550 should never be populated with value zero for the <clock-frequency> property. Unfortunately this is the case for the QEMU ppce500 target. Let's try to assign plat->clock to CONFIG_SYS_NS16550_CLK as the last resort to handle such case. This commit should be reverted when: - The following QEMU patch [1] is merged, and - U-Boot CI has upgraded its QEMU version that contains the fix [1] http://patchwork.ozlabs.org/project/qemu-devel/patch/1612362288-22216-2-git-send-email-bmeng.cn@gmail.com/ Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
09bd0840 |
|
03-Feb-2021 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Correct the base address type Currently ns16550_serial_assign_base() treats the argument 'base' with type `ulong`. This is incorrect because the base address was obtained from device tree with type `fdt_addr_t` that can represent a physical address larger than 32-bit in a 32-bit system. Fixes: 9e6ce62190b7 ("serial: ns16550: Fix ordering of getting base address") Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
401d1c4f |
|
30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
bdf8fd76 |
|
28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
0fd3d911 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com> |
#
2d6bf754 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
#
d30c7209 |
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22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
c69cda25 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
caa4daa2 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
41575d8e |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
addf358b |
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24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
5db92a0e |
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27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo |
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de> |
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> |
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se> |
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> |
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com |
#
9ad3b049 |
|
02-Nov-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: add setconfig support Add possibility to update the serial parity used. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com> |
#
46879196 |
|
24-Oct-2018 |
Bin Meng <bmeng.cn@gmail.com> |
serial: Remove DM_FLAG_PRE_RELOC flag in various drivers When a driver declares DM_FLAG_PRE_RELOC flag, it wishes to be bound before relocation. However due to a bug in the DM core, the flag only takes effect when devices are statically declared via U_BOOT_DEVICE(). This bug has been fixed recently by commit "dm: core: Respect drivers with the DM_FLAG_PRE_RELOC flag in lists_bind_fdt()", but with the fix, it has a side effect that all existing drivers that declared DM_FLAG_PRE_RELOC flag will be bound before relocation now. This may expose potential boot failure on some boards due to insufficient memory during the pre-relocation stage. To mitigate this potential impact, the following changes are implemented: - Remove DM_FLAG_PRE_RELOC flag in the driver, if the driver only supports configuration from device tree (OF_CONTROL) - Keep DM_FLAG_PRE_RELOC flag in the driver only if the device is statically declared via U_BOOT_DEVICE() - Surround DM_FLAG_PRE_RELOC flag with OF_CONTROL check, for drivers that support both statically declared devices and configuration from device tree Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
6f57c344 |
|
09-Aug-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), let's rather ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
5d754197 |
|
27-Aug-2018 |
Lokesh Vutla <lokeshvutla@ti.com> |
serial: omap: Introduce DM specific omap serial Add driver model support for OMAP_SERIAL while reusing the functions in ns16550.c Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Tested-by: Derald D. Woods <woods.technical@gmail.com> |
#
b051eecb |
|
14-Jun-2018 |
Ley Foon Tan <ley.foon.tan@intel.com> |
serial: ns16550: Add reset ctrl to driver Add code to reset all reset signals as in serial DT node. A reset property is an optional feature, so do not fail if a reset property is not present. If a reset property is discovered, then use it to deassert, thus bringing the IP out of reset. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
78b7d37b |
|
15-Feb-2018 |
Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> |
ns16550: Fix mem mapped endian check Do a explicit check for CONFIG_SYS_BIG_ENDIAN and CONFIG_SYS_LITTLE_ENDIAN to avoid errors on platforms where both are undefined (x86). Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> Reviewed-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com> |
#
4dbf9bed |
|
15-Jan-2018 |
Mario Six <mario.six@gdsys.cc> |
serial: ns16550: Fix style violation Clarify the computation precedence in two ternary operator constructions. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc> |
#
7fded0ce |
|
16-Aug-2017 |
Stefan Roese <sr@denx.de> |
Revert "serial: ns16550: Add RX interrupt buffer support" This reverts commit 6822cf3ec7c8768b8727573b8f4b2cb3d870b881. As Bin Meng has tested and pointed out, we don't need the RX interrupt for the RX buffer support at all. Just reading all available characters into a buffer is sufficient to solve the problem with the dropped characters upon long lines pasted into the U-Boot prompt. Since this RX buffer support can be implemented in a generic way, without any device specifica (e.g. for the ns16550), I'll post a new patch with a new serial RX buffer support for DM, which all DM based serial drivers can use. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
6822cf3e |
|
14-Jul-2017 |
Stefan Roese <sr@denx.de> |
serial: ns16550: Add RX interrupt buffer support Pasting longer lines into the U-Boot console prompt sometimes leads to characters missing. One problem here is the small 16-byte FIFO of the legacy NS16550 UART, e.g. on x86 platforms. This patch now introduces a Kconfig option to enable RX interrupt buffer support for NS16550 style UARTs. With this option enabled, I was able paste really long lines into the U-Boot console, without any characters missing. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> [trini: Guard ns16550_serial_remove with CONFIG_IS_ENABLED(SERIAL_PRESENT) to match struct assignment] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
8d3a2568 |
|
11-Jul-2017 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-dm
|
#
db9f8f6a |
|
12-Jun-2017 |
Simon Glass <sjg@chromium.org> |
dm: serial: ns16550: Convert to livetree Update this driver to support a live device tree. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Tested-on: Beaver, Jetson-TK1 |
#
3d40479f |
|
07-Jun-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
rockchip: ns16550: dm: convert fdt_get to dev_read With the new dev_read functions available, we can convert the rockchip architecture-specific drivers and common drivers used by these devices over to the dev_read family of calls. This covers the serial driver (ns16550 and compatible) used for the Rockchip devices. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
a821c4af |
|
17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: Rename dev_addr..() functions These support the flat device tree. We want to use the dev_read_..() prefix for functions that support both flat tree and live tree. So rename the existing functions to avoid confusion. In the end we will have: 1. dev_read_addr...() - works on devices, supports flat/live tree 2. devfdt_get_addr...() - current functions, flat tree only 3. of_get_address() etc. - new functions, live tree only All drivers will be written to use 1. That function will in turn call either 2 or 3 depending on whether the flat or live tree is in use. Note this involves changing some dead code - the imx_lpi2c.c file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
89024ddc |
|
12-May-2017 |
Tom Rini <trini@konsulko.com> |
TI: Drop 'CONFIG_OMAP' In the two cases in the code where we use CONFIG_OMAP as a useful test currently we can make use of CONFIG_ARCH_OMAP2PLUS instead. With that changed we can drop all defines of CONFIG_OMAP. While in here, CONFIG_OMAP3430 is only defined and then never used, so drop. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
a52cf086 |
|
22-Apr-2017 |
Lokesh Vutla <lokeshvutla@ti.com> |
serial: omap: Support debug UART Add debug UART functions to permit omap specific ns16550 to provide an early debug UART. This is mostly in common with DEBUG_UART_NS16550 except for Mode definition register which is required for selecting UART mode(16x auto-baud or 13x mode). Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
6f8c351e |
|
27-Mar-2017 |
Alexandru Gagniuc <alex.g@adaptrum.com> |
serial: ns16550: Link in the DM driver when when using platdata Do not condition the compilation of the U_BOOT_DRIVER by !OF_PLATDATA. This is inconsistent with the majority of other drivers. This also blocks OF_PLATDATA boards with an 16550-compatible serial from using serial in SPL. Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com> Reviewed-by: Simon Glass <sjg@chromium.org> Added tweak for rock to avoid a TPL build failure: Signed-off-by: Simon Glass <sjg@chromium.org> |
#
e160f7d4 |
|
17-Jan-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
17fa0326 |
|
18-Jan-2017 |
Heiko Schocher <hs@denx.de> |
serial, ns16550: bugfix: ns16550 fifo not enabled commit: 65f83802b7a5b "serial: 16550: Add getfcr accessor" breaks u-boot commandline working with long commands sending to the board. Since the above patch, you have to setup the fcr register. For board/archs which enable OF_PLATDATA, the new field fcr in struct ns16550_platdata is not filled with a default value ... This leads in not setting up the uarts fifo, which ends in problems, when you send long commands to u-boots commandline. Detected this issue with automated tbot tests on am335x based shc board. The error does not popup, if you type commands. You need to copy&paste a long command to u-boots commandshell (or send a long command with tbot) Possible boards/plattforms with problems: ./arch/arm/cpu/arm926ejs/lpc32xx/devices.c ./arch/arm/mach-tegra/board.c ./board/overo/overo.c ./board/quipos/cairo/cairo.c ./board/logicpd/omap3som/omap3logic.c ./board/logicpd/zoom1/zoom1.c ./board/timll/devkit8000/devkit8000.c ./board/lg/sniper/sniper.c ./board/ti/beagle/beagle.c ./drivers/serial/serial_rockchip.c Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Tested-by: Adam Ford <aford173@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
0b060eef |
|
30-Nov-2016 |
Marek Vasut <marex@denx.de> |
serial: 16550: Add Ingenic JZ4780 support Add compatibility string for the Ingenic JZ4780 SoC, the necessary UART enable bit into FCR and register shift. Neither are encoded in the DTS coming from Linux, so we need to support it this way. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
79fd9281 |
|
30-Nov-2016 |
Marek Vasut <marex@denx.de> |
serial: 16550: Add port type as driver data Add driver data to each compatible string to identify the type of the port. Since all the ports in the driver are entirely compatible with 16550 for now, all are marked with PORT_NS16550. But, there are ports which have specific quirks, like the JZ4780 UART, which do not have any DT property to denote the quirks. Instead, Linux uses the compatible string to discern such ports and enable the necessary quirks. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> |
#
65f83802 |
|
30-Nov-2016 |
Marek Vasut <marex@denx.de> |
serial: 16550: Add getfcr accessor Add function which allows fetching the default FCR register setting from platform data for DM , while retaining old behavior for non-DM by returning UART_FCRVAL. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
021abf69 |
|
26-Sep-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
Revert "ns16650: Make sure we have CONFIG_CLK set before using infrastructure" This reverts commit 82f5279b0cd99a9163d34cfe926d0316d9dc0d37. The build failure of k2*evm boards was fixed in a different way by the previous commit. It is nasty to patch generic drivers around with #ifdef CONFIG_CLK just for the KeyStone's matter. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
ab895d6a |
|
30-Sep-2016 |
Alexandre Courbot <acourbot@nvidia.com> |
serial: ns16550: Handle -ENOENT when requesting clock When calling clk_get_by_index(), fall back to the legacy method of getting the clock if -ENOENT is returned. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> |
#
82f5279b |
|
22-Sep-2016 |
Tom Rini <trini@konsulko.com> |
ns16650: Make sure we have CONFIG_CLK set before using infrastructure We cannot call on the CONFIG_CLK based clk_get_rate function unless CONFIG_CLK is set. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
50fce1d5 |
|
08-Sep-2016 |
Paul Burton <paul.burton@mips.com> |
serial: ns16550: Support clocks via phandle Previously ns16550 compatible UARTs probed via device tree have needed their device tree nodes to contain a clock-frequency property. An alternative to this commonly used with Linux is to reference a clock via a phandle. This patch allows U-Boot to support that, retrieving the clock frequency by probing the appropriate clock device. For example, a system might choose to provide the UART base clock as a reference to a clock common to multiple devices: sys_clk: clock { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <10000000>; }; uart0: uart@10000000 { compatible = "ns16550a"; reg = <0x10000000 0x1000>; clocks = <&sys_clk>; }; uart1: uart@10000000 { compatible = "ns16550a"; reg = <0x10001000 0x1000>; clocks = <&sys_clk>; }; This removes the need for the frequency information to be duplicated in multiple nodes and allows the device tree to be more descriptive of the system. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
b2927fba |
|
04-Jul-2016 |
Simon Glass <sjg@chromium.org> |
dm: serial: ns16550: Update to support of-platdata With of-platdata this driver cannot know the format of the of-platdata struct, so we cannot use generic code for accessing the of-platdata. Each SoC that uses this driver will need to set up ns16550's platdata for it. So don't compile in the generic code. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
03c6f176 |
|
24-May-2016 |
Marek Vasut <marex@denx.de> |
serial: 16550: Drop OMAP1510 support The CONFIG_OMAP1510 is no longer defined, so remove this dead code. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Nishanth Menon <nm@ti.com> |
#
fa4ce723 |
|
24-May-2016 |
Marek Vasut <marex@denx.de> |
serial: 16550: Make serial_io/out_shift available to debug mode The ns16550 driver needs serial_in_shift() and serial_out_shift() when compiled in debug UART mode, so shift the DM_SERIAL check a little to make these functions available. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
df8ec55d |
|
17-May-2016 |
Paul Burton <paul.burton@mips.com> |
dm: ns16550: Don't map_physmem for I/O ports If the UART is to be accessed using I/O port accessors (inb & outb) then using map_physmem doesn't make sense, since it operates in a different memory space. Remove the call to map_physmem when CONFIG_SYS_NS16550_PORT_MAPPED is defined, allowing I/O port addresses to not be mangled by the incorrect mapping. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> |
#
59b35ddd |
|
16-Feb-2016 |
Michal Simek <michal.simek@xilinx.com> |
dm: ns16550: Add support for reg-offset property reg-offset is the part of standard 8250 binding in the kernel. It is shifting start of address space by reg-offset. On Xilinx platform this offset is typically 0x1000. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Moved the new field to the end of the struct to avoid problems: Signed-off-by: Simon Glass <sjg@chromium.org> |
#
e5e88c65 |
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29-Feb-2016 |
Tom Rini <trini@konsulko.com> |
Revert "dm: ns16550: Add support for reg-offset property" This reverts commit d9a3bec682f9756621615f4306718a356a3230e3. While this is a correct change to do long term it unfortunately breaks a number of platforms that are using pdata and not named struct members so they are getting all of their data after 'base' incorrect. Acked-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
d9a3bec6 |
|
16-Feb-2016 |
Michal Simek <michal.simek@xilinx.com> |
dm: ns16550: Add support for reg-offset property reg-offset is the part of standard 8250 binding in the kernel. It is shifting start of address space by reg-offset. On Xilinx platform this offset is typically 0x1000. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
cc4228f9 |
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14-Dec-2015 |
Thomas Chou <thomas@wytron.com.tw> |
ns16550: zap the rockchip serial compatible string Zap the rockchip serial compatible string, because rockchip serial has "snps,dw-apb-uart" compatible string in the dts. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org> |
#
b7e29834 |
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13-Dec-2015 |
Simon Glass <sjg@chromium.org> |
dm: ns16550: Allow the driver to be omitted if requested Allow the ns16550 debug UART to be used without the full driver. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Thomas Chou <thomas@wytron.com.tw> |
#
fcc0a877 |
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29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: serial: Convert ns16550 driver to use driver model PCI API Use the driver model version of the function to find the BAR. This updates the fdtdec function, of which ns16550 is the only user. The fdtdec_get_pci_bdf() function is dropped for several reasons: - with driver model we should use 'struct udevice *' rather than passing the device tree offset explicitly - there are no other users in the tree - the function parses for information which is already available in the PCI device structure (specifically struct pci_child_platdata which is available at dev_get_parent_platdata(dev) Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> |
#
b7e5a643 |
|
04-Dec-2015 |
Simon Glass <sjg@chromium.org> |
dm: serial: ns16550: Add pre-reloc flag to the driver For platforms that don't use device tree in SPL the only way to mark this driver as 'required by relocation' is with the DM_FLAG_PRE_RELOC flag. Add this to ensure that the driver is bound. Fixes: fde7e18938d8 ("dm: tegra: pci: Move CONFIG_PCI_TEGRA to Kconfig") Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Stephen Warren <swarren@nvidia.com> Acked-by: Thomas Chou <thomas@wytron.com.tw> |
#
80e06146 |
|
28-Nov-2015 |
Thomas Chou <thomas@wytron.com.tw> |
ns16550: change reg-shift property default to zero Change reg-shift property default to zero. When the integer property is missing, it should be taken as zero. This is consistent to Linux drivers/tty/serial/of_serial.c. The x86 and most powerpc use reg-shift of 0. Most others use reg-shift of 2. While reg-shift of 1 is rarely used. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
a51dbebf |
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16-Nov-2015 |
huang lin <hl@rock-chips.com> |
rockchip: serial driver support rk3036 Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
4fb60552 |
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19-Nov-2015 |
Thomas Chou <thomas@wytron.com.tw> |
ns16550: zap CONFIG_NS16550_SERIAL Zap CONFIG_NS16550_SERIAL, as the unification of ns16550 drivers is completed. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
8e62d32e |
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19-Nov-2015 |
Thomas Chou <thomas@wytron.com.tw> |
ns16550: add generic binding to unify the drivers Add generic binding to unify ns16550 drivers. There are several drivers using almost the same code, such as serial_dw, serial_keystone, serial_omap, serial_ppc, serial_rockchip, serial_tegra.c, and serial_x86. But each is platform specific. The key difference between these drivers is the way to get input clock frequency. With this unified approach, fixed clock frequency should be extracted from "clock-frequency" property of device tree blob. If this property is not available, the macro CONFIG_SYS_NS16550_CLK will be used. It can be a constant or a function to get clock, eg, get_serial_clock(). Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de> Acked-by: Simon Glass <sjg@chromium.org> |
#
77d7b5cd |
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19-Nov-2015 |
Thomas Chou <thomas@wytron.com.tw> |
ns16550: change map_sysmem to map_physmem Change map_sysmem() to map_physmem(,,MAP_NOCACHE). Though map_sysmem() can be used to map system memory, it might be wrong to use it for I/O ports. The map_physmem() serves the same purpose to translate physical address to virtual address with the additional flag to take care of cache property. Most drivers use map_physmem() since I/O ports access should be uncached. As ns16550 is a driver, it should use map_physmem() rather than map_sysmem(). Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org> |
#
97b05973 |
|
18-Oct-2015 |
Simon Glass <sjg@chromium.org> |
debug_uart: Adjust the declaration of debug_uart_init() We want to be able to add other common code to this function. So change the driver's version to have an underscore before it, just like _debug_uart_putc(). Define debug_uart_init() to call this version. Update all drivers to this new method. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
4e9838c1 |
|
11-Aug-2015 |
Simon Glass <sjg@chromium.org> |
dm: Use dev_get_addr() where possible This is a convenient way for a driver to get the hardware address of a device, when regmap or syscon are not being used. Change existing callers to use it as an example to others. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> |
#
0f925822 |
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11-Aug-2015 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
of: clean up OF_CONTROL ifdef conditionals We have flipped CONFIG_SPL_DISABLE_OF_CONTROL. We have cleansing devices, $(SPL_) and CONFIG_IS_ENABLED(), so we are ready to clear away the ugly logic in include/fdtdec.h: #ifdef CONFIG_OF_CONTROL # if defined(CONFIG_SPL_BUILD) && !defined(SPL_OF_CONTROL) # define OF_CONTROL 0 # else # define OF_CONTROL 1 # endif #else # define OF_CONTROL 0 #endif Now CONFIG_IS_ENABLED(OF_CONTROL) is the substitute. It refers to CONFIG_OF_CONTROL for U-boot proper and CONFIG_SPL_OF_CONTROL for SPL. Also, we no longer have to cancel CONFIG_OF_CONTROL in include/config_uncmd_spl.h and scripts/Makefile.spl. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> |
#
6e780c7a |
|
23-Jun-2015 |
Simon Glass <sjg@chromium.org> |
ns16550: Improve debug UART so it can work with 32-bit access Since Rockchip requires 32-bit serial access, add this to the driver. Refactor a little to make this easier. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
90914008 |
|
12-May-2015 |
Simon Glass <sjg@chromium.org> |
dm: ns16550: Support CONFIG_SYS_NS16550_MEM32 with driver model This option is used by some boards, so support it with driver model. This is really ugly - we should rewrite this driver once all users are moved to driver model. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4f60166c |
|
24-Apr-2015 |
Axel Lin <axel.lin@ingics.com> |
serial: ns16550: Remove hard-coded baud_divisor setting This was accidentally added by commit dd0b0122bacc "serial: ns16550: Add an option to specify the debug UART register shift". Remove it. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
ab9fd2e8 |
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27-Feb-2015 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Remove unnecessary init on UART setup It is not necessary to write a zero baud rate to the device, and for some chips this will cause problems. Drop this code. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
363e6da1 |
|
27-Feb-2015 |
Simon Glass <sjg@chromium.org> |
dm: ns16550: Support non-byte register spacing with driver model Allow this driver to support boards where the register shift is not 0. This fixes some compiler warnings which appear in that case. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
dd0b0122 |
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27-Feb-2015 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Add an option to specify the debug UART register shift This UART permits different register spacing. To support the debug UART on devices which have a spacing other than 1 byte, allow the shift value to be specified. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
0eb25b61 |
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22-Mar-2015 |
Joe Hershberger <joe.hershberger@ni.com> |
common: Make sure arch-specific map_sysmem() is defined In the case where the arch defines a custom map_sysmem(), make sure that including just mapmem.h is sufficient to have these functions as they are when the arch does not override it. Also split the non-arch specific functions out of common.h Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
20379c11 |
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28-Feb-2015 |
Axel Lin <axel.lin@ingics.com> |
serial: ns16550: Fix build error due to a typo Fix trivial typo. Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Axel Lin <axel.lin@ingics.com> |
#
21d00436 |
|
26-Jan-2015 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support debug UART Add debug UART functions to permit ns16550 to provide an early debug UART. Try to avoid using the stack so that this can be called from assembler before a stack is set up (at least on ARM and PowerPC). Signed-off-by: Simon Glass <sjg@chromium.org> |
#
76571674 |
|
26-Jan-2015 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Add access functions that don't need platdata For the debug UART we need to be able to provide any parameters before driver model is set up. Add parameters to the low-level access functions to make this possible. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
3db886a5 |
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31-Dec-2014 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Support ns16550 compatible pci uart devices There are many pci uart devices which are ns16550 compatible. We can describe them in the board dts file and use it as the U-Boot serial console as specified in the chosen node 'stdout-path' property. Those pci uart devices can have their register be memory-mapped, or i/o-mapped. The driver will try to use the memory-mapped register if the reg property in the node has an entry to describe the memory-mapped register, otherwise i/o-mapped register will be used. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
956a8bae |
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10-Nov-2014 |
Gregoire Gentil <gregoire@gentil.com> |
ns16550.c: Fix for ns16550 driver hanging on OMAP4 The same problem that is seen on some OMAP3 is also seen on some OMAP4 so include them in the test in order to prevent some hangs during SPL. [trini: Re-word commit message, make apply cleanly] Signed-off-by: Tom Rini <trini@ti.com> |
#
1f77690e |
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10-Oct-2014 |
Simon Glass <sjg@chromium.org> |
dm: serial: ns16550: Add a cast to the I/O operations This generates a warning when driver model is enabled, so fix it by adding a cast. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
11c1a878 |
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22-Oct-2014 |
Simon Glass <sjg@chromium.org> |
dm: ns16550: Correct the probe logic for platform data The probe logic sets up the pointer to the platform data in the device tree decode method. It should be done in the probe() method, and anyway the device tree decode method can't be used when CONFIG_OF_CONTROL is not enabled. Fix these two problems. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@ti.com> |
#
167efe01 |
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22-Oct-2014 |
Simon Glass <sjg@chromium.org> |
dm: ns16550: Use an address instead of a pointer for the uart base It is inconvenient to have to use casts when specifying platform data. Also it is not strictly correct, since we should use map_sysmem() to convert an address to a pointer. Adjust the platform data to use an address. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@ti.com> |
#
aea2be20 |
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22-Oct-2014 |
Simon Glass <sjg@chromium.org> |
dm: serial: ns16550: Correct logic for checking for character There is a bug in the logic which checks for an available character. This can cause invalid characters to be received - this was noticed on beaglebone. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@ti.com> |
#
12e431b2 |
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04-Sep-2014 |
Simon Glass <sjg@chromium.org> |
dm: serial: Add driver model support for ns16550 Add driver model support so that ns16550 can support operation both with and without driver model. The driver needs a clock frequency so cannot stand alone unfortunately. The clock frequency must be provided by a separate driver. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8bbe33c8 |
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04-Sep-2014 |
Simon Glass <sjg@chromium.org> |
dm: serial: Collect common baud rate code in ns16550 The same sequence is used in several places, so move it into a function. Note that UART_LCR_BKSE is an alias for UART_LCR_DLAB. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
fa54eb12 |
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04-Sep-2014 |
Simon Glass <sjg@chromium.org> |
dm: serial: Move baud rate calculation to ns16550.c Move the function that calculates the baud rate divisor into ns16550.c so it can be used by that file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8ac22a60 |
|
30-Jul-2014 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
omap: clean-up dead configs The following configs are not defined at all. - CONFIG_OMAP1510 - CONFIG_OMAP_1510P1 - CONFIG_OMAP_SX1 - CONFIG_OMAP3_DMA - CONFIG_OMAP3_ZOOM2 - CONFIG_OMAP_INNOVATOR Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Tom Rini <trini@ti.com> |
#
7c387646 |
|
15-Jul-2014 |
Khoronzhuk, Ivan <ivan.khoronzhuk@ti.com> |
keystone2: use CONFIG_SOC_KEYSTONE in common places Use CONFIG_SOC_KEYSTONE in common places instead of defining a lot of "if def .. || if def " for different Keystone2 SoC types. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> |
#
d57dee57 |
|
09-Apr-2014 |
Karicheri, Muralidharan <m-karicheri2@ti.com> |
serial: nsl16550: add hw flow control support keystone serial hw support hw flow control. This patch enables hw flow control for keystone EVMs as an optional feature based on CONFIG_SERIAL_HW_FLOW_CONTROL. Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> |
#
ef509b90 |
|
04-Apr-2014 |
Vitaly Andrianov <vitalya@ti.com> |
k2hk: add support for k2hk SOC and EVM k2hk EVM is based on Texas Instruments Keystone2 Hawking/Kepler SoC. Keystone2 SoC has ARM v7 Cortex-A15 MPCore processor. Please refer the ti/k2hk_evm/README for details on the board, build and other information. This patch add support for keystone architecture and k2hk evm. Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: WingMan Kwok <w-kwok2@ti.com> Signed-off-by: Sandeep Nair <sandeep_n@ti.com> |
#
456ccfdf |
|
20-Dec-2013 |
Tom Rini <trini@konsulko.com> |
TI:omap3: Drop omap3_zoom2 The omap3_zoom2 board has not been updated for a correct CONFIG_SYS_HZ and Tom Rix's email has long been bouncing. Signed-off-by: Tom Rini <trini@ti.com> |
#
9ed6e412 |
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01-Jul-2013 |
TENART Antoine <atenart@adeneo-embedded.com> |
Prepare for TI816X : reuse existing code from TI814X Rename some CONFIG_TI814X to a more generic CONFIG_TI81XX Signed-off-by: Antoine Tenart <atenart@adeneo-embedded.com> [trini: Adapt for CONFIG_OMAP_COMMON changes, AM43XX] Signed-off-by: Tom Rini <trini@ti.com> |
#
57180408 |
|
30-Jul-2013 |
Lokesh Vutla <lokeshvutla@ti.com> |
ARM: AM43xx: Add build support Add AM43xx support in the required places Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> |
#
7f5eef93 |
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03-Jun-2013 |
Tom Rini <trini@konsulko.com> |
arm: Remove OMAP2420H4 and all omap24xx support The omap2420H4 was the only mainline omap24xx board. Prior to being fixed by Jon Hunter in time for v2013.04 it had been functionally broken for a very long time. Remove this board as there's not been interest in it in U-Boot for quite a long time. Signed-off-by: Tom Rini <trini@ti.com> |
#
fd2aeac5 |
|
28-Mar-2013 |
Manfred Huber <man.huber@arcor.de> |
omap3_beagle: Flush UART3 xmit on enable if TEMT is broken Flush UART3 xmit on enable if TEMT is broken On some OMAP3 devices when UART3 is configured for boot mode before SPL starts only THRE bit is set. We have to empty the transmitter before initialization starts. This patch avoids the use of CONFIG_SYS_NS16550_BROKEN_TEMT. Signed-off-by: Manfred Huber <man.huber@arcor.de> Tested-by: Javier Martinez Canillas <javier@dowhile0.org> Tested-by: Andreas Bießmann <andreas.devel@googlemail.com> |
#
6213a68f |
|
15-Mar-2013 |
Matt Porter <mporter@ti.com> |
ns16550: enable quirks for ti814x TI814X requires the same quirks as AM33XX to be enabled. Signed-off-by: Matt Porter <mporter@ti.com> Reviewed-by: Tom Rini <trini@ti.com> |
#
69e06832 |
|
05-Mar-2013 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Remove unwanted cast This cast does not seem correct, since we should be writing to a pointer, not a ulong. This fixes the following warning on nds32: -ns16550.c:49: warning: passing argument 2 of 'writeb' makes pointer from integer without a cast Signed-off-by: Simon Glass <sjg@chromium.org> |
#
7de0fe1a |
|
06-Jan-2013 |
Javier Martinez Canillas <javier@dowhile0.org> |
serial/ns16550: add an option to avoid hanging on broken platforms Some platforms (e.g. IGEPv2 board) has a broken ns16550 UART that does not set the TEMT bit when the transmitter is empty in SPL. This makes U-Boot to hang while waiting for TEMT to be set. Add a new option to avoid this: CONFIG_SYS_NS16550_BROKEN_TEMT 16550 UART set the Transmitter Empty (TEMT) Bit when all output has finished and the transmitter is totally empty. U-Boot waits for this bit to be set to initialize the serial console. On some broken platforms this bit is not set in SPL making U-Boot to hang while waiting for TEMT. Define this option to avoid it. Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> |
#
cb55b332 |
|
18-Sep-2012 |
Scott Wood <scottwood@freescale.com> |
serial/ns16550: wait for TEMT before initializing TEMT is set when the transmitter is totally empty and all output has finished. This prevents output problems (including a loss of synchronization observed on p2020 that persisted for quite a while) if SPL has output still on its way out. Signed-off-by: Scott Wood <scottwood@freescale.com> -- v2: fixed typo in subject, and explained what the bit does in the changelog |
#
f2041388 |
|
15-Sep-2012 |
Marek Vasut <marex@denx.de> |
serial: ns16550: Call usbtty_poll only in non-SPL build Having both USBTTY and CONFIG_SERIAL_MULTI enabled in SPL, the usbtty.c file is protected in Makefile to not be compiled into the SPL. Yet, the ns16550 serial driver does not contain such protection. Add it to avoid missing symbol error. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Marek Vasut <marek.vasut@gmail.com> Cc: Tom Rini <trini@ti.com> |
#
99b603e7 |
|
09-Jul-2012 |
Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com> |
serial/ns16550: ns16550 has a different register layout on SOC_DA8XX also fix NS16550_init() as we need 16x divider Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com> Acked-by: Christian Riesch <christian.riesch@omicron.at> Tested-by: Christian Riesch <christian.riesch@omicron.at> Acked-by: Sughosh Ganu <urwithsughosh@gmail.com> Tested-by: Sughosh Ganu <urwithsughosh@gmail.com> |
#
5289e83a |
|
13-Oct-2011 |
Chandan Nath <chandan.nath@ti.com> |
ARM:AM33XX: Add support for TI AM335X EVM This patch adds basic support for booting the board. This patch adds support for the UART necessary to get to the u-boot prompt. Signed-off-by: Chandan Nath <chandan.nath@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> |
#
f8df9d0d |
|
15-Oct-2011 |
Simon Glass <sjg@chromium.org> |
NS16550: trivial code clean for checkpatch This removes most checkpatch warnings from the ns16550 driver and its header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
79df1208 |
|
01-Sep-2011 |
Dave Aldridge <fovsoft@gmail.com> |
ns16550: change to allow 32 bit access to registers If CONFIG_SYS_NS16550_MEM32 is defined then 32 bit memory mapped access will be used to read/write the uart registers. This is especially useful for SoC devices that implement 16550 compatible uarts but that have peripheral access width constraints. Signed-off-by: Dave Aldridge <fovsoft@gmail.com> |
#
a160ea0b |
|
27-Oct-2010 |
Prafulla Wadaskar <prafulla@marvell.com> |
Serial: ns16550: Add support for CONFIG_SYS_NS16550_IER macro On some processors this ier register configuration is different for ex. Marvell Armada100 This patch introduce CONFIG_SYS_NS16550_IER macro support to unconditionally initialize this register. Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com> |
#
1a2d9b30 |
|
12-Oct-2010 |
Stefan Roese <sr@denx.de> |
ns16550: Add WATCHDOG_RESET to putc for short watchdog timeout boards Call watchdog_reset() upon newline. This is done here in putc since the environment code uses a single puts() to print the complete envrironment upon "printenv". So we can't put this watchdog call in puts(). This is needed for boards with a very short watchdog timeout, like the lwmon5 with a 100ms timeout. Without this patch this board resets in the commands with long outputs, like "printenv" or "fdt print". Note that the image size is not increased with this patch when CONFIG_HW_WATCHDOG or CONFIG_WATCHDOG are not defined since the compiler optimizes this additional code away. Signed-off-by: Stefan Roese <sr@denx.de> Fix typo in comment. Signed-off-by: Wolfgang Denk <wd@denx.de> |
#
167cdad1 |
|
23-Apr-2010 |
Graeme Russ <graeme.russ@gmail.com> |
SERIAL: Enable port-mapped access The x86 architecture exclusively uses Port-Mapped I/O (inb/outb) to access the 16550 UARTs. This patch mimics how Linux selects between Memory-Mapped and Port-Mapped I/O. This allows x86 boards to use CONFIG_SERIAL_MUTLI and drop the custom serial port driver Signed-off-by: Graeme Russ <graeme.russ@gmail.com> |
#
a47a12be |
|
15-Apr-2010 |
Stefan Roese <sr@denx.de> |
Move arch/ppc to arch/powerpc As discussed on the list, move "arch/ppc" to "arch/powerpc" to better match the Linux directory structure. Please note that this patch also changes the "ppc" target in MAKEALL to "powerpc" to match this new infrastructure. But "ppc" is kept as an alias for now, to not break compatibility with scripts using this name. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Wolfgang Denk <wd@denx.de> Acked-by: Detlev Zundel <dzu@denx.de> Acked-by: Kim Phillips <kim.phillips@freescale.com> Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Anatolij Gustschin <agust@denx.de> |
#
a1b322a9 |
|
01-Feb-2010 |
Ladislav Michl <ladis@linux-mips.org> |
ns16550: kick watchdog while waiting for a character ns16550 busyloops waiting for incoming byte causing watchdog to reboot while waiting for a key press. A call to WATCHDOG_RESET in NS16550_getc loop fixes it. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> |
#
660888b7 |
|
30-May-2009 |
Tom Rix <Tom.Rix@windriver.com> |
ZOOM2 Add serial support. Zoom2 serial is in general supplied by one of the 4 UARTS on the debug board. The default serial is from the USB connector on left side of the debug board. The USB connector will produce 2 of the 4 UARTS. On your host pick the first enumeration. The details of the setting of the serial gpmc setup are not available. The values were provided by another party. The serial port set up is the same with Zoom1. Baud rate 115200, 8 bit data, no parity, 1 stop bit, no flow. The kernel bootargs are console=ttyS3,115200n8 Signed-off-by: Tom Rix <Tom.Rix@windriver.com> |
#
200779e3 |
|
03-Apr-2009 |
Detlev Zundel <dzu@denx.de> |
Rename common ns16550 constants with UART_ prefix to prevent conflicts Fix problems introduced in commit 7b5611cdd12ca0cc33f994f0d4a4454788fc3124 [inka4x0: Add hardware diagnosis functions for inka4x0] which redefined MSR_RI which is already used on PowerPC systems. Also eliminate redundant definitions in ps2mult.h. More cleanup will be needed for other redundant occurrences though. Signed-off-by: Detlev Zundel <dzu@denx.de> |
#
b4746d8b |
|
11-Feb-2009 |
Mike Frysinger <vapier@gentoo.org> |
drivers/serial/ns16550: move ifdef into Makefile COBJS-$(...) Signed-off-by: Mike Frysinger <vapier@gentoo.org> |
#
f5675aa5 |
|
18-Feb-2009 |
Ron Madrid <ron_madrid@sbcglobal.net> |
Create configuration option for restricted ns16550 functions This patch will create a configuration option for a minimum configuration for the ns16550 serial driver at drivers/serial/ns16550.c and will apply this new configuration option to the SIMPC8313.h config file in order to fix the NAND bootstrap build error. This option will exclude all functions with exception of NS16550_putc and NS16550_init. This will be used primarily to save space and remove unused code from builds in which space is limited. Signed-off-by: Ron Madrid <ron_madrid@sbcglobal.net> |
#
6d0f6bcf |
|
16-Oct-2008 |
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
rename CFG_ macros to CONFIG_SYS Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
#
7ec8bb15 |
|
27-Dec-2007 |
Wolfgang Denk <wd@denx.de> |
OMAP5912: fix FIFO handling in UART driver According to the OMAP5912 Serial Interfaces Reference Guide (see http://focus.ti.com/lit/ug/spru760c/spru760c.pdf, page 150), the FIFO_EN enable bit in the FIFO Control Register (FCR) can only be changed when the baud clock is not running, i. e. when both DLL and DLH are set to 0. Thus make sure that DLL and DLH are 0 when writing the FCR. Signed-off-by: Wolfgang Denk <wd@denx.de> |
#
1378df79 |
|
24-Nov-2007 |
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
drivers/serial : move serial drivers to drivers/serial Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
#
f899cc14 |
|
12-Sep-2021 |
Tom Rini <trini@konsulko.com> |
ti: keystone: Move away from CONFIG_SOC_KEYSTONE We have individual SOC symbols for each keystone 2 platform. Use the existing CONFIG_ARCH_KEYSTONE rather than CONFIG_SOC_KEYSTONE to encompass all of the keystone families. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
414cc151 |
|
07-Aug-2021 |
Simon Glass <sjg@chromium.org> |
treewide: Simply conditions with the new OF_REAL Use this new Kconfig to simplify the compilation conditions where appropriate. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
384b62c0 |
|
03-Feb-2021 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Handle zero <clock-frequency> value A working device tree node of ns16550 should never be populated with value zero for the <clock-frequency> property. Unfortunately this is the case for the QEMU ppce500 target. Let's try to assign plat->clock to CONFIG_SYS_NS16550_CLK as the last resort to handle such case. This commit should be reverted when: - The following QEMU patch [1] is merged, and - U-Boot CI has upgraded its QEMU version that contains the fix [1] http://patchwork.ozlabs.org/project/qemu-devel/patch/1612362288-22216-2-git-send-email-bmeng.cn@gmail.com/ Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
09bd0840 |
|
03-Feb-2021 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Correct the base address type Currently ns16550_serial_assign_base() treats the argument 'base' with type `ulong`. This is incorrect because the base address was obtained from device tree with type `fdt_addr_t` that can represent a physical address larger than 32-bit in a 32-bit system. Fixes: 9e6ce62190b7 ("serial: ns16550: Fix ordering of getting base address") Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
401d1c4f |
|
30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
bdf8fd76 |
|
28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
0fd3d911 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com> |
#
2d6bf754 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
#
d30c7209 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo |
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de> |
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> |
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se> |
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> |
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4e720779 |
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20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com |
#
9ad3b049 |
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02-Nov-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: add setconfig support Add possibility to update the serial parity used. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com> |
#
46879196 |
|
24-Oct-2018 |
Bin Meng <bmeng.cn@gmail.com> |
serial: Remove DM_FLAG_PRE_RELOC flag in various drivers When a driver declares DM_FLAG_PRE_RELOC flag, it wishes to be bound before relocation. However due to a bug in the DM core, the flag only takes effect when devices are statically declared via U_BOOT_DEVICE(). This bug has been fixed recently by commit "dm: core: Respect drivers with the DM_FLAG_PRE_RELOC flag in lists_bind_fdt()", but with the fix, it has a side effect that all existing drivers that declared DM_FLAG_PRE_RELOC flag will be bound before relocation now. This may expose potential boot failure on some boards due to insufficient memory during the pre-relocation stage. To mitigate this potential impact, the following changes are implemented: - Remove DM_FLAG_PRE_RELOC flag in the driver, if the driver only supports configuration from device tree (OF_CONTROL) - Keep DM_FLAG_PRE_RELOC flag in the driver only if the device is statically declared via U_BOOT_DEVICE() - Surround DM_FLAG_PRE_RELOC flag with OF_CONTROL check, for drivers that support both statically declared devices and configuration from device tree Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
6f57c344 |
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09-Aug-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), let's rather ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
5d754197 |
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27-Aug-2018 |
Lokesh Vutla <lokeshvutla@ti.com> |
serial: omap: Introduce DM specific omap serial Add driver model support for OMAP_SERIAL while reusing the functions in ns16550.c Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Tested-by: Derald D. Woods <woods.technical@gmail.com> |
#
b051eecb |
|
14-Jun-2018 |
Ley Foon Tan <ley.foon.tan@intel.com> |
serial: ns16550: Add reset ctrl to driver Add code to reset all reset signals as in serial DT node. A reset property is an optional feature, so do not fail if a reset property is not present. If a reset property is discovered, then use it to deassert, thus bringing the IP out of reset. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
78b7d37b |
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15-Feb-2018 |
Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> |
ns16550: Fix mem mapped endian check Do a explicit check for CONFIG_SYS_BIG_ENDIAN and CONFIG_SYS_LITTLE_ENDIAN to avoid errors on platforms where both are undefined (x86). Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> Reviewed-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com> |
#
4dbf9bed |
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15-Jan-2018 |
Mario Six <mario.six@gdsys.cc> |
serial: ns16550: Fix style violation Clarify the computation precedence in two ternary operator constructions. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc> |
#
7fded0ce |
|
16-Aug-2017 |
Stefan Roese <sr@denx.de> |
Revert "serial: ns16550: Add RX interrupt buffer support" This reverts commit 6822cf3ec7c8768b8727573b8f4b2cb3d870b881. As Bin Meng has tested and pointed out, we don't need the RX interrupt for the RX buffer support at all. Just reading all available characters into a buffer is sufficient to solve the problem with the dropped characters upon long lines pasted into the U-Boot prompt. Since this RX buffer support can be implemented in a generic way, without any device specifica (e.g. for the ns16550), I'll post a new patch with a new serial RX buffer support for DM, which all DM based serial drivers can use. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
6822cf3e |
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14-Jul-2017 |
Stefan Roese <sr@denx.de> |
serial: ns16550: Add RX interrupt buffer support Pasting longer lines into the U-Boot console prompt sometimes leads to characters missing. One problem here is the small 16-byte FIFO of the legacy NS16550 UART, e.g. on x86 platforms. This patch now introduces a Kconfig option to enable RX interrupt buffer support for NS16550 style UARTs. With this option enabled, I was able paste really long lines into the U-Boot console, without any characters missing. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> [trini: Guard ns16550_serial_remove with CONFIG_IS_ENABLED(SERIAL_PRESENT) to match struct assignment] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
8d3a2568 |
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11-Jul-2017 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-dm
|
#
db9f8f6a |
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12-Jun-2017 |
Simon Glass <sjg@chromium.org> |
dm: serial: ns16550: Convert to livetree Update this driver to support a live device tree. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Tested-on: Beaver, Jetson-TK1 |
#
3d40479f |
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07-Jun-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
rockchip: ns16550: dm: convert fdt_get to dev_read With the new dev_read functions available, we can convert the rockchip architecture-specific drivers and common drivers used by these devices over to the dev_read family of calls. This covers the serial driver (ns16550 and compatible) used for the Rockchip devices. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
a821c4af |
|
17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: Rename dev_addr..() functions These support the flat device tree. We want to use the dev_read_..() prefix for functions that support both flat tree and live tree. So rename the existing functions to avoid confusion. In the end we will have: 1. dev_read_addr...() - works on devices, supports flat/live tree 2. devfdt_get_addr...() - current functions, flat tree only 3. of_get_address() etc. - new functions, live tree only All drivers will be written to use 1. That function will in turn call either 2 or 3 depending on whether the flat or live tree is in use. Note this involves changing some dead code - the imx_lpi2c.c file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
89024ddc |
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12-May-2017 |
Tom Rini <trini@konsulko.com> |
TI: Drop 'CONFIG_OMAP' In the two cases in the code where we use CONFIG_OMAP as a useful test currently we can make use of CONFIG_ARCH_OMAP2PLUS instead. With that changed we can drop all defines of CONFIG_OMAP. While in here, CONFIG_OMAP3430 is only defined and then never used, so drop. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
a52cf086 |
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22-Apr-2017 |
Lokesh Vutla <lokeshvutla@ti.com> |
serial: omap: Support debug UART Add debug UART functions to permit omap specific ns16550 to provide an early debug UART. This is mostly in common with DEBUG_UART_NS16550 except for Mode definition register which is required for selecting UART mode(16x auto-baud or 13x mode). Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
6f8c351e |
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27-Mar-2017 |
Alexandru Gagniuc <alex.g@adaptrum.com> |
serial: ns16550: Link in the DM driver when when using platdata Do not condition the compilation of the U_BOOT_DRIVER by !OF_PLATDATA. This is inconsistent with the majority of other drivers. This also blocks OF_PLATDATA boards with an 16550-compatible serial from using serial in SPL. Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com> Reviewed-by: Simon Glass <sjg@chromium.org> Added tweak for rock to avoid a TPL build failure: Signed-off-by: Simon Glass <sjg@chromium.org> |
#
e160f7d4 |
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17-Jan-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
17fa0326 |
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18-Jan-2017 |
Heiko Schocher <hs@denx.de> |
serial, ns16550: bugfix: ns16550 fifo not enabled commit: 65f83802b7a5b "serial: 16550: Add getfcr accessor" breaks u-boot commandline working with long commands sending to the board. Since the above patch, you have to setup the fcr register. For board/archs which enable OF_PLATDATA, the new field fcr in struct ns16550_platdata is not filled with a default value ... This leads in not setting up the uarts fifo, which ends in problems, when you send long commands to u-boots commandline. Detected this issue with automated tbot tests on am335x based shc board. The error does not popup, if you type commands. You need to copy&paste a long command to u-boots commandshell (or send a long command with tbot) Possible boards/plattforms with problems: ./arch/arm/cpu/arm926ejs/lpc32xx/devices.c ./arch/arm/mach-tegra/board.c ./board/overo/overo.c ./board/quipos/cairo/cairo.c ./board/logicpd/omap3som/omap3logic.c ./board/logicpd/zoom1/zoom1.c ./board/timll/devkit8000/devkit8000.c ./board/lg/sniper/sniper.c ./board/ti/beagle/beagle.c ./drivers/serial/serial_rockchip.c Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Tested-by: Adam Ford <aford173@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
0b060eef |
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30-Nov-2016 |
Marek Vasut <marex@denx.de> |
serial: 16550: Add Ingenic JZ4780 support Add compatibility string for the Ingenic JZ4780 SoC, the necessary UART enable bit into FCR and register shift. Neither are encoded in the DTS coming from Linux, so we need to support it this way. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
79fd9281 |
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30-Nov-2016 |
Marek Vasut <marex@denx.de> |
serial: 16550: Add port type as driver data Add driver data to each compatible string to identify the type of the port. Since all the ports in the driver are entirely compatible with 16550 for now, all are marked with PORT_NS16550. But, there are ports which have specific quirks, like the JZ4780 UART, which do not have any DT property to denote the quirks. Instead, Linux uses the compatible string to discern such ports and enable the necessary quirks. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> |
#
65f83802 |
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30-Nov-2016 |
Marek Vasut <marex@denx.de> |
serial: 16550: Add getfcr accessor Add function which allows fetching the default FCR register setting from platform data for DM , while retaining old behavior for non-DM by returning UART_FCRVAL. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
021abf69 |
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26-Sep-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
Revert "ns16650: Make sure we have CONFIG_CLK set before using infrastructure" This reverts commit 82f5279b0cd99a9163d34cfe926d0316d9dc0d37. The build failure of k2*evm boards was fixed in a different way by the previous commit. It is nasty to patch generic drivers around with #ifdef CONFIG_CLK just for the KeyStone's matter. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
ab895d6a |
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30-Sep-2016 |
Alexandre Courbot <acourbot@nvidia.com> |
serial: ns16550: Handle -ENOENT when requesting clock When calling clk_get_by_index(), fall back to the legacy method of getting the clock if -ENOENT is returned. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> |
#
82f5279b |
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22-Sep-2016 |
Tom Rini <trini@konsulko.com> |
ns16650: Make sure we have CONFIG_CLK set before using infrastructure We cannot call on the CONFIG_CLK based clk_get_rate function unless CONFIG_CLK is set. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
50fce1d5 |
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08-Sep-2016 |
Paul Burton <paul.burton@mips.com> |
serial: ns16550: Support clocks via phandle Previously ns16550 compatible UARTs probed via device tree have needed their device tree nodes to contain a clock-frequency property. An alternative to this commonly used with Linux is to reference a clock via a phandle. This patch allows U-Boot to support that, retrieving the clock frequency by probing the appropriate clock device. For example, a system might choose to provide the UART base clock as a reference to a clock common to multiple devices: sys_clk: clock { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <10000000>; }; uart0: uart@10000000 { compatible = "ns16550a"; reg = <0x10000000 0x1000>; clocks = <&sys_clk>; }; uart1: uart@10000000 { compatible = "ns16550a"; reg = <0x10001000 0x1000>; clocks = <&sys_clk>; }; This removes the need for the frequency information to be duplicated in multiple nodes and allows the device tree to be more descriptive of the system. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
b2927fba |
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04-Jul-2016 |
Simon Glass <sjg@chromium.org> |
dm: serial: ns16550: Update to support of-platdata With of-platdata this driver cannot know the format of the of-platdata struct, so we cannot use generic code for accessing the of-platdata. Each SoC that uses this driver will need to set up ns16550's platdata for it. So don't compile in the generic code. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
03c6f176 |
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24-May-2016 |
Marek Vasut <marex@denx.de> |
serial: 16550: Drop OMAP1510 support The CONFIG_OMAP1510 is no longer defined, so remove this dead code. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Nishanth Menon <nm@ti.com> |
#
fa4ce723 |
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24-May-2016 |
Marek Vasut <marex@denx.de> |
serial: 16550: Make serial_io/out_shift available to debug mode The ns16550 driver needs serial_in_shift() and serial_out_shift() when compiled in debug UART mode, so shift the DM_SERIAL check a little to make these functions available. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
df8ec55d |
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17-May-2016 |
Paul Burton <paul.burton@mips.com> |
dm: ns16550: Don't map_physmem for I/O ports If the UART is to be accessed using I/O port accessors (inb & outb) then using map_physmem doesn't make sense, since it operates in a different memory space. Remove the call to map_physmem when CONFIG_SYS_NS16550_PORT_MAPPED is defined, allowing I/O port addresses to not be mangled by the incorrect mapping. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> |
#
59b35ddd |
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16-Feb-2016 |
Michal Simek <michal.simek@xilinx.com> |
dm: ns16550: Add support for reg-offset property reg-offset is the part of standard 8250 binding in the kernel. It is shifting start of address space by reg-offset. On Xilinx platform this offset is typically 0x1000. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Moved the new field to the end of the struct to avoid problems: Signed-off-by: Simon Glass <sjg@chromium.org> |
#
e5e88c65 |
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29-Feb-2016 |
Tom Rini <trini@konsulko.com> |
Revert "dm: ns16550: Add support for reg-offset property" This reverts commit d9a3bec682f9756621615f4306718a356a3230e3. While this is a correct change to do long term it unfortunately breaks a number of platforms that are using pdata and not named struct members so they are getting all of their data after 'base' incorrect. Acked-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
d9a3bec6 |
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16-Feb-2016 |
Michal Simek <michal.simek@xilinx.com> |
dm: ns16550: Add support for reg-offset property reg-offset is the part of standard 8250 binding in the kernel. It is shifting start of address space by reg-offset. On Xilinx platform this offset is typically 0x1000. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
cc4228f9 |
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14-Dec-2015 |
Thomas Chou <thomas@wytron.com.tw> |
ns16550: zap the rockchip serial compatible string Zap the rockchip serial compatible string, because rockchip serial has "snps,dw-apb-uart" compatible string in the dts. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org> |
#
b7e29834 |
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13-Dec-2015 |
Simon Glass <sjg@chromium.org> |
dm: ns16550: Allow the driver to be omitted if requested Allow the ns16550 debug UART to be used without the full driver. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Thomas Chou <thomas@wytron.com.tw> |
#
fcc0a877 |
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29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: serial: Convert ns16550 driver to use driver model PCI API Use the driver model version of the function to find the BAR. This updates the fdtdec function, of which ns16550 is the only user. The fdtdec_get_pci_bdf() function is dropped for several reasons: - with driver model we should use 'struct udevice *' rather than passing the device tree offset explicitly - there are no other users in the tree - the function parses for information which is already available in the PCI device structure (specifically struct pci_child_platdata which is available at dev_get_parent_platdata(dev) Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> |
#
b7e5a643 |
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04-Dec-2015 |
Simon Glass <sjg@chromium.org> |
dm: serial: ns16550: Add pre-reloc flag to the driver For platforms that don't use device tree in SPL the only way to mark this driver as 'required by relocation' is with the DM_FLAG_PRE_RELOC flag. Add this to ensure that the driver is bound. Fixes: fde7e18938d8 ("dm: tegra: pci: Move CONFIG_PCI_TEGRA to Kconfig") Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Stephen Warren <swarren@nvidia.com> Acked-by: Thomas Chou <thomas@wytron.com.tw> |
#
80e06146 |
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28-Nov-2015 |
Thomas Chou <thomas@wytron.com.tw> |
ns16550: change reg-shift property default to zero Change reg-shift property default to zero. When the integer property is missing, it should be taken as zero. This is consistent to Linux drivers/tty/serial/of_serial.c. The x86 and most powerpc use reg-shift of 0. Most others use reg-shift of 2. While reg-shift of 1 is rarely used. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
a51dbebf |
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16-Nov-2015 |
huang lin <hl@rock-chips.com> |
rockchip: serial driver support rk3036 Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
4fb60552 |
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19-Nov-2015 |
Thomas Chou <thomas@wytron.com.tw> |
ns16550: zap CONFIG_NS16550_SERIAL Zap CONFIG_NS16550_SERIAL, as the unification of ns16550 drivers is completed. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
8e62d32e |
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19-Nov-2015 |
Thomas Chou <thomas@wytron.com.tw> |
ns16550: add generic binding to unify the drivers Add generic binding to unify ns16550 drivers. There are several drivers using almost the same code, such as serial_dw, serial_keystone, serial_omap, serial_ppc, serial_rockchip, serial_tegra.c, and serial_x86. But each is platform specific. The key difference between these drivers is the way to get input clock frequency. With this unified approach, fixed clock frequency should be extracted from "clock-frequency" property of device tree blob. If this property is not available, the macro CONFIG_SYS_NS16550_CLK will be used. It can be a constant or a function to get clock, eg, get_serial_clock(). Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de> Acked-by: Simon Glass <sjg@chromium.org> |
#
77d7b5cd |
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19-Nov-2015 |
Thomas Chou <thomas@wytron.com.tw> |
ns16550: change map_sysmem to map_physmem Change map_sysmem() to map_physmem(,,MAP_NOCACHE). Though map_sysmem() can be used to map system memory, it might be wrong to use it for I/O ports. The map_physmem() serves the same purpose to translate physical address to virtual address with the additional flag to take care of cache property. Most drivers use map_physmem() since I/O ports access should be uncached. As ns16550 is a driver, it should use map_physmem() rather than map_sysmem(). Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org> |
#
97b05973 |
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18-Oct-2015 |
Simon Glass <sjg@chromium.org> |
debug_uart: Adjust the declaration of debug_uart_init() We want to be able to add other common code to this function. So change the driver's version to have an underscore before it, just like _debug_uart_putc(). Define debug_uart_init() to call this version. Update all drivers to this new method. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
4e9838c1 |
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11-Aug-2015 |
Simon Glass <sjg@chromium.org> |
dm: Use dev_get_addr() where possible This is a convenient way for a driver to get the hardware address of a device, when regmap or syscon are not being used. Change existing callers to use it as an example to others. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> |
#
0f925822 |
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11-Aug-2015 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
of: clean up OF_CONTROL ifdef conditionals We have flipped CONFIG_SPL_DISABLE_OF_CONTROL. We have cleansing devices, $(SPL_) and CONFIG_IS_ENABLED(), so we are ready to clear away the ugly logic in include/fdtdec.h: #ifdef CONFIG_OF_CONTROL # if defined(CONFIG_SPL_BUILD) && !defined(SPL_OF_CONTROL) # define OF_CONTROL 0 # else # define OF_CONTROL 1 # endif #else # define OF_CONTROL 0 #endif Now CONFIG_IS_ENABLED(OF_CONTROL) is the substitute. It refers to CONFIG_OF_CONTROL for U-boot proper and CONFIG_SPL_OF_CONTROL for SPL. Also, we no longer have to cancel CONFIG_OF_CONTROL in include/config_uncmd_spl.h and scripts/Makefile.spl. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> |
#
6e780c7a |
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23-Jun-2015 |
Simon Glass <sjg@chromium.org> |
ns16550: Improve debug UART so it can work with 32-bit access Since Rockchip requires 32-bit serial access, add this to the driver. Refactor a little to make this easier. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
90914008 |
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12-May-2015 |
Simon Glass <sjg@chromium.org> |
dm: ns16550: Support CONFIG_SYS_NS16550_MEM32 with driver model This option is used by some boards, so support it with driver model. This is really ugly - we should rewrite this driver once all users are moved to driver model. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4f60166c |
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24-Apr-2015 |
Axel Lin <axel.lin@ingics.com> |
serial: ns16550: Remove hard-coded baud_divisor setting This was accidentally added by commit dd0b0122bacc "serial: ns16550: Add an option to specify the debug UART register shift". Remove it. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
ab9fd2e8 |
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27-Feb-2015 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Remove unnecessary init on UART setup It is not necessary to write a zero baud rate to the device, and for some chips this will cause problems. Drop this code. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
363e6da1 |
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27-Feb-2015 |
Simon Glass <sjg@chromium.org> |
dm: ns16550: Support non-byte register spacing with driver model Allow this driver to support boards where the register shift is not 0. This fixes some compiler warnings which appear in that case. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
dd0b0122 |
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27-Feb-2015 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Add an option to specify the debug UART register shift This UART permits different register spacing. To support the debug UART on devices which have a spacing other than 1 byte, allow the shift value to be specified. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
0eb25b61 |
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22-Mar-2015 |
Joe Hershberger <joe.hershberger@ni.com> |
common: Make sure arch-specific map_sysmem() is defined In the case where the arch defines a custom map_sysmem(), make sure that including just mapmem.h is sufficient to have these functions as they are when the arch does not override it. Also split the non-arch specific functions out of common.h Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
20379c11 |
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28-Feb-2015 |
Axel Lin <axel.lin@ingics.com> |
serial: ns16550: Fix build error due to a typo Fix trivial typo. Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Axel Lin <axel.lin@ingics.com> |
#
21d00436 |
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26-Jan-2015 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support debug UART Add debug UART functions to permit ns16550 to provide an early debug UART. Try to avoid using the stack so that this can be called from assembler before a stack is set up (at least on ARM and PowerPC). Signed-off-by: Simon Glass <sjg@chromium.org> |
#
76571674 |
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26-Jan-2015 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Add access functions that don't need platdata For the debug UART we need to be able to provide any parameters before driver model is set up. Add parameters to the low-level access functions to make this possible. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
3db886a5 |
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31-Dec-2014 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Support ns16550 compatible pci uart devices There are many pci uart devices which are ns16550 compatible. We can describe them in the board dts file and use it as the U-Boot serial console as specified in the chosen node 'stdout-path' property. Those pci uart devices can have their register be memory-mapped, or i/o-mapped. The driver will try to use the memory-mapped register if the reg property in the node has an entry to describe the memory-mapped register, otherwise i/o-mapped register will be used. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
956a8bae |
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10-Nov-2014 |
Gregoire Gentil <gregoire@gentil.com> |
ns16550.c: Fix for ns16550 driver hanging on OMAP4 The same problem that is seen on some OMAP3 is also seen on some OMAP4 so include them in the test in order to prevent some hangs during SPL. [trini: Re-word commit message, make apply cleanly] Signed-off-by: Tom Rini <trini@ti.com> |
#
1f77690e |
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10-Oct-2014 |
Simon Glass <sjg@chromium.org> |
dm: serial: ns16550: Add a cast to the I/O operations This generates a warning when driver model is enabled, so fix it by adding a cast. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
11c1a878 |
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22-Oct-2014 |
Simon Glass <sjg@chromium.org> |
dm: ns16550: Correct the probe logic for platform data The probe logic sets up the pointer to the platform data in the device tree decode method. It should be done in the probe() method, and anyway the device tree decode method can't be used when CONFIG_OF_CONTROL is not enabled. Fix these two problems. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@ti.com> |
#
167efe01 |
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22-Oct-2014 |
Simon Glass <sjg@chromium.org> |
dm: ns16550: Use an address instead of a pointer for the uart base It is inconvenient to have to use casts when specifying platform data. Also it is not strictly correct, since we should use map_sysmem() to convert an address to a pointer. Adjust the platform data to use an address. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@ti.com> |
#
aea2be20 |
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22-Oct-2014 |
Simon Glass <sjg@chromium.org> |
dm: serial: ns16550: Correct logic for checking for character There is a bug in the logic which checks for an available character. This can cause invalid characters to be received - this was noticed on beaglebone. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@ti.com> |
#
12e431b2 |
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04-Sep-2014 |
Simon Glass <sjg@chromium.org> |
dm: serial: Add driver model support for ns16550 Add driver model support so that ns16550 can support operation both with and without driver model. The driver needs a clock frequency so cannot stand alone unfortunately. The clock frequency must be provided by a separate driver. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8bbe33c8 |
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04-Sep-2014 |
Simon Glass <sjg@chromium.org> |
dm: serial: Collect common baud rate code in ns16550 The same sequence is used in several places, so move it into a function. Note that UART_LCR_BKSE is an alias for UART_LCR_DLAB. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
fa54eb12 |
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04-Sep-2014 |
Simon Glass <sjg@chromium.org> |
dm: serial: Move baud rate calculation to ns16550.c Move the function that calculates the baud rate divisor into ns16550.c so it can be used by that file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8ac22a60 |
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30-Jul-2014 |
Masahiro Yamada <yamada.m@jp.panasonic.com> |
omap: clean-up dead configs The following configs are not defined at all. - CONFIG_OMAP1510 - CONFIG_OMAP_1510P1 - CONFIG_OMAP_SX1 - CONFIG_OMAP3_DMA - CONFIG_OMAP3_ZOOM2 - CONFIG_OMAP_INNOVATOR Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Tom Rini <trini@ti.com> |
#
7c387646 |
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15-Jul-2014 |
Khoronzhuk, Ivan <ivan.khoronzhuk@ti.com> |
keystone2: use CONFIG_SOC_KEYSTONE in common places Use CONFIG_SOC_KEYSTONE in common places instead of defining a lot of "if def .. || if def " for different Keystone2 SoC types. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> |
#
d57dee57 |
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09-Apr-2014 |
Karicheri, Muralidharan <m-karicheri2@ti.com> |
serial: nsl16550: add hw flow control support keystone serial hw support hw flow control. This patch enables hw flow control for keystone EVMs as an optional feature based on CONFIG_SERIAL_HW_FLOW_CONTROL. Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> |
#
ef509b90 |
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04-Apr-2014 |
Vitaly Andrianov <vitalya@ti.com> |
k2hk: add support for k2hk SOC and EVM k2hk EVM is based on Texas Instruments Keystone2 Hawking/Kepler SoC. Keystone2 SoC has ARM v7 Cortex-A15 MPCore processor. Please refer the ti/k2hk_evm/README for details on the board, build and other information. This patch add support for keystone architecture and k2hk evm. Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: WingMan Kwok <w-kwok2@ti.com> Signed-off-by: Sandeep Nair <sandeep_n@ti.com> |
#
456ccfdf |
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20-Dec-2013 |
Tom Rini <trini@ti.com> |
TI:omap3: Drop omap3_zoom2 The omap3_zoom2 board has not been updated for a correct CONFIG_SYS_HZ and Tom Rix's email has long been bouncing. Signed-off-by: Tom Rini <trini@ti.com> |
#
9ed6e412 |
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01-Jul-2013 |
TENART Antoine <atenart@adeneo-embedded.com> |
Prepare for TI816X : reuse existing code from TI814X Rename some CONFIG_TI814X to a more generic CONFIG_TI81XX Signed-off-by: Antoine Tenart <atenart@adeneo-embedded.com> [trini: Adapt for CONFIG_OMAP_COMMON changes, AM43XX] Signed-off-by: Tom Rini <trini@ti.com> |
#
57180408 |
|
30-Jul-2013 |
Lokesh Vutla <lokeshvutla@ti.com> |
ARM: AM43xx: Add build support Add AM43xx support in the required places Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> |
#
7f5eef93 |
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03-Jun-2013 |
Tom Rini <trini@ti.com> |
arm: Remove OMAP2420H4 and all omap24xx support The omap2420H4 was the only mainline omap24xx board. Prior to being fixed by Jon Hunter in time for v2013.04 it had been functionally broken for a very long time. Remove this board as there's not been interest in it in U-Boot for quite a long time. Signed-off-by: Tom Rini <trini@ti.com> |
#
fd2aeac5 |
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28-Mar-2013 |
Manfred Huber <man.huber@arcor.de> |
omap3_beagle: Flush UART3 xmit on enable if TEMT is broken Flush UART3 xmit on enable if TEMT is broken On some OMAP3 devices when UART3 is configured for boot mode before SPL starts only THRE bit is set. We have to empty the transmitter before initialization starts. This patch avoids the use of CONFIG_SYS_NS16550_BROKEN_TEMT. Signed-off-by: Manfred Huber <man.huber@arcor.de> Tested-by: Javier Martinez Canillas <javier@dowhile0.org> Tested-by: Andreas Bießmann <andreas.devel@googlemail.com> |
#
6213a68f |
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15-Mar-2013 |
Matt Porter <mporter@ti.com> |
ns16550: enable quirks for ti814x TI814X requires the same quirks as AM33XX to be enabled. Signed-off-by: Matt Porter <mporter@ti.com> Reviewed-by: Tom Rini <trini@ti.com> |
#
69e06832 |
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05-Mar-2013 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Remove unwanted cast This cast does not seem correct, since we should be writing to a pointer, not a ulong. This fixes the following warning on nds32: -ns16550.c:49: warning: passing argument 2 of 'writeb' makes pointer from integer without a cast Signed-off-by: Simon Glass <sjg@chromium.org> |
#
7de0fe1a |
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06-Jan-2013 |
Javier Martinez Canillas <javier@dowhile0.org> |
serial/ns16550: add an option to avoid hanging on broken platforms Some platforms (e.g. IGEPv2 board) has a broken ns16550 UART that does not set the TEMT bit when the transmitter is empty in SPL. This makes U-Boot to hang while waiting for TEMT to be set. Add a new option to avoid this: CONFIG_SYS_NS16550_BROKEN_TEMT 16550 UART set the Transmitter Empty (TEMT) Bit when all output has finished and the transmitter is totally empty. U-Boot waits for this bit to be set to initialize the serial console. On some broken platforms this bit is not set in SPL making U-Boot to hang while waiting for TEMT. Define this option to avoid it. Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> |
#
cb55b332 |
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18-Sep-2012 |
Scott Wood <scottwood@freescale.com> |
serial/ns16550: wait for TEMT before initializing TEMT is set when the transmitter is totally empty and all output has finished. This prevents output problems (including a loss of synchronization observed on p2020 that persisted for quite a while) if SPL has output still on its way out. Signed-off-by: Scott Wood <scottwood@freescale.com> -- v2: fixed typo in subject, and explained what the bit does in the changelog |
#
f2041388 |
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15-Sep-2012 |
Marek Vasut <marex@denx.de> |
serial: ns16550: Call usbtty_poll only in non-SPL build Having both USBTTY and CONFIG_SERIAL_MULTI enabled in SPL, the usbtty.c file is protected in Makefile to not be compiled into the SPL. Yet, the ns16550 serial driver does not contain such protection. Add it to avoid missing symbol error. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Marek Vasut <marek.vasut@gmail.com> Cc: Tom Rini <trini@ti.com> |
#
99b603e7 |
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09-Jul-2012 |
Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com> |
serial/ns16550: ns16550 has a different register layout on SOC_DA8XX also fix NS16550_init() as we need 16x divider Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com> Acked-by: Christian Riesch <christian.riesch@omicron.at> Tested-by: Christian Riesch <christian.riesch@omicron.at> Acked-by: Sughosh Ganu <urwithsughosh@gmail.com> Tested-by: Sughosh Ganu <urwithsughosh@gmail.com> |
#
5289e83a |
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13-Oct-2011 |
Chandan Nath <chandan.nath@ti.com> |
ARM:AM33XX: Add support for TI AM335X EVM This patch adds basic support for booting the board. This patch adds support for the UART necessary to get to the u-boot prompt. Signed-off-by: Chandan Nath <chandan.nath@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> |
#
f8df9d0d |
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15-Oct-2011 |
Simon Glass <sjg@chromium.org> |
NS16550: trivial code clean for checkpatch This removes most checkpatch warnings from the ns16550 driver and its header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
79df1208 |
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01-Sep-2011 |
Dave Aldridge <fovsoft@gmail.com> |
ns16550: change to allow 32 bit access to registers If CONFIG_SYS_NS16550_MEM32 is defined then 32 bit memory mapped access will be used to read/write the uart registers. This is especially useful for SoC devices that implement 16550 compatible uarts but that have peripheral access width constraints. Signed-off-by: Dave Aldridge <fovsoft@gmail.com> |
#
a160ea0b |
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27-Oct-2010 |
Prafulla Wadaskar <prafulla@marvell.com> |
Serial: ns16550: Add support for CONFIG_SYS_NS16550_IER macro On some processors this ier register configuration is different for ex. Marvell Armada100 This patch introduce CONFIG_SYS_NS16550_IER macro support to unconditionally initialize this register. Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com> |
#
1a2d9b30 |
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12-Oct-2010 |
Stefan Roese <sr@denx.de> |
ns16550: Add WATCHDOG_RESET to putc for short watchdog timeout boards Call watchdog_reset() upon newline. This is done here in putc since the environment code uses a single puts() to print the complete envrironment upon "printenv". So we can't put this watchdog call in puts(). This is needed for boards with a very short watchdog timeout, like the lwmon5 with a 100ms timeout. Without this patch this board resets in the commands with long outputs, like "printenv" or "fdt print". Note that the image size is not increased with this patch when CONFIG_HW_WATCHDOG or CONFIG_WATCHDOG are not defined since the compiler optimizes this additional code away. Signed-off-by: Stefan Roese <sr@denx.de> Fix typo in comment. Signed-off-by: Wolfgang Denk <wd@denx.de> |
#
167cdad1 |
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23-Apr-2010 |
Graeme Russ <graeme.russ@gmail.com> |
SERIAL: Enable port-mapped access The x86 architecture exclusively uses Port-Mapped I/O (inb/outb) to access the 16550 UARTs. This patch mimics how Linux selects between Memory-Mapped and Port-Mapped I/O. This allows x86 boards to use CONFIG_SERIAL_MUTLI and drop the custom serial port driver Signed-off-by: Graeme Russ <graeme.russ@gmail.com> |
#
a47a12be |
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15-Apr-2010 |
Stefan Roese <sr@denx.de> |
Move arch/ppc to arch/powerpc As discussed on the list, move "arch/ppc" to "arch/powerpc" to better match the Linux directory structure. Please note that this patch also changes the "ppc" target in MAKEALL to "powerpc" to match this new infrastructure. But "ppc" is kept as an alias for now, to not break compatibility with scripts using this name. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Wolfgang Denk <wd@denx.de> Acked-by: Detlev Zundel <dzu@denx.de> Acked-by: Kim Phillips <kim.phillips@freescale.com> Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Anatolij Gustschin <agust@denx.de> |
#
a1b322a9 |
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01-Feb-2010 |
Ladislav Michl <ladis@linux-mips.org> |
ns16550: kick watchdog while waiting for a character ns16550 busyloops waiting for incoming byte causing watchdog to reboot while waiting for a key press. A call to WATCHDOG_RESET in NS16550_getc loop fixes it. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> |
#
660888b7 |
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30-May-2009 |
Tom Rix <Tom.Rix@windriver.com> |
ZOOM2 Add serial support. Zoom2 serial is in general supplied by one of the 4 UARTS on the debug board. The default serial is from the USB connector on left side of the debug board. The USB connector will produce 2 of the 4 UARTS. On your host pick the first enumeration. The details of the setting of the serial gpmc setup are not available. The values were provided by another party. The serial port set up is the same with Zoom1. Baud rate 115200, 8 bit data, no parity, 1 stop bit, no flow. The kernel bootargs are console=ttyS3,115200n8 Signed-off-by: Tom Rix <Tom.Rix@windriver.com> |
#
200779e3 |
|
03-Apr-2009 |
Detlev Zundel <dzu@denx.de> |
Rename common ns16550 constants with UART_ prefix to prevent conflicts Fix problems introduced in commit 7b5611cdd12ca0cc33f994f0d4a4454788fc3124 [inka4x0: Add hardware diagnosis functions for inka4x0] which redefined MSR_RI which is already used on PowerPC systems. Also eliminate redundant definitions in ps2mult.h. More cleanup will be needed for other redundant occurrences though. Signed-off-by: Detlev Zundel <dzu@denx.de> |
#
b4746d8b |
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11-Feb-2009 |
Mike Frysinger <vapier@gentoo.org> |
drivers/serial/ns16550: move ifdef into Makefile COBJS-$(...) Signed-off-by: Mike Frysinger <vapier@gentoo.org> |
#
f5675aa5 |
|
18-Feb-2009 |
Ron Madrid <ron_madrid@sbcglobal.net> |
Create configuration option for restricted ns16550 functions This patch will create a configuration option for a minimum configuration for the ns16550 serial driver at drivers/serial/ns16550.c and will apply this new configuration option to the SIMPC8313.h config file in order to fix the NAND bootstrap build error. This option will exclude all functions with exception of NS16550_putc and NS16550_init. This will be used primarily to save space and remove unused code from builds in which space is limited. Signed-off-by: Ron Madrid <ron_madrid@sbcglobal.net> |
#
6d0f6bcf |
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16-Oct-2008 |
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
rename CFG_ macros to CONFIG_SYS Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
#
7ec8bb15 |
|
27-Dec-2007 |
Wolfgang Denk <wd@denx.de> |
OMAP5912: fix FIFO handling in UART driver According to the OMAP5912 Serial Interfaces Reference Guide (see http://focus.ti.com/lit/ug/spru760c/spru760c.pdf, page 150), the FIFO_EN enable bit in the FIFO Control Register (FCR) can only be changed when the baud clock is not running, i. e. when both DLL and DLH are set to 0. Thus make sure that DLL and DLH are 0 when writing the FCR. Signed-off-by: Wolfgang Denk <wd@denx.de> |
#
1378df79 |
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24-Nov-2007 |
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
drivers/serial : move serial drivers to drivers/serial Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
#
384b62c0 |
|
03-Feb-2021 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Handle zero <clock-frequency> value A working device tree node of ns16550 should never be populated with value zero for the <clock-frequency> property. Unfortunately this is the case for the QEMU ppce500 target. Let's try to assign plat->clock to CONFIG_SYS_NS16550_CLK as the last resort to handle such case. This commit should be reverted when: - The following QEMU patch [1] is merged, and - U-Boot CI has upgraded its QEMU version that contains the fix [1] http://patchwork.ozlabs.org/project/qemu-devel/patch/1612362288-22216-2-git-send-email-bmeng.cn@gmail.com/ Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
09bd0840 |
|
03-Feb-2021 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Correct the base address type Currently ns16550_serial_assign_base() treats the argument 'base' with type `ulong`. This is incorrect because the base address was obtained from device tree with type `fdt_addr_t` that can represent a physical address larger than 32-bit in a 32-bit system. Fixes: 9e6ce62190b7 ("serial: ns16550: Fix ordering of getting base address") Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
401d1c4f |
|
30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
bdf8fd76 |
|
28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
0fd3d911 |
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22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com> |
#
2d6bf754 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
#
d30c7209 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
d1998a9f |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
c69cda25 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
caa4daa2 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
41575d8e |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
addf358b |
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24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo |
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de> |
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> |
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se> |
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> |
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com |
#
9ad3b049 |
|
02-Nov-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: add setconfig support Add possibility to update the serial parity used. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com> |
#
46879196 |
|
24-Oct-2018 |
Bin Meng <bmeng.cn@gmail.com> |
serial: Remove DM_FLAG_PRE_RELOC flag in various drivers When a driver declares DM_FLAG_PRE_RELOC flag, it wishes to be bound before relocation. However due to a bug in the DM core, the flag only takes effect when devices are statically declared via U_BOOT_DEVICE(). This bug has been fixed recently by commit "dm: core: Respect drivers with the DM_FLAG_PRE_RELOC flag in lists_bind_fdt()", but with the fix, it has a side effect that all existing drivers that declared DM_FLAG_PRE_RELOC flag will be bound before relocation now. This may expose potential boot failure on some boards due to insufficient memory during the pre-relocation stage. To mitigate this potential impact, the following changes are implemented: - Remove DM_FLAG_PRE_RELOC flag in the driver, if the driver only supports configuration from device tree (OF_CONTROL) - Keep DM_FLAG_PRE_RELOC flag in the driver only if the device is statically declared via U_BOOT_DEVICE() - Surround DM_FLAG_PRE_RELOC flag with OF_CONTROL check, for drivers that support both statically declared devices and configuration from device tree Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
6f57c344 |
|
09-Aug-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), let's rather ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
5d754197 |
|
27-Aug-2018 |
Lokesh Vutla <lokeshvutla@ti.com> |
serial: omap: Introduce DM specific omap serial Add driver model support for OMAP_SERIAL while reusing the functions in ns16550.c Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Tested-by: Derald D. Woods <woods.technical@gmail.com> |
#
b051eecb |
|
14-Jun-2018 |
Ley Foon Tan <ley.foon.tan@intel.com> |
serial: ns16550: Add reset ctrl to driver Add code to reset all reset signals as in serial DT node. A reset property is an optional feature, so do not fail if a reset property is not present. If a reset property is discovered, then use it to deassert, thus bringing the IP out of reset. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
78b7d37b |
|
15-Feb-2018 |
Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> |
ns16550: Fix mem mapped endian check Do a explicit check for CONFIG_SYS_BIG_ENDIAN and CONFIG_SYS_LITTLE_ENDIAN to avoid errors on platforms where both are undefined (x86). Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> Reviewed-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com> |
#
4dbf9bed |
|
15-Jan-2018 |
Mario Six <mario.six@gdsys.cc> |
serial: ns16550: Fix style violation Clarify the computation precedence in two ternary operator constructions. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc> |
#
7fded0ce |
|
16-Aug-2017 |
Stefan Roese <sr@denx.de> |
Revert "serial: ns16550: Add RX interrupt buffer support" This reverts commit 6822cf3ec7c8768b8727573b8f4b2cb3d870b881. As Bin Meng has tested and pointed out, we don't need the RX interrupt for the RX buffer support at all. Just reading all available characters into a buffer is sufficient to solve the problem with the dropped characters upon long lines pasted into the U-Boot prompt. Since this RX buffer support can be implemented in a generic way, without any device specifica (e.g. for the ns16550), I'll post a new patch with a new serial RX buffer support for DM, which all DM based serial drivers can use. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
6822cf3e |
|
14-Jul-2017 |
Stefan Roese <sr@denx.de> |
serial: ns16550: Add RX interrupt buffer support Pasting longer lines into the U-Boot console prompt sometimes leads to characters missing. One problem here is the small 16-byte FIFO of the legacy NS16550 UART, e.g. on x86 platforms. This patch now introduces a Kconfig option to enable RX interrupt buffer support for NS16550 style UARTs. With this option enabled, I was able paste really long lines into the U-Boot console, without any characters missing. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> [trini: Guard ns16550_serial_remove with CONFIG_IS_ENABLED(SERIAL_PRESENT) to match struct assignment] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
8d3a2568 |
|
11-Jul-2017 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-dm
|
#
db9f8f6a |
|
12-Jun-2017 |
Simon Glass <sjg@chromium.org> |
dm: serial: ns16550: Convert to livetree Update this driver to support a live device tree. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Tested-on: Beaver, Jetson-TK1 |
#
3d40479f |
|
07-Jun-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
rockchip: ns16550: dm: convert fdt_get to dev_read With the new dev_read functions available, we can convert the rockchip architecture-specific drivers and common drivers used by these devices over to the dev_read family of calls. This covers the serial driver (ns16550 and compatible) used for the Rockchip devices. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
a821c4af |
|
17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: Rename dev_addr..() functions These support the flat device tree. We want to use the dev_read_..() prefix for functions that support both flat tree and live tree. So rename the existing functions to avoid confusion. In the end we will have: 1. dev_read_addr...() - works on devices, supports flat/live tree 2. devfdt_get_addr...() - current functions, flat tree only 3. of_get_address() etc. - new functions, live tree only All drivers will be written to use 1. That function will in turn call either 2 or 3 depending on whether the flat or live tree is in use. Note this involves changing some dead code - the imx_lpi2c.c file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
89024ddc |
|
12-May-2017 |
Tom Rini <trini@konsulko.com> |
TI: Drop 'CONFIG_OMAP' In the two cases in the code where we use CONFIG_OMAP as a useful test currently we can make use of CONFIG_ARCH_OMAP2PLUS instead. With that changed we can drop all defines of CONFIG_OMAP. While in here, CONFIG_OMAP3430 is only defined and then never used, so drop. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
a52cf086 |
|
22-Apr-2017 |
Lokesh Vutla <lokeshvutla@ti.com> |
serial: omap: Support debug UART Add debug UART functions to permit omap specific ns16550 to provide an early debug UART. This is mostly in common with DEBUG_UART_NS16550 except for Mode definition register which is required for selecting UART mode(16x auto-baud or 13x mode). Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
6f8c351e |
|
27-Mar-2017 |
Alexandru Gagniuc <alex.g@adaptrum.com> |
serial: ns16550: Link in the DM driver when when using platdata Do not condition the compilation of the U_BOOT_DRIVER by !OF_PLATDATA. This is inconsistent with the majority of other drivers. This also blocks OF_PLATDATA boards with an 16550-compatible serial from using serial in SPL. Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com> Reviewed-by: Simon Glass <sjg@chromium.org> Added tweak for rock to avoid a TPL build failure: Signed-off-by: Simon Glass <sjg@chromium.org> |
#
e160f7d4 |
|
17-Jan-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
17fa0326 |
|
18-Jan-2017 |
Heiko Schocher <hs@denx.de> |
serial, ns16550: bugfix: ns16550 fifo not enabled commit: 65f83802b7a5b "serial: 16550: Add getfcr accessor" breaks u-boot commandline working with long commands sending to the board. Since the above patch, you have to setup the fcr register. For board/archs which enable OF_PLATDATA, the new field fcr in struct ns16550_platdata is not filled with a default value ... This leads in not setting up the uarts fifo, which ends in problems, when you send long commands to u-boots commandline. Detected this issue with automated tbot tests on am335x based shc board. The error does not popup, if you type commands. You need to copy&paste a long command to u-boots commandshell (or send a long command with tbot) Possible boards/plattforms with problems: ./arch/arm/cpu/arm926ejs/lpc32xx/devices.c ./arch/arm/mach-tegra/board.c ./board/overo/overo.c ./board/quipos/cairo/cairo.c ./board/logicpd/omap3som/omap3logic.c ./board/logicpd/zoom1/zoom1.c ./board/timll/devkit8000/devkit8000.c ./board/lg/sniper/sniper.c ./board/ti/beagle/beagle.c ./drivers/serial/serial_rockchip.c Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Tested-by: Adam Ford <aford173@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
0b060eef |
|
30-Nov-2016 |
Marek Vasut <marex@denx.de> |
serial: 16550: Add Ingenic JZ4780 support Add compatibility string for the Ingenic JZ4780 SoC, the necessary UART enable bit into FCR and register shift. Neither are encoded in the DTS coming from Linux, so we need to support it this way. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
79fd9281 |
|
30-Nov-2016 |
Marek Vasut <marex@denx.de> |
serial: 16550: Add port type as driver data Add driver data to each compatible string to identify the type of the port. Since all the ports in the driver are entirely compatible with 16550 for now, all are marked with PORT_NS16550. But, there are ports which have specific quirks, like the JZ4780 UART, which do not have any DT property to denote the quirks. Instead, Linux uses the compatible string to discern such ports and enable the necessary quirks. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> |
#
65f83802 |
|
30-Nov-2016 |
Marek Vasut <marex@denx.de> |
serial: 16550: Add getfcr accessor Add function which allows fetching the default FCR register setting from platform data for DM , while retaining old behavior for non-DM by returning UART_FCRVAL. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
021abf69 |
|
26-Sep-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
Revert "ns16650: Make sure we have CONFIG_CLK set before using infrastructure" This reverts commit 82f5279b0cd99a9163d34cfe926d0316d9dc0d37. The build failure of k2*evm boards was fixed in a different way by the previous commit. It is nasty to patch generic drivers around with #ifdef CONFIG_CLK just for the KeyStone's matter. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
ab895d6a |
|
30-Sep-2016 |
Alexandre Courbot <acourbot@nvidia.com> |
serial: ns16550: Handle -ENOENT when requesting clock When calling clk_get_by_index(), fall back to the legacy method of getting the clock if -ENOENT is returned. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> |
#
82f5279b |
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22-Sep-2016 |
Tom Rini <trini@konsulko.com> |
ns16650: Make sure we have CONFIG_CLK set before using infrastructure We cannot call on the CONFIG_CLK based clk_get_rate function unless CONFIG_CLK is set. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
50fce1d5 |
|
08-Sep-2016 |
Paul Burton <paul.burton@mips.com> |
serial: ns16550: Support clocks via phandle Previously ns16550 compatible UARTs probed via device tree have needed their device tree nodes to contain a clock-frequency property. An alternative to this commonly used with Linux is to reference a clock via a phandle. This patch allows U-Boot to support that, retrieving the clock frequency by probing the appropriate clock device. For example, a system might choose to provide the UART base clock as a reference to a clock common to multiple devices: sys_clk: clock { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <10000000>; }; uart0: uart@10000000 { compatible = "ns16550a"; reg = <0x10000000 0x1000>; clocks = <&sys_clk>; }; uart1: uart@10000000 { compatible = "ns16550a"; reg = <0x10001000 0x1000>; clocks = <&sys_clk>; }; This removes the need for the frequency information to be duplicated in multiple nodes and allows the device tree to be more descriptive of the system. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
b2927fba |
|
04-Jul-2016 |
Simon Glass <sjg@chromium.org> |
dm: serial: ns16550: Update to support of-platdata With of-platdata this driver cannot know the format of the of-platdata struct, so we cannot use generic code for accessing the of-platdata. Each SoC that uses this driver will need to set up ns16550's platdata for it. So don't compile in the generic code. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
03c6f176 |
|
24-May-2016 |
Marek Vasut <marex@denx.de> |
serial: 16550: Drop OMAP1510 support The CONFIG_OMAP1510 is no longer defined, so remove this dead code. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Nishanth Menon <nm@ti.com> |
#
fa4ce723 |
|
24-May-2016 |
Marek Vasut <marex@denx.de> |
serial: 16550: Make serial_io/out_shift available to debug mode The ns16550 driver needs serial_in_shift() and serial_out_shift() when compiled in debug UART mode, so shift the DM_SERIAL check a little to make these functions available. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
df8ec55d |
|
17-May-2016 |
Paul Burton <paul.burton@mips.com> |
dm: ns16550: Don't map_physmem for I/O ports If the UART is to be accessed using I/O port accessors (inb & outb) then using map_physmem doesn't make sense, since it operates in a different memory space. Remove the call to map_physmem when CONFIG_SYS_NS16550_PORT_MAPPED is defined, allowing I/O port addresses to not be mangled by the incorrect mapping. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> |
#
59b35ddd |
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16-Feb-2016 |
Michal Simek <michal.simek@xilinx.com> |
dm: ns16550: Add support for reg-offset property reg-offset is the part of standard 8250 binding in the kernel. It is shifting start of address space by reg-offset. On Xilinx platform this offset is typically 0x1000. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Moved the new field to the end of the struct to avoid problems: Signed-off-by: Simon Glass <sjg@chromium.org> |
#
e5e88c65 |
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29-Feb-2016 |
Tom Rini <trini@konsulko.com> |
Revert "dm: ns16550: Add support for reg-offset property" This reverts commit d9a3bec682f9756621615f4306718a356a3230e3. While this is a correct change to do long term it unfortunately breaks a number of platforms that are using pdata and not named struct members so they are getting all of their data after 'base' incorrect. Acked-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
d9a3bec6 |
|
16-Feb-2016 |
Michal Simek <michal.simek@xilinx.com> |
dm: ns16550: Add support for reg-offset property reg-offset is the part of standard 8250 binding in the kernel. It is shifting start of address space by reg-offset. On Xilinx platform this offset is typically 0x1000. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
cc4228f9 |
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14-Dec-2015 |
Thomas Chou <thomas@wytron.com.tw> |
ns16550: zap the rockchip serial compatible string Zap the rockchip serial compatible string, because rockchip serial has "snps,dw-apb-uart" compatible string in the dts. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org> |
#
b7e29834 |
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13-Dec-2015 |
Simon Glass <sjg@chromium.org> |
dm: ns16550: Allow the driver to be omitted if requested Allow the ns16550 debug UART to be used without the full driver. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Thomas Chou <thomas@wytron.com.tw> |
#
fcc0a877 |
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29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: serial: Convert ns16550 driver to use driver model PCI API Use the driver model version of the function to find the BAR. This updates the fdtdec function, of which ns16550 is the only user. The fdtdec_get_pci_bdf() function is dropped for several reasons: - with driver model we should use 'struct udevice *' rather than passing the device tree offset explicitly - there are no other users in the tree - the function parses for information which is already available in the PCI device structure (specifically struct pci_child_platdata which is available at dev_get_parent_platdata(dev) Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> |
#
b7e5a643 |
|
04-Dec-2015 |
Simon Glass <sjg@chromium.org> |
dm: serial: ns16550: Add pre-reloc flag to the driver For platforms that don't use device tree in SPL the only way to mark this driver as 'required by relocation' is with the DM_FLAG_PRE_RELOC flag. Add this to ensure that the driver is bound. Fixes: fde7e18938d8 ("dm: tegra: pci: Move CONFIG_PCI_TEGRA to Kconfig") Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Stephen Warren <swarren@nvidia.com> Acked-by: Thomas Chou <thomas@wytron.com.tw> |
#
80e06146 |
|
28-Nov-2015 |
Thomas Chou <thomas@wytron.com.tw> |
ns16550: change reg-shift property default to zero Change reg-shift property default to zero. When the integer property is missing, it should be taken as zero. This is consistent to Linux drivers/tty/serial/of_serial.c. The x86 and most powerpc use reg-shift of 0. Most others use reg-shift of 2. While reg-shift of 1 is rarely used. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
a51dbebf |
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16-Nov-2015 |
huang lin <hl@rock-chips.com> |
rockchip: serial driver support rk3036 Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
4fb60552 |
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19-Nov-2015 |
Thomas Chou <thomas@wytron.com.tw> |
ns16550: zap CONFIG_NS16550_SERIAL Zap CONFIG_NS16550_SERIAL, as the unification of ns16550 drivers is completed. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
8e62d32e |
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19-Nov-2015 |
Thomas Chou <thomas@wytron.com.tw> |
ns16550: add generic binding to unify the drivers Add generic binding to unify ns16550 drivers. There are several drivers using almost the same code, such as serial_dw, serial_keystone, serial_omap, serial_ppc, serial_rockchip, serial_tegra.c, and serial_x86. But each is platform specific. The key difference between these drivers is the way to get input clock frequency. With this unified approach, fixed clock frequency should be extracted from "clock-frequency" property of device tree blob. If this property is not available, the macro CONFIG_SYS_NS16550_CLK will be used. It can be a constant or a function to get clock, eg, get_serial_clock(). Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de> Acked-by: Simon Glass <sjg@chromium.org> |
#
77d7b5cd |
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19-Nov-2015 |
Thomas Chou <thomas@wytron.com.tw> |
ns16550: change map_sysmem to map_physmem Change map_sysmem() to map_physmem(,,MAP_NOCACHE). Though map_sysmem() can be used to map system memory, it might be wrong to use it for I/O ports. The map_physmem() serves the same purpose to translate physical address to virtual address with the additional flag to take care of cache property. Most drivers use map_physmem() since I/O ports access should be uncached. As ns16550 is a driver, it should use map_physmem() rather than map_sysmem(). Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org> |
#
97b05973 |
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18-Oct-2015 |
Simon Glass <sjg@chromium.org> |
debug_uart: Adjust the declaration of debug_uart_init() We want to be able to add other common code to this function. So change the driver's version to have an underscore before it, just like _debug_uart_putc(). Define debug_uart_init() to call this version. Update all drivers to this new method. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
4e9838c1 |
|
11-Aug-2015 |
Simon Glass <sjg@chromium.org> |
dm: Use dev_get_addr() where possible This is a convenient way for a driver to get the hardware address of a device, when regmap or syscon are not being used. Change existing callers to use it as an example to others. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> |
#
0f925822 |
|
11-Aug-2015 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
of: clean up OF_CONTROL ifdef conditionals We have flipped CONFIG_SPL_DISABLE_OF_CONTROL. We have cleansing devices, $(SPL_) and CONFIG_IS_ENABLED(), so we are ready to clear away the ugly logic in include/fdtdec.h: #ifdef CONFIG_OF_CONTROL # if defined(CONFIG_SPL_BUILD) && !defined(SPL_OF_CONTROL) # define OF_CONTROL 0 # else # define OF_CONTROL 1 # endif #else # define OF_CONTROL 0 #endif Now CONFIG_IS_ENABLED(OF_CONTROL) is the substitute. It refers to CONFIG_OF_CONTROL for U-boot proper and CONFIG_SPL_OF_CONTROL for SPL. Also, we no longer have to cancel CONFIG_OF_CONTROL in include/config_uncmd_spl.h and scripts/Makefile.spl. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> |
#
6e780c7a |
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23-Jun-2015 |
Simon Glass <sjg@chromium.org> |
ns16550: Improve debug UART so it can work with 32-bit access Since Rockchip requires 32-bit serial access, add this to the driver. Refactor a little to make this easier. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
90914008 |
|
12-May-2015 |
Simon Glass <sjg@chromium.org> |
dm: ns16550: Support CONFIG_SYS_NS16550_MEM32 with driver model This option is used by some boards, so support it with driver model. This is really ugly - we should rewrite this driver once all users are moved to driver model. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4f60166c |
|
24-Apr-2015 |
Axel Lin <axel.lin@ingics.com> |
serial: ns16550: Remove hard-coded baud_divisor setting This was accidentally added by commit dd0b0122bacc "serial: ns16550: Add an option to specify the debug UART register shift". Remove it. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
ab9fd2e8 |
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27-Feb-2015 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Remove unnecessary init on UART setup It is not necessary to write a zero baud rate to the device, and for some chips this will cause problems. Drop this code. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
363e6da1 |
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27-Feb-2015 |
Simon Glass <sjg@chromium.org> |
dm: ns16550: Support non-byte register spacing with driver model Allow this driver to support boards where the register shift is not 0. This fixes some compiler warnings which appear in that case. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
dd0b0122 |
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27-Feb-2015 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Add an option to specify the debug UART register shift This UART permits different register spacing. To support the debug UART on devices which have a spacing other than 1 byte, allow the shift value to be specified. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
0eb25b61 |
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22-Mar-2015 |
Joe Hershberger <joe.hershberger@ni.com> |
common: Make sure arch-specific map_sysmem() is defined In the case where the arch defines a custom map_sysmem(), make sure that including just mapmem.h is sufficient to have these functions as they are when the arch does not override it. Also split the non-arch specific functions out of common.h Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
20379c11 |
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28-Feb-2015 |
Axel Lin <axel.lin@ingics.com> |
serial: ns16550: Fix build error due to a typo Fix trivial typo. Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Axel Lin <axel.lin@ingics.com> |
#
21d00436 |
|
26-Jan-2015 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support debug UART Add debug UART functions to permit ns16550 to provide an early debug UART. Try to avoid using the stack so that this can be called from assembler before a stack is set up (at least on ARM and PowerPC). Signed-off-by: Simon Glass <sjg@chromium.org> |
#
76571674 |
|
26-Jan-2015 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Add access functions that don't need platdata For the debug UART we need to be able to provide any parameters before driver model is set up. Add parameters to the low-level access functions to make this possible. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
3db886a5 |
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31-Dec-2014 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Support ns16550 compatible pci uart devices There are many pci uart devices which are ns16550 compatible. We can describe them in the board dts file and use it as the U-Boot serial console as specified in the chosen node 'stdout-path' property. Those pci uart devices can have their register be memory-mapped, or i/o-mapped. The driver will try to use the memory-mapped register if the reg property in the node has an entry to describe the memory-mapped register, otherwise i/o-mapped register will be used. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
956a8bae |
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10-Nov-2014 |
Gregoire Gentil <gregoire@gentil.com> |
ns16550.c: Fix for ns16550 driver hanging on OMAP4 The same problem that is seen on some OMAP3 is also seen on some OMAP4 so include them in the test in order to prevent some hangs during SPL. [trini: Re-word commit message, make apply cleanly] Signed-off-by: Tom Rini <trini@ti.com> |
#
1f77690e |
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10-Oct-2014 |
Simon Glass <sjg@chromium.org> |
dm: serial: ns16550: Add a cast to the I/O operations This generates a warning when driver model is enabled, so fix it by adding a cast. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
11c1a878 |
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22-Oct-2014 |
Simon Glass <sjg@chromium.org> |
dm: ns16550: Correct the probe logic for platform data The probe logic sets up the pointer to the platform data in the device tree decode method. It should be done in the probe() method, and anyway the device tree decode method can't be used when CONFIG_OF_CONTROL is not enabled. Fix these two problems. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@ti.com> |
#
167efe01 |
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22-Oct-2014 |
Simon Glass <sjg@chromium.org> |
dm: ns16550: Use an address instead of a pointer for the uart base It is inconvenient to have to use casts when specifying platform data. Also it is not strictly correct, since we should use map_sysmem() to convert an address to a pointer. Adjust the platform data to use an address. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@ti.com> |
#
aea2be20 |
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22-Oct-2014 |
Simon Glass <sjg@chromium.org> |
dm: serial: ns16550: Correct logic for checking for character There is a bug in the logic which checks for an available character. This can cause invalid characters to be received - this was noticed on beaglebone. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@ti.com> |
#
12e431b2 |
|
04-Sep-2014 |
Simon Glass <sjg@chromium.org> |
dm: serial: Add driver model support for ns16550 Add driver model support so that ns16550 can support operation both with and without driver model. The driver needs a clock frequency so cannot stand alone unfortunately. The clock frequency must be provided by a separate driver. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8bbe33c8 |
|
04-Sep-2014 |
Simon Glass <sjg@chromium.org> |
dm: serial: Collect common baud rate code in ns16550 The same sequence is used in several places, so move it into a function. Note that UART_LCR_BKSE is an alias for UART_LCR_DLAB. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
fa54eb12 |
|
04-Sep-2014 |
Simon Glass <sjg@chromium.org> |
dm: serial: Move baud rate calculation to ns16550.c Move the function that calculates the baud rate divisor into ns16550.c so it can be used by that file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8ac22a60 |
|
30-Jul-2014 |
Masahiro Yamada <yamada.m@jp.panasonic.com> |
omap: clean-up dead configs The following configs are not defined at all. - CONFIG_OMAP1510 - CONFIG_OMAP_1510P1 - CONFIG_OMAP_SX1 - CONFIG_OMAP3_DMA - CONFIG_OMAP3_ZOOM2 - CONFIG_OMAP_INNOVATOR Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Tom Rini <trini@ti.com> |
#
7c387646 |
|
15-Jul-2014 |
Khoronzhuk, Ivan <ivan.khoronzhuk@ti.com> |
keystone2: use CONFIG_SOC_KEYSTONE in common places Use CONFIG_SOC_KEYSTONE in common places instead of defining a lot of "if def .. || if def " for different Keystone2 SoC types. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> |
#
d57dee57 |
|
09-Apr-2014 |
Karicheri, Muralidharan <m-karicheri2@ti.com> |
serial: nsl16550: add hw flow control support keystone serial hw support hw flow control. This patch enables hw flow control for keystone EVMs as an optional feature based on CONFIG_SERIAL_HW_FLOW_CONTROL. Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> |
#
ef509b90 |
|
04-Apr-2014 |
Vitaly Andrianov <vitalya@ti.com> |
k2hk: add support for k2hk SOC and EVM k2hk EVM is based on Texas Instruments Keystone2 Hawking/Kepler SoC. Keystone2 SoC has ARM v7 Cortex-A15 MPCore processor. Please refer the ti/k2hk_evm/README for details on the board, build and other information. This patch add support for keystone architecture and k2hk evm. Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: WingMan Kwok <w-kwok2@ti.com> Signed-off-by: Sandeep Nair <sandeep_n@ti.com> |
#
456ccfdf |
|
20-Dec-2013 |
Tom Rini <trini@ti.com> |
TI:omap3: Drop omap3_zoom2 The omap3_zoom2 board has not been updated for a correct CONFIG_SYS_HZ and Tom Rix's email has long been bouncing. Signed-off-by: Tom Rini <trini@ti.com> |
#
9ed6e412 |
|
01-Jul-2013 |
TENART Antoine <atenart@adeneo-embedded.com> |
Prepare for TI816X : reuse existing code from TI814X Rename some CONFIG_TI814X to a more generic CONFIG_TI81XX Signed-off-by: Antoine Tenart <atenart@adeneo-embedded.com> [trini: Adapt for CONFIG_OMAP_COMMON changes, AM43XX] Signed-off-by: Tom Rini <trini@ti.com> |
#
57180408 |
|
30-Jul-2013 |
Lokesh Vutla <lokeshvutla@ti.com> |
ARM: AM43xx: Add build support Add AM43xx support in the required places Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> |
#
7f5eef93 |
|
03-Jun-2013 |
Tom Rini <trini@ti.com> |
arm: Remove OMAP2420H4 and all omap24xx support The omap2420H4 was the only mainline omap24xx board. Prior to being fixed by Jon Hunter in time for v2013.04 it had been functionally broken for a very long time. Remove this board as there's not been interest in it in U-Boot for quite a long time. Signed-off-by: Tom Rini <trini@ti.com> |
#
fd2aeac5 |
|
28-Mar-2013 |
Manfred Huber <man.huber@arcor.de> |
omap3_beagle: Flush UART3 xmit on enable if TEMT is broken Flush UART3 xmit on enable if TEMT is broken On some OMAP3 devices when UART3 is configured for boot mode before SPL starts only THRE bit is set. We have to empty the transmitter before initialization starts. This patch avoids the use of CONFIG_SYS_NS16550_BROKEN_TEMT. Signed-off-by: Manfred Huber <man.huber@arcor.de> Tested-by: Javier Martinez Canillas <javier@dowhile0.org> Tested-by: Andreas Bießmann <andreas.devel@googlemail.com> |
#
6213a68f |
|
15-Mar-2013 |
Matt Porter <mporter@ti.com> |
ns16550: enable quirks for ti814x TI814X requires the same quirks as AM33XX to be enabled. Signed-off-by: Matt Porter <mporter@ti.com> Reviewed-by: Tom Rini <trini@ti.com> |
#
69e06832 |
|
05-Mar-2013 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Remove unwanted cast This cast does not seem correct, since we should be writing to a pointer, not a ulong. This fixes the following warning on nds32: -ns16550.c:49: warning: passing argument 2 of 'writeb' makes pointer from integer without a cast Signed-off-by: Simon Glass <sjg@chromium.org> |
#
7de0fe1a |
|
06-Jan-2013 |
Javier Martinez Canillas <javier@dowhile0.org> |
serial/ns16550: add an option to avoid hanging on broken platforms Some platforms (e.g. IGEPv2 board) has a broken ns16550 UART that does not set the TEMT bit when the transmitter is empty in SPL. This makes U-Boot to hang while waiting for TEMT to be set. Add a new option to avoid this: CONFIG_SYS_NS16550_BROKEN_TEMT 16550 UART set the Transmitter Empty (TEMT) Bit when all output has finished and the transmitter is totally empty. U-Boot waits for this bit to be set to initialize the serial console. On some broken platforms this bit is not set in SPL making U-Boot to hang while waiting for TEMT. Define this option to avoid it. Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> |
#
cb55b332 |
|
18-Sep-2012 |
Scott Wood <scottwood@freescale.com> |
serial/ns16550: wait for TEMT before initializing TEMT is set when the transmitter is totally empty and all output has finished. This prevents output problems (including a loss of synchronization observed on p2020 that persisted for quite a while) if SPL has output still on its way out. Signed-off-by: Scott Wood <scottwood@freescale.com> -- v2: fixed typo in subject, and explained what the bit does in the changelog |
#
f2041388 |
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15-Sep-2012 |
Marek Vasut <marex@denx.de> |
serial: ns16550: Call usbtty_poll only in non-SPL build Having both USBTTY and CONFIG_SERIAL_MULTI enabled in SPL, the usbtty.c file is protected in Makefile to not be compiled into the SPL. Yet, the ns16550 serial driver does not contain such protection. Add it to avoid missing symbol error. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Marek Vasut <marek.vasut@gmail.com> Cc: Tom Rini <trini@ti.com> |
#
99b603e7 |
|
09-Jul-2012 |
Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com> |
serial/ns16550: ns16550 has a different register layout on SOC_DA8XX also fix NS16550_init() as we need 16x divider Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com> Acked-by: Christian Riesch <christian.riesch@omicron.at> Tested-by: Christian Riesch <christian.riesch@omicron.at> Acked-by: Sughosh Ganu <urwithsughosh@gmail.com> Tested-by: Sughosh Ganu <urwithsughosh@gmail.com> |
#
5289e83a |
|
13-Oct-2011 |
Chandan Nath <chandan.nath@ti.com> |
ARM:AM33XX: Add support for TI AM335X EVM This patch adds basic support for booting the board. This patch adds support for the UART necessary to get to the u-boot prompt. Signed-off-by: Chandan Nath <chandan.nath@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> |
#
f8df9d0d |
|
15-Oct-2011 |
Simon Glass <sjg@chromium.org> |
NS16550: trivial code clean for checkpatch This removes most checkpatch warnings from the ns16550 driver and its header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
79df1208 |
|
01-Sep-2011 |
Dave Aldridge <fovsoft@gmail.com> |
ns16550: change to allow 32 bit access to registers If CONFIG_SYS_NS16550_MEM32 is defined then 32 bit memory mapped access will be used to read/write the uart registers. This is especially useful for SoC devices that implement 16550 compatible uarts but that have peripheral access width constraints. Signed-off-by: Dave Aldridge <fovsoft@gmail.com> |
#
a160ea0b |
|
27-Oct-2010 |
Prafulla Wadaskar <prafulla@marvell.com> |
Serial: ns16550: Add support for CONFIG_SYS_NS16550_IER macro On some processors this ier register configuration is different for ex. Marvell Armada100 This patch introduce CONFIG_SYS_NS16550_IER macro support to unconditionally initialize this register. Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com> |
#
1a2d9b30 |
|
12-Oct-2010 |
Stefan Roese <sr@denx.de> |
ns16550: Add WATCHDOG_RESET to putc for short watchdog timeout boards Call watchdog_reset() upon newline. This is done here in putc since the environment code uses a single puts() to print the complete envrironment upon "printenv". So we can't put this watchdog call in puts(). This is needed for boards with a very short watchdog timeout, like the lwmon5 with a 100ms timeout. Without this patch this board resets in the commands with long outputs, like "printenv" or "fdt print". Note that the image size is not increased with this patch when CONFIG_HW_WATCHDOG or CONFIG_WATCHDOG are not defined since the compiler optimizes this additional code away. Signed-off-by: Stefan Roese <sr@denx.de> Fix typo in comment. Signed-off-by: Wolfgang Denk <wd@denx.de> |
#
167cdad1 |
|
23-Apr-2010 |
Graeme Russ <graeme.russ@gmail.com> |
SERIAL: Enable port-mapped access The x86 architecture exclusively uses Port-Mapped I/O (inb/outb) to access the 16550 UARTs. This patch mimics how Linux selects between Memory-Mapped and Port-Mapped I/O. This allows x86 boards to use CONFIG_SERIAL_MUTLI and drop the custom serial port driver Signed-off-by: Graeme Russ <graeme.russ@gmail.com> |
#
a47a12be |
|
15-Apr-2010 |
Stefan Roese <sr@denx.de> |
Move arch/ppc to arch/powerpc As discussed on the list, move "arch/ppc" to "arch/powerpc" to better match the Linux directory structure. Please note that this patch also changes the "ppc" target in MAKEALL to "powerpc" to match this new infrastructure. But "ppc" is kept as an alias for now, to not break compatibility with scripts using this name. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Wolfgang Denk <wd@denx.de> Acked-by: Detlev Zundel <dzu@denx.de> Acked-by: Kim Phillips <kim.phillips@freescale.com> Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Anatolij Gustschin <agust@denx.de> |
#
a1b322a9 |
|
01-Feb-2010 |
Ladislav Michl <ladis@linux-mips.org> |
ns16550: kick watchdog while waiting for a character ns16550 busyloops waiting for incoming byte causing watchdog to reboot while waiting for a key press. A call to WATCHDOG_RESET in NS16550_getc loop fixes it. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> |
#
660888b7 |
|
30-May-2009 |
Tom Rix <Tom.Rix@windriver.com> |
ZOOM2 Add serial support. Zoom2 serial is in general supplied by one of the 4 UARTS on the debug board. The default serial is from the USB connector on left side of the debug board. The USB connector will produce 2 of the 4 UARTS. On your host pick the first enumeration. The details of the setting of the serial gpmc setup are not available. The values were provided by another party. The serial port set up is the same with Zoom1. Baud rate 115200, 8 bit data, no parity, 1 stop bit, no flow. The kernel bootargs are console=ttyS3,115200n8 Signed-off-by: Tom Rix <Tom.Rix@windriver.com> |
#
200779e3 |
|
03-Apr-2009 |
Detlev Zundel <dzu@denx.de> |
Rename common ns16550 constants with UART_ prefix to prevent conflicts Fix problems introduced in commit 7b5611cdd12ca0cc33f994f0d4a4454788fc3124 [inka4x0: Add hardware diagnosis functions for inka4x0] which redefined MSR_RI which is already used on PowerPC systems. Also eliminate redundant definitions in ps2mult.h. More cleanup will be needed for other redundant occurrences though. Signed-off-by: Detlev Zundel <dzu@denx.de> |
#
b4746d8b |
|
11-Feb-2009 |
Mike Frysinger <vapier@gentoo.org> |
drivers/serial/ns16550: move ifdef into Makefile COBJS-$(...) Signed-off-by: Mike Frysinger <vapier@gentoo.org> |
#
f5675aa5 |
|
18-Feb-2009 |
Ron Madrid <ron_madrid@sbcglobal.net> |
Create configuration option for restricted ns16550 functions This patch will create a configuration option for a minimum configuration for the ns16550 serial driver at drivers/serial/ns16550.c and will apply this new configuration option to the SIMPC8313.h config file in order to fix the NAND bootstrap build error. This option will exclude all functions with exception of NS16550_putc and NS16550_init. This will be used primarily to save space and remove unused code from builds in which space is limited. Signed-off-by: Ron Madrid <ron_madrid@sbcglobal.net> |
#
6d0f6bcf |
|
16-Oct-2008 |
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
rename CFG_ macros to CONFIG_SYS Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
#
7ec8bb15 |
|
27-Dec-2007 |
Wolfgang Denk <wd@denx.de> |
OMAP5912: fix FIFO handling in UART driver According to the OMAP5912 Serial Interfaces Reference Guide (see http://focus.ti.com/lit/ug/spru760c/spru760c.pdf, page 150), the FIFO_EN enable bit in the FIFO Control Register (FCR) can only be changed when the baud clock is not running, i. e. when both DLL and DLH are set to 0. Thus make sure that DLL and DLH are 0 when writing the FCR. Signed-off-by: Wolfgang Denk <wd@denx.de> |
#
1378df79 |
|
24-Nov-2007 |
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
drivers/serial : move serial drivers to drivers/serial Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
#
401d1c4f |
|
30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
bdf8fd76 |
|
28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0fd3d911 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
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#
2d6bf754 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
d30c7209 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
d1998a9f |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
c69cda25 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
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27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
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#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
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#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
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#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
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20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
4e720779 |
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20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
1a67969a |
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03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
401d1c4f |
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30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
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#
bdf8fd76 |
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28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
0fd3d911 |
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22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
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#
2d6bf754 |
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22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
d30c7209 |
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22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
8a8d24bd |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
d1998a9f |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
c69cda25 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
caa4daa2 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
41575d8e |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
addf358b |
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24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
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27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
9e6ce621 |
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03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
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#
720f9e1f |
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02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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#
61b29b82 |
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03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
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#
62cbde4c |
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19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
b63ff2ae |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
1c16606a |
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21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
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#
d96c2604 |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
33c215af |
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15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
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25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
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09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
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06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
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20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
4e720779 |
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20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
1a67969a |
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03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
401d1c4f |
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30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
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#
bdf8fd76 |
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28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
0fd3d911 |
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22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
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#
2d6bf754 |
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22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
d30c7209 |
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22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
8a8d24bd |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
d1998a9f |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
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#
720f9e1f |
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02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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#
61b29b82 |
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03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
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#
62cbde4c |
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19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
b63ff2ae |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
1c16606a |
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21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
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#
d96c2604 |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
33c215af |
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15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
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25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
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09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
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06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
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20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
4e720779 |
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20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
1a67969a |
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03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
401d1c4f |
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30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
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#
bdf8fd76 |
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28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
0fd3d911 |
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22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
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#
2d6bf754 |
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22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
d30c7209 |
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22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
8a8d24bd |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
d1998a9f |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
c69cda25 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
caa4daa2 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
41575d8e |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
addf358b |
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24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
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27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
9e6ce621 |
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03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
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#
720f9e1f |
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02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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#
61b29b82 |
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03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
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#
62cbde4c |
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19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
b63ff2ae |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
1c16606a |
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21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
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#
d96c2604 |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
33c215af |
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15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
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25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
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09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
4e720779 |
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20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
401d1c4f |
|
30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
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#
bdf8fd76 |
|
28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
0fd3d911 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
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#
2d6bf754 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
d30c7209 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
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#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
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#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
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#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
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09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
401d1c4f |
|
30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
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#
bdf8fd76 |
|
28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
0fd3d911 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
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#
2d6bf754 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
d30c7209 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
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#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
4e720779 |
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20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
401d1c4f |
|
30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
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#
bdf8fd76 |
|
28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
0fd3d911 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
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#
2d6bf754 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
d30c7209 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
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27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
9e6ce621 |
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03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
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#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
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#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
1c16606a |
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21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
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#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
4e720779 |
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20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
401d1c4f |
|
30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
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#
bdf8fd76 |
|
28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
0fd3d911 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
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#
2d6bf754 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
d30c7209 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
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#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
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#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
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#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
401d1c4f |
|
30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
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#
bdf8fd76 |
|
28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
0fd3d911 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
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#
2d6bf754 |
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22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
d30c7209 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
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#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
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#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
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#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
401d1c4f |
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30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
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bdf8fd76 |
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28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
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0fd3d911 |
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22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
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2d6bf754 |
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22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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d30c7209 |
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22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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8a8d24bd |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
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d1998a9f |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
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c69cda25 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
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caa4daa2 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
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41575d8e |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
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addf358b |
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24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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5db92a0e |
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27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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9e6ce621 |
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03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
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720f9e1f |
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02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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61b29b82 |
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03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
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62cbde4c |
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19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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b63ff2ae |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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1c16606a |
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21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
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d96c2604 |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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33c215af |
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15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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2e2c514a |
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25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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c4448bdc |
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09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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d50d6817 |
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06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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50bf7d03 |
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20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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4e720779 |
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20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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1a67969a |
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03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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401d1c4f |
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30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
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bdf8fd76 |
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28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
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0fd3d911 |
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22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
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2d6bf754 |
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22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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d30c7209 |
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22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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8a8d24bd |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
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d1998a9f |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
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c69cda25 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
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caa4daa2 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
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41575d8e |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
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addf358b |
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24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
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27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
9e6ce621 |
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03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
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#
720f9e1f |
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02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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#
61b29b82 |
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03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
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#
62cbde4c |
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19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
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#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
401d1c4f |
|
30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
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#
bdf8fd76 |
|
28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
0fd3d911 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
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#
2d6bf754 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
d30c7209 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
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#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
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#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
401d1c4f |
|
30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
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#
bdf8fd76 |
|
28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
0fd3d911 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
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#
2d6bf754 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
|
#
d30c7209 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
caa4daa2 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
41575d8e |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
addf358b |
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24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
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27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
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#
720f9e1f |
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02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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#
61b29b82 |
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03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
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#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
b63ff2ae |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
1c16606a |
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21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
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#
d96c2604 |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
33c215af |
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15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
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25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
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09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
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06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
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20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
4e720779 |
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20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
1a67969a |
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03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
401d1c4f |
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30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
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#
bdf8fd76 |
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28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
0fd3d911 |
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22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
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#
2d6bf754 |
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22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
d30c7209 |
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22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
8a8d24bd |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
d1998a9f |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
c69cda25 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
caa4daa2 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
41575d8e |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
addf358b |
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24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
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27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
9e6ce621 |
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03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
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#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
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#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
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#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
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20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
4e720779 |
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20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
1a67969a |
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03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
401d1c4f |
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30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
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#
bdf8fd76 |
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28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
0fd3d911 |
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22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
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#
2d6bf754 |
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22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
d30c7209 |
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22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
8a8d24bd |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
d1998a9f |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
c69cda25 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
caa4daa2 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
41575d8e |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
addf358b |
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24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
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27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
9e6ce621 |
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03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
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#
720f9e1f |
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02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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#
61b29b82 |
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03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
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#
62cbde4c |
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19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
b63ff2ae |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
1c16606a |
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21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
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#
d96c2604 |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
33c215af |
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15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
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25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
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09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
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06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
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20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
4e720779 |
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20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
1a67969a |
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03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
401d1c4f |
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30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
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#
bdf8fd76 |
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28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
0fd3d911 |
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22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
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#
2d6bf754 |
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22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
d30c7209 |
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22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
8a8d24bd |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
d1998a9f |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
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#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
bdf8fd76 |
|
28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
0fd3d911 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
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#
2d6bf754 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
d30c7209 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
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#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
bdf8fd76 |
|
28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0fd3d911 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
|
#
2d6bf754 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
|
#
d30c7209 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
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#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
bdf8fd76 |
|
28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
0fd3d911 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
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#
2d6bf754 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
d30c7209 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
1a67969a |
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03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
bdf8fd76 |
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28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
0fd3d911 |
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22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
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#
2d6bf754 |
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22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
d30c7209 |
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22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
8a8d24bd |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
d1998a9f |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
c69cda25 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
caa4daa2 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
addf358b |
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24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
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27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
9e6ce621 |
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03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
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#
720f9e1f |
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02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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#
61b29b82 |
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03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
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#
62cbde4c |
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19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
b63ff2ae |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
1c16606a |
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21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
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#
d96c2604 |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
33c215af |
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15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
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25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
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09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
bdf8fd76 |
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28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
0fd3d911 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
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#
2d6bf754 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
d30c7209 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
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#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
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#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
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#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
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25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
bdf8fd76 |
|
28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
0fd3d911 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
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#
2d6bf754 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
d30c7209 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
8a8d24bd |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
d1998a9f |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
c69cda25 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
caa4daa2 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
41575d8e |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
addf358b |
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24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
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27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
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#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
bdf8fd76 |
|
28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0fd3d911 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
|
#
2d6bf754 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
|
#
d30c7209 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
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#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
bdf8fd76 |
|
28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
0fd3d911 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
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#
2d6bf754 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
d30c7209 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
1a67969a |
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03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
bdf8fd76 |
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28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
0fd3d911 |
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22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
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#
2d6bf754 |
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22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
d30c7209 |
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22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
8a8d24bd |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
d1998a9f |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
c69cda25 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
caa4daa2 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
addf358b |
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24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
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27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
9e6ce621 |
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03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
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#
720f9e1f |
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02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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#
61b29b82 |
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03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
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#
62cbde4c |
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19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
b63ff2ae |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
1c16606a |
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21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
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#
d96c2604 |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
33c215af |
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15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
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25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
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09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
bdf8fd76 |
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28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
0fd3d911 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
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#
2d6bf754 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
d30c7209 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
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#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
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#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
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#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
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25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
bdf8fd76 |
|
28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
0fd3d911 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
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#
2d6bf754 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
d30c7209 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
8a8d24bd |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
d1998a9f |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
c69cda25 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
caa4daa2 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
41575d8e |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
addf358b |
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24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
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27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
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#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
bdf8fd76 |
|
28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0fd3d911 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
|
#
2d6bf754 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
|
#
d30c7209 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
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#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
bdf8fd76 |
|
28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
0fd3d911 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
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#
2d6bf754 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
d30c7209 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
1a67969a |
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03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
bdf8fd76 |
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28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
0fd3d911 |
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22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
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#
2d6bf754 |
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22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
d30c7209 |
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22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
8a8d24bd |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
d1998a9f |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
c69cda25 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
caa4daa2 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
addf358b |
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24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
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27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
9e6ce621 |
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03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
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#
720f9e1f |
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02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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#
61b29b82 |
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03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
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#
62cbde4c |
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19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
b63ff2ae |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
1c16606a |
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21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
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#
d96c2604 |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
33c215af |
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15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
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25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
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09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
bdf8fd76 |
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28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
0fd3d911 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
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#
2d6bf754 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
d30c7209 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
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#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
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#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
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#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
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25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
bdf8fd76 |
|
28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
0fd3d911 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
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#
2d6bf754 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
d30c7209 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
8a8d24bd |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
d1998a9f |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
c69cda25 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
caa4daa2 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
41575d8e |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
addf358b |
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24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
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27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
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#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
bdf8fd76 |
|
28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0fd3d911 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
|
#
2d6bf754 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
|
#
d30c7209 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
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#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
bdf8fd76 |
|
28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
0fd3d911 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
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#
2d6bf754 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
d30c7209 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
1a67969a |
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03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
bdf8fd76 |
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28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
0fd3d911 |
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22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
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#
2d6bf754 |
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22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
d30c7209 |
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22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
8a8d24bd |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
d1998a9f |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
c69cda25 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
caa4daa2 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
addf358b |
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24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
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27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
9e6ce621 |
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03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
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#
720f9e1f |
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02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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#
61b29b82 |
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03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
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#
62cbde4c |
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19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
b63ff2ae |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
1c16606a |
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21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
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#
d96c2604 |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
33c215af |
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15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
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25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
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09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
bdf8fd76 |
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28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
0fd3d911 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
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#
2d6bf754 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
d30c7209 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
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#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
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#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
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#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
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25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
bdf8fd76 |
|
28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
0fd3d911 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
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#
2d6bf754 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
d30c7209 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
8a8d24bd |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
d1998a9f |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
c69cda25 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
caa4daa2 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
41575d8e |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
addf358b |
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24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
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27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
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#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
bdf8fd76 |
|
28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0fd3d911 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
|
#
2d6bf754 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
|
#
d30c7209 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
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#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
bdf8fd76 |
|
28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
0fd3d911 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
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#
2d6bf754 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
d30c7209 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
1a67969a |
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03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
bdf8fd76 |
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28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
0fd3d911 |
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22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
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#
2d6bf754 |
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22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
d30c7209 |
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22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
8a8d24bd |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
d1998a9f |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
c69cda25 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
caa4daa2 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
addf358b |
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24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
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27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
9e6ce621 |
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03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
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#
720f9e1f |
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02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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#
61b29b82 |
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03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
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#
62cbde4c |
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19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
b63ff2ae |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
1c16606a |
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21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
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#
d96c2604 |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
33c215af |
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15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
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25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
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09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
bdf8fd76 |
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28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
0fd3d911 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
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#
2d6bf754 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
d30c7209 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
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#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
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#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
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#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
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25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
bdf8fd76 |
|
28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
0fd3d911 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
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#
2d6bf754 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
d30c7209 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
8a8d24bd |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
d1998a9f |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
c69cda25 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
caa4daa2 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
41575d8e |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
addf358b |
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24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
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27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
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#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
bdf8fd76 |
|
28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0fd3d911 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
|
#
2d6bf754 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
|
#
d30c7209 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
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#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
bdf8fd76 |
|
28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
0fd3d911 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
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#
2d6bf754 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
d30c7209 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
1a67969a |
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03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
bdf8fd76 |
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28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
0fd3d911 |
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22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
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#
2d6bf754 |
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22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
d30c7209 |
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22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
8a8d24bd |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
d1998a9f |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
c69cda25 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
caa4daa2 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
addf358b |
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24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
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27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
9e6ce621 |
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03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
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#
720f9e1f |
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02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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#
61b29b82 |
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03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
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#
62cbde4c |
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19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
b63ff2ae |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
1c16606a |
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21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
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#
d96c2604 |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
33c215af |
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15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
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25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
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09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
bdf8fd76 |
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28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
0fd3d911 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
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#
2d6bf754 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
d30c7209 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
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#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
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#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
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#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
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25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
bdf8fd76 |
|
28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
0fd3d911 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
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#
2d6bf754 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
d30c7209 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
8a8d24bd |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
d1998a9f |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
c69cda25 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
caa4daa2 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
41575d8e |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
addf358b |
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24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
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27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
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#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
bdf8fd76 |
|
28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0fd3d911 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
|
#
2d6bf754 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
|
#
d30c7209 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
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#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
bdf8fd76 |
|
28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
0fd3d911 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
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#
2d6bf754 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
d30c7209 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
1a67969a |
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03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
bdf8fd76 |
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28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
0fd3d911 |
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22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
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#
2d6bf754 |
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22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
d30c7209 |
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22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
8a8d24bd |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
d1998a9f |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
c69cda25 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
caa4daa2 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
addf358b |
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24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
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27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
9e6ce621 |
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03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
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#
720f9e1f |
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02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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#
61b29b82 |
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03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
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#
62cbde4c |
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19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
b63ff2ae |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
1c16606a |
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21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
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#
d96c2604 |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
33c215af |
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15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
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25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
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09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
bdf8fd76 |
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28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
0fd3d911 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
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#
2d6bf754 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
d30c7209 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
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#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
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#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
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#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
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25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
bdf8fd76 |
|
28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
0fd3d911 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
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#
2d6bf754 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
d30c7209 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
8a8d24bd |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
d1998a9f |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
c69cda25 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
caa4daa2 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
41575d8e |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
addf358b |
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24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
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27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
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#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
bdf8fd76 |
|
28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0fd3d911 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
|
#
2d6bf754 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
|
#
d30c7209 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
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#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
bdf8fd76 |
|
28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
0fd3d911 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
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#
2d6bf754 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
d30c7209 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
1a67969a |
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03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
bdf8fd76 |
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28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
0fd3d911 |
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22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
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#
2d6bf754 |
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22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
d30c7209 |
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22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
8a8d24bd |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
d1998a9f |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
c69cda25 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
caa4daa2 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
addf358b |
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24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
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27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
9e6ce621 |
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03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
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#
720f9e1f |
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02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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#
61b29b82 |
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03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
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#
62cbde4c |
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19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
b63ff2ae |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
1c16606a |
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21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
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#
d96c2604 |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
33c215af |
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15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
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25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
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09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
bdf8fd76 |
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28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
0fd3d911 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
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#
2d6bf754 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
d30c7209 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
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#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
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#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
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#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
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25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
bdf8fd76 |
|
28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
0fd3d911 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
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#
2d6bf754 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
d30c7209 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
8a8d24bd |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
d1998a9f |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
c69cda25 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
caa4daa2 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
41575d8e |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
addf358b |
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24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
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27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
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#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
bdf8fd76 |
|
28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0fd3d911 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
|
#
2d6bf754 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
|
#
d30c7209 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
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#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
bdf8fd76 |
|
28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
0fd3d911 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
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#
2d6bf754 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
d30c7209 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
1a67969a |
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03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
bdf8fd76 |
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28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
0fd3d911 |
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22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
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#
2d6bf754 |
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22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
d30c7209 |
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22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
8a8d24bd |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
d1998a9f |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
c69cda25 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
caa4daa2 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
addf358b |
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24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
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27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
9e6ce621 |
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03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
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#
720f9e1f |
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02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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#
61b29b82 |
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03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
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#
62cbde4c |
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19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
b63ff2ae |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
1c16606a |
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21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
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#
d96c2604 |
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28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
33c215af |
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15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
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25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
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09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
bdf8fd76 |
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28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
0fd3d911 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
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#
2d6bf754 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
d30c7209 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
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#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
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#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
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#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
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25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
bdf8fd76 |
|
28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
0fd3d911 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
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#
2d6bf754 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
d30c7209 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
8a8d24bd |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
d1998a9f |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
c69cda25 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
caa4daa2 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
41575d8e |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
addf358b |
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24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
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27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
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#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
bdf8fd76 |
|
28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0fd3d911 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
|
#
2d6bf754 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
|
#
d30c7209 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
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#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
bdf8fd76 |
|
28-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
0fd3d911 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Use access methods for dev/uclass private data Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
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#
2d6bf754 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Rename ns16550 functions to lower case Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
d30c7209 |
|
22-Dec-2020 |
Simon Glass <sjg@chromium.org> |
serial: Update NS16550_t and struct NS16550 Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d1998a9f |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
c69cda25 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
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#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
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#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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#
61b29b82 |
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03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
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#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
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#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
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25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
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#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
addf358b |
|
24-Jun-2020 |
Walter Lozano <walter.lozano@collabora.com> |
core: add support for U_BOOT_DRIVER_ALIAS Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
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#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
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#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
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#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
5db92a0e |
|
27-Feb-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide UART base clock speed in ->getinfo() Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
9e6ce621 |
|
03-Apr-2020 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
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#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
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#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
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#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
720f9e1f |
|
02-Mar-2020 |
Wolfgang Wallner <wolfgang.wallner@br-automation.com> |
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
62cbde4c |
|
19-Dec-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support run-time configuration At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
b63ff2ae |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
1c16606a |
|
21-Dec-2019 |
Patrik Dahlström <risca@dalakolonin.se> |
serial: ns16550: Use old baud rate divisor for flushing if not given If baud_divisor is not set (i.e. == -1), we should use the baud divisor already in use for flushing the xmit register. If we don't flush the xmit register, then SPL will hang. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
33c215af |
|
15-Sep-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR At present PCI address transaction is not supported so drivers must manually read the correct BAR after reading the device tree info. The ns16550 has a suitable implementation, so move this code into the core DM support. Note that there is no live-tree equivalent at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the unclear comments in test.dts] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2e2c514a |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Allow serial to enabled/disabled in SPL At present this driver uses the wrong condition for including the code and drivers in SPL/TPL. Update it so that the code is only included if DM_SERIAL is enabled for SPL/TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
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06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
1a67969a |
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03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
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06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
1a67969a |
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03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
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06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
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06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
50bf7d03 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4e720779 |
|
20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
1a67969a |
|
03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
|
#
c4448bdc |
|
09-Jan-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d50d6817 |
|
06-Dec-2018 |
Sekhar Nori <nsekhar@ti.com> |
spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but CONFIG_SPL_PCI_SUPPORT disabled, results in following linker error: lib/built-in.o: In function `fdtdec_get_pci_bar32': lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32' fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32' This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c while SPL build does not descend into drivers/pci directory in drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled. Fix this by applying appropriate #define guards in lib/fdtdec.c. It looks like ns16550.c has the same problem, so fixed that too. To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI (enables use of CONFIG_IS_ENABLED() macro). Suggested-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
50bf7d03 |
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20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Provide ->getinfo() implementation New callback will supply necessary information, for example, to ACPI SPCR table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
4e720779 |
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20-Nov-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
serial: ns16550: Read reg-io-width from device tree Cache the value of the reg-io-width property for the future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
1a67969a |
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03-Dec-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
Revert "serial: ns16550: fix debug uart putc called before init" This reverts commit 6f57c34473d37b8da5e6a3764d0d377d748aeef1 since it does not seem to work at least on rk3399. The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud rate prescaler register is readable only when USR[0] is zero. Since this bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather drop this than making the ns16550 debug uart more platform specific. Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com
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#
9ad3b049 |
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02-Nov-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: add setconfig support Add possibility to update the serial parity used. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
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#
46879196 |
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24-Oct-2018 |
Bin Meng <bmeng.cn@gmail.com> |
serial: Remove DM_FLAG_PRE_RELOC flag in various drivers When a driver declares DM_FLAG_PRE_RELOC flag, it wishes to be bound before relocation. However due to a bug in the DM core, the flag only takes effect when devices are statically declared via U_BOOT_DEVICE(). This bug has been fixed recently by commit "dm: core: Respect drivers with the DM_FLAG_PRE_RELOC flag in lists_bind_fdt()", but with the fix, it has a side effect that all existing drivers that declared DM_FLAG_PRE_RELOC flag will be bound before relocation now. This may expose potential boot failure on some boards due to insufficient memory during the pre-relocation stage. To mitigate this potential impact, the following changes are implemented: - Remove DM_FLAG_PRE_RELOC flag in the driver, if the driver only supports configuration from device tree (OF_CONTROL) - Keep DM_FLAG_PRE_RELOC flag in the driver only if the device is statically declared via U_BOOT_DEVICE() - Surround DM_FLAG_PRE_RELOC flag with OF_CONTROL check, for drivers that support both statically declared devices and configuration from device tree Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
6f57c344 |
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09-Aug-2018 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
serial: ns16550: fix debug uart putc called before init If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), let's rather ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
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#
5d754197 |
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27-Aug-2018 |
Lokesh Vutla <lokeshvutla@ti.com> |
serial: omap: Introduce DM specific omap serial Add driver model support for OMAP_SERIAL while reusing the functions in ns16550.c Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Tested-by: Derald D. Woods <woods.technical@gmail.com>
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#
b051eecb |
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14-Jun-2018 |
Ley Foon Tan <ley.foon.tan@intel.com> |
serial: ns16550: Add reset ctrl to driver Add code to reset all reset signals as in serial DT node. A reset property is an optional feature, so do not fail if a reset property is not present. If a reset property is discovered, then use it to deassert, thus bringing the IP out of reset. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
78b7d37b |
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15-Feb-2018 |
Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> |
ns16550: Fix mem mapped endian check Do a explicit check for CONFIG_SYS_BIG_ENDIAN and CONFIG_SYS_LITTLE_ENDIAN to avoid errors on platforms where both are undefined (x86). Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> Reviewed-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
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#
4dbf9bed |
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15-Jan-2018 |
Mario Six <mario.six@gdsys.cc> |
serial: ns16550: Fix style violation Clarify the computation precedence in two ternary operator constructions. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc>
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#
7fded0ce |
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16-Aug-2017 |
Stefan Roese <sr@denx.de> |
Revert "serial: ns16550: Add RX interrupt buffer support" This reverts commit 6822cf3ec7c8768b8727573b8f4b2cb3d870b881. As Bin Meng has tested and pointed out, we don't need the RX interrupt for the RX buffer support at all. Just reading all available characters into a buffer is sufficient to solve the problem with the dropped characters upon long lines pasted into the U-Boot prompt. Since this RX buffer support can be implemented in a generic way, without any device specifica (e.g. for the ns16550), I'll post a new patch with a new serial RX buffer support for DM, which all DM based serial drivers can use. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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6822cf3e |
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14-Jul-2017 |
Stefan Roese <sr@denx.de> |
serial: ns16550: Add RX interrupt buffer support Pasting longer lines into the U-Boot console prompt sometimes leads to characters missing. One problem here is the small 16-byte FIFO of the legacy NS16550 UART, e.g. on x86 platforms. This patch now introduces a Kconfig option to enable RX interrupt buffer support for NS16550 style UARTs. With this option enabled, I was able paste really long lines into the U-Boot console, without any characters missing. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> [trini: Guard ns16550_serial_remove with CONFIG_IS_ENABLED(SERIAL_PRESENT) to match struct assignment] Signed-off-by: Tom Rini <trini@konsulko.com>
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#
db9f8f6a |
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12-Jun-2017 |
Simon Glass <sjg@chromium.org> |
dm: serial: ns16550: Convert to livetree Update this driver to support a live device tree. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Tested-on: Beaver, Jetson-TK1
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#
3d40479f |
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07-Jun-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
rockchip: ns16550: dm: convert fdt_get to dev_read With the new dev_read functions available, we can convert the rockchip architecture-specific drivers and common drivers used by these devices over to the dev_read family of calls. This covers the serial driver (ns16550 and compatible) used for the Rockchip devices. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
a821c4af |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: Rename dev_addr..() functions These support the flat device tree. We want to use the dev_read_..() prefix for functions that support both flat tree and live tree. So rename the existing functions to avoid confusion. In the end we will have: 1. dev_read_addr...() - works on devices, supports flat/live tree 2. devfdt_get_addr...() - current functions, flat tree only 3. of_get_address() etc. - new functions, live tree only All drivers will be written to use 1. That function will in turn call either 2 or 3 depending on whether the flat or live tree is in use. Note this involves changing some dead code - the imx_lpi2c.c file. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
89024ddc |
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12-May-2017 |
Tom Rini <trini@konsulko.com> |
TI: Drop 'CONFIG_OMAP' In the two cases in the code where we use CONFIG_OMAP as a useful test currently we can make use of CONFIG_ARCH_OMAP2PLUS instead. With that changed we can drop all defines of CONFIG_OMAP. While in here, CONFIG_OMAP3430 is only defined and then never used, so drop. Signed-off-by: Tom Rini <trini@konsulko.com>
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#
a52cf086 |
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22-Apr-2017 |
Lokesh Vutla <lokeshvutla@ti.com> |
serial: omap: Support debug UART Add debug UART functions to permit omap specific ns16550 to provide an early debug UART. This is mostly in common with DEBUG_UART_NS16550 except for Mode definition register which is required for selecting UART mode(16x auto-baud or 13x mode). Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
6f8c351e |
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27-Mar-2017 |
Alexandru Gagniuc <alex.g@adaptrum.com> |
serial: ns16550: Link in the DM driver when when using platdata Do not condition the compilation of the U_BOOT_DRIVER by !OF_PLATDATA. This is inconsistent with the majority of other drivers. This also blocks OF_PLATDATA boards with an 16550-compatible serial from using serial in SPL. Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com> Reviewed-by: Simon Glass <sjg@chromium.org> Added tweak for rock to avoid a TPL build failure: Signed-off-by: Simon Glass <sjg@chromium.org>
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#
e160f7d4 |
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17-Jan-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
17fa0326 |
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18-Jan-2017 |
Heiko Schocher <hs@denx.de> |
serial, ns16550: bugfix: ns16550 fifo not enabled commit: 65f83802b7a5b "serial: 16550: Add getfcr accessor" breaks u-boot commandline working with long commands sending to the board. Since the above patch, you have to setup the fcr register. For board/archs which enable OF_PLATDATA, the new field fcr in struct ns16550_platdata is not filled with a default value ... This leads in not setting up the uarts fifo, which ends in problems, when you send long commands to u-boots commandline. Detected this issue with automated tbot tests on am335x based shc board. The error does not popup, if you type commands. You need to copy&paste a long command to u-boots commandshell (or send a long command with tbot) Possible boards/plattforms with problems: ./arch/arm/cpu/arm926ejs/lpc32xx/devices.c ./arch/arm/mach-tegra/board.c ./board/overo/overo.c ./board/quipos/cairo/cairo.c ./board/logicpd/omap3som/omap3logic.c ./board/logicpd/zoom1/zoom1.c ./board/timll/devkit8000/devkit8000.c ./board/lg/sniper/sniper.c ./board/ti/beagle/beagle.c ./drivers/serial/serial_rockchip.c Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Tested-by: Adam Ford <aford173@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
0b060eef |
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30-Nov-2016 |
Marek Vasut <marex@denx.de> |
serial: 16550: Add Ingenic JZ4780 support Add compatibility string for the Ingenic JZ4780 SoC, the necessary UART enable bit into FCR and register shift. Neither are encoded in the DTS coming from Linux, so we need to support it this way. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
79fd9281 |
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30-Nov-2016 |
Marek Vasut <marex@denx.de> |
serial: 16550: Add port type as driver data Add driver data to each compatible string to identify the type of the port. Since all the ports in the driver are entirely compatible with 16550 for now, all are marked with PORT_NS16550. But, there are ports which have specific quirks, like the JZ4780 UART, which do not have any DT property to denote the quirks. Instead, Linux uses the compatible string to discern such ports and enable the necessary quirks. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org>
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#
65f83802 |
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30-Nov-2016 |
Marek Vasut <marex@denx.de> |
serial: 16550: Add getfcr accessor Add function which allows fetching the default FCR register setting from platform data for DM , while retaining old behavior for non-DM by returning UART_FCRVAL. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
021abf69 |
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26-Sep-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
Revert "ns16650: Make sure we have CONFIG_CLK set before using infrastructure" This reverts commit 82f5279b0cd99a9163d34cfe926d0316d9dc0d37. The build failure of k2*evm boards was fixed in a different way by the previous commit. It is nasty to patch generic drivers around with #ifdef CONFIG_CLK just for the KeyStone's matter. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
ab895d6a |
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30-Sep-2016 |
Alexandre Courbot <acourbot@nvidia.com> |
serial: ns16550: Handle -ENOENT when requesting clock When calling clk_get_by_index(), fall back to the legacy method of getting the clock if -ENOENT is returned. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com>
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#
82f5279b |
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22-Sep-2016 |
Tom Rini <trini@konsulko.com> |
ns16650: Make sure we have CONFIG_CLK set before using infrastructure We cannot call on the CONFIG_CLK based clk_get_rate function unless CONFIG_CLK is set. Signed-off-by: Tom Rini <trini@konsulko.com>
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#
50fce1d5 |
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08-Sep-2016 |
Paul Burton <paul.burton@imgtec.com> |
serial: ns16550: Support clocks via phandle Previously ns16550 compatible UARTs probed via device tree have needed their device tree nodes to contain a clock-frequency property. An alternative to this commonly used with Linux is to reference a clock via a phandle. This patch allows U-Boot to support that, retrieving the clock frequency by probing the appropriate clock device. For example, a system might choose to provide the UART base clock as a reference to a clock common to multiple devices: sys_clk: clock { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <10000000>; }; uart0: uart@10000000 { compatible = "ns16550a"; reg = <0x10000000 0x1000>; clocks = <&sys_clk>; }; uart1: uart@10000000 { compatible = "ns16550a"; reg = <0x10001000 0x1000>; clocks = <&sys_clk>; }; This removes the need for the frequency information to be duplicated in multiple nodes and allows the device tree to be more descriptive of the system. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
b2927fba |
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04-Jul-2016 |
Simon Glass <sjg@chromium.org> |
dm: serial: ns16550: Update to support of-platdata With of-platdata this driver cannot know the format of the of-platdata struct, so we cannot use generic code for accessing the of-platdata. Each SoC that uses this driver will need to set up ns16550's platdata for it. So don't compile in the generic code. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
03c6f176 |
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24-May-2016 |
Marek Vasut <marex@denx.de> |
serial: 16550: Drop OMAP1510 support The CONFIG_OMAP1510 is no longer defined, so remove this dead code. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Nishanth Menon <nm@ti.com>
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#
fa4ce723 |
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24-May-2016 |
Marek Vasut <marex@denx.de> |
serial: 16550: Make serial_io/out_shift available to debug mode The ns16550 driver needs serial_in_shift() and serial_out_shift() when compiled in debug UART mode, so shift the DM_SERIAL check a little to make these functions available. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
df8ec55d |
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17-May-2016 |
Paul Burton <paul.burton@imgtec.com> |
dm: ns16550: Don't map_physmem for I/O ports If the UART is to be accessed using I/O port accessors (inb & outb) then using map_physmem doesn't make sense, since it operates in a different memory space. Remove the call to map_physmem when CONFIG_SYS_NS16550_PORT_MAPPED is defined, allowing I/O port addresses to not be mangled by the incorrect mapping. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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59b35ddd |
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16-Feb-2016 |
Michal Simek <michal.simek@xilinx.com> |
dm: ns16550: Add support for reg-offset property reg-offset is the part of standard 8250 binding in the kernel. It is shifting start of address space by reg-offset. On Xilinx platform this offset is typically 0x1000. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Moved the new field to the end of the struct to avoid problems: Signed-off-by: Simon Glass <sjg@chromium.org>
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e5e88c65 |
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29-Feb-2016 |
Tom Rini <trini@konsulko.com> |
Revert "dm: ns16550: Add support for reg-offset property" This reverts commit d9a3bec682f9756621615f4306718a356a3230e3. While this is a correct change to do long term it unfortunately breaks a number of platforms that are using pdata and not named struct members so they are getting all of their data after 'base' incorrect. Acked-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Tom Rini <trini@konsulko.com>
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d9a3bec6 |
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16-Feb-2016 |
Michal Simek <michal.simek@xilinx.com> |
dm: ns16550: Add support for reg-offset property reg-offset is the part of standard 8250 binding in the kernel. It is shifting start of address space by reg-offset. On Xilinx platform this offset is typically 0x1000. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
cc4228f9 |
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14-Dec-2015 |
Thomas Chou <thomas@wytron.com.tw> |
ns16550: zap the rockchip serial compatible string Zap the rockchip serial compatible string, because rockchip serial has "snps,dw-apb-uart" compatible string in the dts. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org>
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#
b7e29834 |
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13-Dec-2015 |
Simon Glass <sjg@chromium.org> |
dm: ns16550: Allow the driver to be omitted if requested Allow the ns16550 debug UART to be used without the full driver. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Thomas Chou <thomas@wytron.com.tw>
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#
fcc0a877 |
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29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: serial: Convert ns16550 driver to use driver model PCI API Use the driver model version of the function to find the BAR. This updates the fdtdec function, of which ns16550 is the only user. The fdtdec_get_pci_bdf() function is dropped for several reasons: - with driver model we should use 'struct udevice *' rather than passing the device tree offset explicitly - there are no other users in the tree - the function parses for information which is already available in the PCI device structure (specifically struct pci_child_platdata which is available at dev_get_parent_platdata(dev) Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
b7e5a643 |
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04-Dec-2015 |
Simon Glass <sjg@chromium.org> |
dm: serial: ns16550: Add pre-reloc flag to the driver For platforms that don't use device tree in SPL the only way to mark this driver as 'required by relocation' is with the DM_FLAG_PRE_RELOC flag. Add this to ensure that the driver is bound. Fixes: fde7e18938d8 ("dm: tegra: pci: Move CONFIG_PCI_TEGRA to Kconfig") Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Stephen Warren <swarren@nvidia.com> Acked-by: Thomas Chou <thomas@wytron.com.tw>
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80e06146 |
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28-Nov-2015 |
Thomas Chou <thomas@wytron.com.tw> |
ns16550: change reg-shift property default to zero Change reg-shift property default to zero. When the integer property is missing, it should be taken as zero. This is consistent to Linux drivers/tty/serial/of_serial.c. The x86 and most powerpc use reg-shift of 0. Most others use reg-shift of 2. While reg-shift of 1 is rarely used. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Acked-by: Simon Glass <sjg@chromium.org>
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#
a51dbebf |
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16-Nov-2015 |
huang lin <hl@rock-chips.com> |
rockchip: serial driver support rk3036 Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
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#
4fb60552 |
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19-Nov-2015 |
Thomas Chou <thomas@wytron.com.tw> |
ns16550: zap CONFIG_NS16550_SERIAL Zap CONFIG_NS16550_SERIAL, as the unification of ns16550 drivers is completed. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
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#
8e62d32e |
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19-Nov-2015 |
Thomas Chou <thomas@wytron.com.tw> |
ns16550: add generic binding to unify the drivers Add generic binding to unify ns16550 drivers. There are several drivers using almost the same code, such as serial_dw, serial_keystone, serial_omap, serial_ppc, serial_rockchip, serial_tegra.c, and serial_x86. But each is platform specific. The key difference between these drivers is the way to get input clock frequency. With this unified approach, fixed clock frequency should be extracted from "clock-frequency" property of device tree blob. If this property is not available, the macro CONFIG_SYS_NS16550_CLK will be used. It can be a constant or a function to get clock, eg, get_serial_clock(). Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de> Acked-by: Simon Glass <sjg@chromium.org>
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77d7b5cd |
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19-Nov-2015 |
Thomas Chou <thomas@wytron.com.tw> |
ns16550: change map_sysmem to map_physmem Change map_sysmem() to map_physmem(,,MAP_NOCACHE). Though map_sysmem() can be used to map system memory, it might be wrong to use it for I/O ports. The map_physmem() serves the same purpose to translate physical address to virtual address with the additional flag to take care of cache property. Most drivers use map_physmem() since I/O ports access should be uncached. As ns16550 is a driver, it should use map_physmem() rather than map_sysmem(). Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org>
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97b05973 |
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18-Oct-2015 |
Simon Glass <sjg@chromium.org> |
debug_uart: Adjust the declaration of debug_uart_init() We want to be able to add other common code to this function. So change the driver's version to have an underscore before it, just like _debug_uart_putc(). Define debug_uart_init() to call this version. Update all drivers to this new method. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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4e9838c1 |
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11-Aug-2015 |
Simon Glass <sjg@chromium.org> |
dm: Use dev_get_addr() where possible This is a convenient way for a driver to get the hardware address of a device, when regmap or syscon are not being used. Change existing callers to use it as an example to others. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org>
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0f925822 |
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11-Aug-2015 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
of: clean up OF_CONTROL ifdef conditionals We have flipped CONFIG_SPL_DISABLE_OF_CONTROL. We have cleansing devices, $(SPL_) and CONFIG_IS_ENABLED(), so we are ready to clear away the ugly logic in include/fdtdec.h: #ifdef CONFIG_OF_CONTROL # if defined(CONFIG_SPL_BUILD) && !defined(SPL_OF_CONTROL) # define OF_CONTROL 0 # else # define OF_CONTROL 1 # endif #else # define OF_CONTROL 0 #endif Now CONFIG_IS_ENABLED(OF_CONTROL) is the substitute. It refers to CONFIG_OF_CONTROL for U-boot proper and CONFIG_SPL_OF_CONTROL for SPL. Also, we no longer have to cancel CONFIG_OF_CONTROL in include/config_uncmd_spl.h and scripts/Makefile.spl. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Linus Walleij <linus.walleij@linaro.org>
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6e780c7a |
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23-Jun-2015 |
Simon Glass <sjg@chromium.org> |
ns16550: Improve debug UART so it can work with 32-bit access Since Rockchip requires 32-bit serial access, add this to the driver. Refactor a little to make this easier. Signed-off-by: Simon Glass <sjg@chromium.org>
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90914008 |
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12-May-2015 |
Simon Glass <sjg@chromium.org> |
dm: ns16550: Support CONFIG_SYS_NS16550_MEM32 with driver model This option is used by some boards, so support it with driver model. This is really ugly - we should rewrite this driver once all users are moved to driver model. Signed-off-by: Simon Glass <sjg@chromium.org>
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4f60166c |
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24-Apr-2015 |
Axel Lin <axel.lin@ingics.com> |
serial: ns16550: Remove hard-coded baud_divisor setting This was accidentally added by commit dd0b0122bacc "serial: ns16550: Add an option to specify the debug UART register shift". Remove it. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Simon Glass <sjg@chromium.org>
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ab9fd2e8 |
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27-Feb-2015 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Remove unnecessary init on UART setup It is not necessary to write a zero baud rate to the device, and for some chips this will cause problems. Drop this code. Signed-off-by: Simon Glass <sjg@chromium.org>
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363e6da1 |
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27-Feb-2015 |
Simon Glass <sjg@chromium.org> |
dm: ns16550: Support non-byte register spacing with driver model Allow this driver to support boards where the register shift is not 0. This fixes some compiler warnings which appear in that case. Signed-off-by: Simon Glass <sjg@chromium.org>
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dd0b0122 |
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27-Feb-2015 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Add an option to specify the debug UART register shift This UART permits different register spacing. To support the debug UART on devices which have a spacing other than 1 byte, allow the shift value to be specified. Signed-off-by: Simon Glass <sjg@chromium.org>
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0eb25b61 |
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22-Mar-2015 |
Joe Hershberger <joe.hershberger@ni.com> |
common: Make sure arch-specific map_sysmem() is defined In the case where the arch defines a custom map_sysmem(), make sure that including just mapmem.h is sufficient to have these functions as they are when the arch does not override it. Also split the non-arch specific functions out of common.h Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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20379c11 |
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28-Feb-2015 |
Axel Lin <axel.lin@ingics.com> |
serial: ns16550: Fix build error due to a typo Fix trivial typo. Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Axel Lin <axel.lin@ingics.com>
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21d00436 |
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26-Jan-2015 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Support debug UART Add debug UART functions to permit ns16550 to provide an early debug UART. Try to avoid using the stack so that this can be called from assembler before a stack is set up (at least on ARM and PowerPC). Signed-off-by: Simon Glass <sjg@chromium.org>
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76571674 |
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26-Jan-2015 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Add access functions that don't need platdata For the debug UART we need to be able to provide any parameters before driver model is set up. Add parameters to the low-level access functions to make this possible. Signed-off-by: Simon Glass <sjg@chromium.org>
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3db886a5 |
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31-Dec-2014 |
Bin Meng <bmeng.cn@gmail.com> |
serial: ns16550: Support ns16550 compatible pci uart devices There are many pci uart devices which are ns16550 compatible. We can describe them in the board dts file and use it as the U-Boot serial console as specified in the chosen node 'stdout-path' property. Those pci uart devices can have their register be memory-mapped, or i/o-mapped. The driver will try to use the memory-mapped register if the reg property in the node has an entry to describe the memory-mapped register, otherwise i/o-mapped register will be used. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
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956a8bae |
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10-Nov-2014 |
Gregoire Gentil <gregoire@gentil.com> |
ns16550.c: Fix for ns16550 driver hanging on OMAP4 The same problem that is seen on some OMAP3 is also seen on some OMAP4 so include them in the test in order to prevent some hangs during SPL. [trini: Re-word commit message, make apply cleanly] Signed-off-by: Tom Rini <trini@ti.com>
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1f77690e |
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10-Oct-2014 |
Simon Glass <sjg@chromium.org> |
dm: serial: ns16550: Add a cast to the I/O operations This generates a warning when driver model is enabled, so fix it by adding a cast. Signed-off-by: Simon Glass <sjg@chromium.org>
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11c1a878 |
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22-Oct-2014 |
Simon Glass <sjg@chromium.org> |
dm: ns16550: Correct the probe logic for platform data The probe logic sets up the pointer to the platform data in the device tree decode method. It should be done in the probe() method, and anyway the device tree decode method can't be used when CONFIG_OF_CONTROL is not enabled. Fix these two problems. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@ti.com>
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167efe01 |
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22-Oct-2014 |
Simon Glass <sjg@chromium.org> |
dm: ns16550: Use an address instead of a pointer for the uart base It is inconvenient to have to use casts when specifying platform data. Also it is not strictly correct, since we should use map_sysmem() to convert an address to a pointer. Adjust the platform data to use an address. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@ti.com>
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aea2be20 |
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22-Oct-2014 |
Simon Glass <sjg@chromium.org> |
dm: serial: ns16550: Correct logic for checking for character There is a bug in the logic which checks for an available character. This can cause invalid characters to be received - this was noticed on beaglebone. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@ti.com>
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12e431b2 |
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04-Sep-2014 |
Simon Glass <sjg@chromium.org> |
dm: serial: Add driver model support for ns16550 Add driver model support so that ns16550 can support operation both with and without driver model. The driver needs a clock frequency so cannot stand alone unfortunately. The clock frequency must be provided by a separate driver. Signed-off-by: Simon Glass <sjg@chromium.org>
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8bbe33c8 |
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04-Sep-2014 |
Simon Glass <sjg@chromium.org> |
dm: serial: Collect common baud rate code in ns16550 The same sequence is used in several places, so move it into a function. Note that UART_LCR_BKSE is an alias for UART_LCR_DLAB. Signed-off-by: Simon Glass <sjg@chromium.org>
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fa54eb12 |
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04-Sep-2014 |
Simon Glass <sjg@chromium.org> |
dm: serial: Move baud rate calculation to ns16550.c Move the function that calculates the baud rate divisor into ns16550.c so it can be used by that file. Signed-off-by: Simon Glass <sjg@chromium.org>
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8ac22a60 |
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30-Jul-2014 |
Masahiro Yamada <yamada.m@jp.panasonic.com> |
omap: clean-up dead configs The following configs are not defined at all. - CONFIG_OMAP1510 - CONFIG_OMAP_1510P1 - CONFIG_OMAP_SX1 - CONFIG_OMAP3_DMA - CONFIG_OMAP3_ZOOM2 - CONFIG_OMAP_INNOVATOR Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Tom Rini <trini@ti.com>
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7c387646 |
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15-Jul-2014 |
Khoronzhuk, Ivan <ivan.khoronzhuk@ti.com> |
keystone2: use CONFIG_SOC_KEYSTONE in common places Use CONFIG_SOC_KEYSTONE in common places instead of defining a lot of "if def .. || if def " for different Keystone2 SoC types. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
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d57dee57 |
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09-Apr-2014 |
Karicheri, Muralidharan <m-karicheri2@ti.com> |
serial: nsl16550: add hw flow control support keystone serial hw support hw flow control. This patch enables hw flow control for keystone EVMs as an optional feature based on CONFIG_SERIAL_HW_FLOW_CONTROL. Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
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ef509b90 |
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04-Apr-2014 |
Vitaly Andrianov <vitalya@ti.com> |
k2hk: add support for k2hk SOC and EVM k2hk EVM is based on Texas Instruments Keystone2 Hawking/Kepler SoC. Keystone2 SoC has ARM v7 Cortex-A15 MPCore processor. Please refer the ti/k2hk_evm/README for details on the board, build and other information. This patch add support for keystone architecture and k2hk evm. Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: WingMan Kwok <w-kwok2@ti.com> Signed-off-by: Sandeep Nair <sandeep_n@ti.com>
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456ccfdf |
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20-Dec-2013 |
Tom Rini <trini@ti.com> |
TI:omap3: Drop omap3_zoom2 The omap3_zoom2 board has not been updated for a correct CONFIG_SYS_HZ and Tom Rix's email has long been bouncing. Signed-off-by: Tom Rini <trini@ti.com>
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9ed6e412 |
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01-Jul-2013 |
TENART Antoine <atenart@adeneo-embedded.com> |
Prepare for TI816X : reuse existing code from TI814X Rename some CONFIG_TI814X to a more generic CONFIG_TI81XX Signed-off-by: Antoine Tenart <atenart@adeneo-embedded.com> [trini: Adapt for CONFIG_OMAP_COMMON changes, AM43XX] Signed-off-by: Tom Rini <trini@ti.com>
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#
57180408 |
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30-Jul-2013 |
Lokesh Vutla <lokeshvutla@ti.com> |
ARM: AM43xx: Add build support Add AM43xx support in the required places Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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7f5eef93 |
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03-Jun-2013 |
Tom Rini <trini@ti.com> |
arm: Remove OMAP2420H4 and all omap24xx support The omap2420H4 was the only mainline omap24xx board. Prior to being fixed by Jon Hunter in time for v2013.04 it had been functionally broken for a very long time. Remove this board as there's not been interest in it in U-Boot for quite a long time. Signed-off-by: Tom Rini <trini@ti.com>
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fd2aeac5 |
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28-Mar-2013 |
Manfred Huber <man.huber@arcor.de> |
omap3_beagle: Flush UART3 xmit on enable if TEMT is broken Flush UART3 xmit on enable if TEMT is broken On some OMAP3 devices when UART3 is configured for boot mode before SPL starts only THRE bit is set. We have to empty the transmitter before initialization starts. This patch avoids the use of CONFIG_SYS_NS16550_BROKEN_TEMT. Signed-off-by: Manfred Huber <man.huber@arcor.de> Tested-by: Javier Martinez Canillas <javier@dowhile0.org> Tested-by: Andreas Bießmann <andreas.devel@googlemail.com>
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6213a68f |
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15-Mar-2013 |
Matt Porter <mporter@ti.com> |
ns16550: enable quirks for ti814x TI814X requires the same quirks as AM33XX to be enabled. Signed-off-by: Matt Porter <mporter@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
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69e06832 |
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05-Mar-2013 |
Simon Glass <sjg@chromium.org> |
serial: ns16550: Remove unwanted cast This cast does not seem correct, since we should be writing to a pointer, not a ulong. This fixes the following warning on nds32: -ns16550.c:49: warning: passing argument 2 of 'writeb' makes pointer from integer without a cast Signed-off-by: Simon Glass <sjg@chromium.org>
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7de0fe1a |
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06-Jan-2013 |
Javier Martinez Canillas <javier@dowhile0.org> |
serial/ns16550: add an option to avoid hanging on broken platforms Some platforms (e.g. IGEPv2 board) has a broken ns16550 UART that does not set the TEMT bit when the transmitter is empty in SPL. This makes U-Boot to hang while waiting for TEMT to be set. Add a new option to avoid this: CONFIG_SYS_NS16550_BROKEN_TEMT 16550 UART set the Transmitter Empty (TEMT) Bit when all output has finished and the transmitter is totally empty. U-Boot waits for this bit to be set to initialize the serial console. On some broken platforms this bit is not set in SPL making U-Boot to hang while waiting for TEMT. Define this option to avoid it. Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
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cb55b332 |
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18-Sep-2012 |
Scott Wood <scottwood@freescale.com> |
serial/ns16550: wait for TEMT before initializing TEMT is set when the transmitter is totally empty and all output has finished. This prevents output problems (including a loss of synchronization observed on p2020 that persisted for quite a while) if SPL has output still on its way out. Signed-off-by: Scott Wood <scottwood@freescale.com> -- v2: fixed typo in subject, and explained what the bit does in the changelog
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f2041388 |
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15-Sep-2012 |
Marek Vasut <marex@denx.de> |
serial: ns16550: Call usbtty_poll only in non-SPL build Having both USBTTY and CONFIG_SERIAL_MULTI enabled in SPL, the usbtty.c file is protected in Makefile to not be compiled into the SPL. Yet, the ns16550 serial driver does not contain such protection. Add it to avoid missing symbol error. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Marek Vasut <marek.vasut@gmail.com> Cc: Tom Rini <trini@ti.com>
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99b603e7 |
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09-Jul-2012 |
Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com> |
serial/ns16550: ns16550 has a different register layout on SOC_DA8XX also fix NS16550_init() as we need 16x divider Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com> Acked-by: Christian Riesch <christian.riesch@omicron.at> Tested-by: Christian Riesch <christian.riesch@omicron.at> Acked-by: Sughosh Ganu <urwithsughosh@gmail.com> Tested-by: Sughosh Ganu <urwithsughosh@gmail.com>
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5289e83a |
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13-Oct-2011 |
Chandan Nath <chandan.nath@ti.com> |
ARM:AM33XX: Add support for TI AM335X EVM This patch adds basic support for booting the board. This patch adds support for the UART necessary to get to the u-boot prompt. Signed-off-by: Chandan Nath <chandan.nath@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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f8df9d0d |
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15-Oct-2011 |
Simon Glass <sjg@chromium.org> |
NS16550: trivial code clean for checkpatch This removes most checkpatch warnings from the ns16550 driver and its header. Signed-off-by: Simon Glass <sjg@chromium.org>
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79df1208 |
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01-Sep-2011 |
Dave Aldridge <fovsoft@gmail.com> |
ns16550: change to allow 32 bit access to registers If CONFIG_SYS_NS16550_MEM32 is defined then 32 bit memory mapped access will be used to read/write the uart registers. This is especially useful for SoC devices that implement 16550 compatible uarts but that have peripheral access width constraints. Signed-off-by: Dave Aldridge <fovsoft@gmail.com>
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a160ea0b |
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27-Oct-2010 |
Prafulla Wadaskar <prafulla@marvell.com> |
Serial: ns16550: Add support for CONFIG_SYS_NS16550_IER macro On some processors this ier register configuration is different for ex. Marvell Armada100 This patch introduce CONFIG_SYS_NS16550_IER macro support to unconditionally initialize this register. Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
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1a2d9b30 |
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12-Oct-2010 |
Stefan Roese <sr@denx.de> |
ns16550: Add WATCHDOG_RESET to putc for short watchdog timeout boards Call watchdog_reset() upon newline. This is done here in putc since the environment code uses a single puts() to print the complete envrironment upon "printenv". So we can't put this watchdog call in puts(). This is needed for boards with a very short watchdog timeout, like the lwmon5 with a 100ms timeout. Without this patch this board resets in the commands with long outputs, like "printenv" or "fdt print". Note that the image size is not increased with this patch when CONFIG_HW_WATCHDOG or CONFIG_WATCHDOG are not defined since the compiler optimizes this additional code away. Signed-off-by: Stefan Roese <sr@denx.de> Fix typo in comment. Signed-off-by: Wolfgang Denk <wd@denx.de>
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167cdad1 |
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23-Apr-2010 |
Graeme Russ <graeme.russ@gmail.com> |
SERIAL: Enable port-mapped access The x86 architecture exclusively uses Port-Mapped I/O (inb/outb) to access the 16550 UARTs. This patch mimics how Linux selects between Memory-Mapped and Port-Mapped I/O. This allows x86 boards to use CONFIG_SERIAL_MUTLI and drop the custom serial port driver Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
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a47a12be |
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15-Apr-2010 |
Stefan Roese <sr@denx.de> |
Move arch/ppc to arch/powerpc As discussed on the list, move "arch/ppc" to "arch/powerpc" to better match the Linux directory structure. Please note that this patch also changes the "ppc" target in MAKEALL to "powerpc" to match this new infrastructure. But "ppc" is kept as an alias for now, to not break compatibility with scripts using this name. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Wolfgang Denk <wd@denx.de> Acked-by: Detlev Zundel <dzu@denx.de> Acked-by: Kim Phillips <kim.phillips@freescale.com> Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Anatolij Gustschin <agust@denx.de>
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a1b322a9 |
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01-Feb-2010 |
Ladislav Michl <ladis@linux-mips.org> |
ns16550: kick watchdog while waiting for a character ns16550 busyloops waiting for incoming byte causing watchdog to reboot while waiting for a key press. A call to WATCHDOG_RESET in NS16550_getc loop fixes it. Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
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660888b7 |
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30-May-2009 |
Tom Rix <Tom.Rix@windriver.com> |
ZOOM2 Add serial support. Zoom2 serial is in general supplied by one of the 4 UARTS on the debug board. The default serial is from the USB connector on left side of the debug board. The USB connector will produce 2 of the 4 UARTS. On your host pick the first enumeration. The details of the setting of the serial gpmc setup are not available. The values were provided by another party. The serial port set up is the same with Zoom1. Baud rate 115200, 8 bit data, no parity, 1 stop bit, no flow. The kernel bootargs are console=ttyS3,115200n8 Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
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200779e3 |
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03-Apr-2009 |
Detlev Zundel <dzu@denx.de> |
Rename common ns16550 constants with UART_ prefix to prevent conflicts Fix problems introduced in commit 7b5611cdd12ca0cc33f994f0d4a4454788fc3124 [inka4x0: Add hardware diagnosis functions for inka4x0] which redefined MSR_RI which is already used on PowerPC systems. Also eliminate redundant definitions in ps2mult.h. More cleanup will be needed for other redundant occurrences though. Signed-off-by: Detlev Zundel <dzu@denx.de>
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#
b4746d8b |
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11-Feb-2009 |
Mike Frysinger <vapier@gentoo.org> |
drivers/serial/ns16550: move ifdef into Makefile COBJS-$(...) Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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f5675aa5 |
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18-Feb-2009 |
Ron Madrid <ron_madrid@sbcglobal.net> |
Create configuration option for restricted ns16550 functions This patch will create a configuration option for a minimum configuration for the ns16550 serial driver at drivers/serial/ns16550.c and will apply this new configuration option to the SIMPC8313.h config file in order to fix the NAND bootstrap build error. This option will exclude all functions with exception of NS16550_putc and NS16550_init. This will be used primarily to save space and remove unused code from builds in which space is limited. Signed-off-by: Ron Madrid <ron_madrid@sbcglobal.net>
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6d0f6bcf |
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16-Oct-2008 |
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
rename CFG_ macros to CONFIG_SYS Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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#
7ec8bb15 |
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27-Dec-2007 |
Wolfgang Denk <wd@denx.de> |
OMAP5912: fix FIFO handling in UART driver According to the OMAP5912 Serial Interfaces Reference Guide (see http://focus.ti.com/lit/ug/spru760c/spru760c.pdf, page 150), the FIFO_EN enable bit in the FIFO Control Register (FCR) can only be changed when the baud clock is not running, i. e. when both DLL and DLH are set to 0. Thus make sure that DLL and DLH are 0 when writing the FCR. Signed-off-by: Wolfgang Denk <wd@denx.de>
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#
1378df79 |
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24-Nov-2007 |
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
drivers/serial : move serial drivers to drivers/serial Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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